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VLSI Design Assignment 3

The document outlines an assignment for EEPC24 VLSI Design, dated June 2, 2020, with a total of 20 marks. It requires students to write Verilog and VHDL programs for various digital components, including a full adder, full subtractor, multiplexers, decoders, and flip-flops. Each task is assigned specific marks, emphasizing both structural and behavioral design approaches.

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Bhavani Bhagyasree
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39 views1 page

VLSI Design Assignment 3

The document outlines an assignment for EEPC24 VLSI Design, dated June 2, 2020, with a total of 20 marks. It requires students to write Verilog and VHDL programs for various digital components, including a full adder, full subtractor, multiplexers, decoders, and flip-flops. Each task is assigned specific marks, emphasizing both structural and behavioral design approaches.

Uploaded by

Bhavani Bhagyasree
Copyright
© © All Rights Reserved
We take content rights seriously. If you suspect this is your content, claim it here.
Available Formats
Download as PDF, TXT or read online on Scribd

Date : 2-June-2020

EEPC24 VLSI DESIGN (ECE A)

ASSIGNMENT – 3 (Total marks – 20)

Write both verilog and VHDL program for the following :

1. Full adder (dataflow) – 2 marks


2. Full subtractor (structural) – 3 marks
3. 2:1 Multiplexer (structural,data flow,behavioral) – 6 marks
4. 3:8 Decoder (behavioural) – 2 marks
5. D flipflop (structural) – 3 marks
6. SR flipflop (behavioral) – 2 marks
7. 4-bit Up-down Counter (behavioural) - 2 marks

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