Digital Circuits and Logic Design
Lecture6-2 :Number Representation
and Arithmetic Circuits
112341 Digital Circuits and Logic Design 2010 (KTS)
Note: Half-Adder (HA)
112341 Digital Circuits and Logic Design 2010 (KTS)
Note: Full-Adder (FA)
112341 Digital Circuits and Logic Design 2010 (KTS)
Note: Full-Adder (FA)
112341 Digital Circuits and Logic Design 2010 (KTS)
Note: Alternative Implementation
of Adder
ci s si
s HA c
xi
HA c ci + 1
yi
(a) Block diagram
ci
si
xi
yi
ci + 1
(b) Detailed diagram
Figure 5.5. A decomposed implementation of the full-adder circuit.
Note:Ripple Carry Adder
xn – 1 yn – 1 x1 y1 x0 y0
c1
cn FA cn ” 1 c2 FA FA c0
sn – 1 s1 s0
MSB position LSB position
Figure 5.6. An n-bit ripple-carry adder.
112341 Digital Circuits and Logic Design 2010 (KTS)
Note:Adder/subtractor unit.
yn – 1 y1 y0
Add ⁄ Sub
control
xn – 1 x1 x0
cn n-bit adder c0
sn – 1 s1 s0
112341 Digital Circuits and Logic Design 2010 (KTS)
Carry-lookahead adder
Recall the carry-out
function for stage I can
be realized as
112341 Digital Circuits and Logic Design 2010 (KTS)
Carry-lookahead adder
1 = 1 + d
Carry-Out =1 if (g=1)
112341 Digital Circuits and Logic Design 2010 (KTS)
Carry-lookahead adder
1 = d+ 1
Carry-Out <= (Carry-In of 1) if (p=1)
112341 Digital Circuits and Logic Design 2010 (KTS)
Carry-lookahead adder
Why Generate and Propagate?
Why generate and propagate. If you look at the
Boolean expressions for pi and gi, you will see that
they both use only xi and yi. Neither depend on the
carry. Since xi and yi are available immediately, this
gives us hope that we can avoid waiting for carries.
112341 Digital Circuits and Logic Design 2010 (KTS)
Carry-lookahead adder
First, let's write the c1 which is the carry
out for the adding bit 0 of x and y.
c1 = g0 + p0c0
Now, we write it for c2.
c2 = g1 + p1c1
c2 = g1 + p1(g0 + p0c0)
= g1 + p1g0 + p1p0c0
112341 Digital Circuits and Logic Design 2010 (KTS)
Carry-lookahead adder
Let's go one more step further:
c3 = g2 + p2c2
= g2 + p2(g1 + p1g0 + p1p0c0)
= g2 + p2g1 + p2p1g0 + p2p1p0c0
Already, you should be able to detect a pattern.
By following the same pattern, you'd expect:
c4 = g3 + p3g2 + p3p2g1 + p3p2p1g0 + p3p2p1p0c0
112341 Digital Circuits and Logic Design 2010 (KTS)
Carry-lookahead (CLA) adder
n-bit Adder
112341 Digital Circuits and Logic Design 2010 (KTS)
Ripple-Carry adder
112341 Digital Circuits and Logic Design 2010 (KTS)
Carry-lookahead (CLA) adder
112341 Digital Circuits and Logic Design 2010 (KTS)
Ripple-carry adder critical path
112341 Digital Circuits and Logic Design 2010 (KTS)
Carry-lookahead critical path
112341 Digital Circuits and Logic Design 2010 (KTS)
x1 y1 x0 y0
g1 p1 g0 p0
c0
c2
c1
s1 s0
Figure 5.19. An alternative design for a carry-lookahead adder.
112341 Digital Circuits and Logic Design 2010 (KTS)
Carry-lookahead limitations
112341 Digital Circuits and Logic Design 2010 (KTS)
32-bit adder design
• Suppose we want to design a 32-bit adder
• Divide this adder into 4 blocks such that
– Bits b7-0 are block 0
– Bits b15-8 are block 1
– Bits b23-16 are block 2
– Bits b31-24 are block 3
• Each block can be constructed as an 8-bit CLA adder
– The carry-out signals from the four blocks are c8, c16,
c24, and c32
• There are 2 basic approaches for interconnecting
these four blocks
– Ripple-carry between blocks
– Second level carry-lookahead circuit
112341 Digital Circuits and Logic Design 2010 (KTS)
Ripple-carry between blocks
112341 Digital Circuits and Logic Design 2010 (KTS)
Second level carry-lookahead
circuit
112341 Digital Circuits and Logic Design 2010 (KTS)
Second level carry-lookahead
circuit
112341 Digital Circuits and Logic Design 2010 (KTS)
Hierarchical CLA analysis
• Assuming a fan-in constraint of four inputs,
the time to add two 32-bit numbers involves
Gj, and Pj require three gate delays, C8, C16, and
C24 are available after five gate delays. The time
needed to add two 32-bit numbers involves these
five gate delays plus two more to produce the
internal carries in blocks 1, 2, and 3, plus one
more gate delay (XOR) to generate each sum bit.
This gives a total of eight gate delays.
112341 Digital Circuits and Logic Design 2010 (KTS)
