Outline

VLSI Testing  Introduction

Design for Testability Basics
(積體電路測試) 
 Ad Hoc DFT
 Scan DFT
Chapter 4
Design for Testability

Ping-Liang Lai (賴秉樑)

Department of Electronic Engineering, Notional Chin-Yi University of Technology

P.L.Lai, VLSI Testing 2010 Chapter 4-2

Introduction Introduction
 History  History
 During early years, design and test were separate  Various testability measures & ad hoc testability enhancement
» The final quality of the test was determined by keeping track of the methods
number of defective parts shipped to the customer » To improve the testability of a design
» Defective parts per million (PPM) shipped was a final test score » To ease sequential ATPG (automatic test pattern generation)
» This approach worked well for small-scale integrated circuit » Still quite difficult to reach more than 90% fault coverage
 During 1980s, fault simulation was used  Structured DFT
» Failed to improve the circuit’s fault coverage beyond 80% » To conquer the difficulties in controlling and observing the internal
 Increased test cost and decreased test quality lead to Design states of sequential circuits
for Testability (DFT) engineering » Scan design is the most popular structured DFT approach
 Design for testability (DFT) has migration

P.L.Lai, VLSI Testing 2010 Chapter 4-3 P.L.Lai, VLSI Testing 2010 Chapter 4-4
 Outline What is Design for Test?
 Introduction  Also called design for testability
 Design for Testability Basics  “ A digital IC is testable if test patterns can be generated,
 Scan Cells Designs applied, and evaluated in such a way as to satisfy predefined
 Scan Architectures cost budget and time scale “, [Bennetts 1984]
 Scan Design Rules  That is design to facilitate testing
 Scan Design Flow  No formal definition for testability
 Special-Purpose Scan Designs  Possible definition, testability increases as the cost and time
 RTL Design for Testability of testing decreases
 Concluding Remarks

P.L.Lai, VLSI Testing 2010 Chapter 4-5 P.L.Lai, VLSI Testing 2010 Chapter 4-6

The Case for DFT Complexity: Gates per Pin

 Characteristics of present VLSI 800
 Smaller devices and higher operating frequency

in thousands of transitors per pin

700
 Higher device density that leads the designer to make more complex and lager

Testing complexity index,

circuits 600
 Lower power supply voltage, thus the circuit is becoming less immune to noise; 500
 Thinner and longer interconnect wires, ex., smaller wire cross sections have
caused an increase in resistance and capacitance 400
 Design paradigm of a system on a chip (SOC): this approach to integrating 300
several designs on the same chip involves the concept of reuse and brings new
challenges to testing 200
 Large number of gates per pin (the second and fifth characteristics) 100
 See next chart 0
0.25 0.18 0.13 0.1 0.07 0.05 0.035
 High cost of ATPG particularly for sequential circuits 1997 1999 2002 2005 2008 2011 2014
 Need for a shorter design & test cycle Feature size, m
 Shorter-time-to-market
Fig. 1. Testability index: number of transistors per pin

P.L.Lai, VLSI Testing 2010 Chapter 4-7 P.L.Lai, VLSI Testing 2010 Chapter 4-8
 Design for Testability Basics Outline
 Ad hoc DFT  Introduction
 Effects are local and not systematic  Design for Testability Basics
 Not methodical  Ad Hoc DFT
 Difficult to predict  Structured DFT
 A structured DFT
 Easily incorporated and budgeted
 Yield the desired results
 Easy to automate

P.L.Lai, VLSI Testing 2010 Chapter 4-9 P.L.Lai, VLSI Testing 2010 Chapter 4-10

Ad Hoc Approach Test Points Insertion (1/2)

OP

P
 Typical ad hoc DFT techniques W
P
U W U

 Insert test points

(a) Original circuit (b) Observation point
 Avoid asynchronous set/reset for storage elements
 Avoid combinational feedback loops P P
W U W
 Avoid redundant logic U

 Avoid asynchronous logic CP CP1

CP2
 Partition a large circuit into small blocks
(c) Controlling P to 0 (d) Controlling P to 0 and 1

OP
G1
A OP F
G4 Y
B G1
F
C Z A G2
G3 B
D H
G2 H
E G5 Z
C G3
(a) G
(b)
P.L.Lai, VLSI Testing 2010 Chapter 4-11 P.L.Lai, VLSI Testing 2010 Chapter 4-12
 Test Point Insertion (2/2) Segmentation
 A circuit has been divided into three subsections.
 Want to test the β partition

A R 
B
Z1
C
D
W
E

 OP2 shows the structure F Z2
of an observation, which is
composed of a multiplexer G
(MUX) and a D flip-flop. H V


P.L.Lai, VLSI Testing 2010 Chapter 4-13 P.L.Lai, VLSI Testing 2010 Chapter 4-14

Physical Partitioning (test β) Physical Partitioning (test α & γ)

A R  A R 
B B
Z1 Z1
C 0 C 1
S S
D 0 D 1
E 0 W S E 0 W S
 1 0  1 0
I I
1 1
F Z2 F Z2
G G
H V H V
 

P.L.Lai, VLSI Testing 2010 Chapter 4-15 P.L.Lai, VLSI Testing 2010 Chapter 4-16
 Sensitized Partitioning Verification Testing [McCluskey 1984]
 N-input circuit is partitioned into M segments each of which  An example, f(a,b,c)=a(b+c), g(b,c,d)=d⊕(b+c), h(e,d)=e+d
has Ki primary inputs, where Ki < N, thus i 1 2  2 N
iM K
Exhaustive test: 32 patterns
i

 The length of an exhaustive test: 256 patterns  One output at a time, the combined test will consist of 8, 8, and
 α : 8 patterns, β: 8 patterns, γ: 16 patterns (Total is 8+8+16=32) 4 patterns (20 patterns)


A R a
B f
Z1
C
S b
D
E 0 W S c
 I 1 0
g
F
1
Z2 d
G
H V

e h
P.L.Lai, VLSI Testing 2010 Chapter 4-17 P.L.Lai, VLSI Testing 2010 Chapter 4-18

Easily Testable Circuits Example: Adder or Array Multiplier

 Iterative Logic Arrays (ILAs)
V1 V2 V3
 Regularly structured circuits: RAMs, i-1 i i+1
FPGAs, array multipliers… a1 b1 Rc1 a2 b2 Rc2 a3 b3
Tc
 Test patterns is independent of the (a) c1
FA1
c2 c2
FA2
c3 c3
FA3
size of the circuit – the number of
s1 s2 s3
identical cells.
 Friedman called these ILAs C-
testable. Tc V1 Rc1 V2 Rc2 V1
0 00 0 00 0 00
 Two examples will be illustrated: i,j 0 01 0 01 0 01
 An array multiplier and a parity tree 0 10 0 10 0 10
0 11 1 00 0 11
1 00 0 11 1 00
1 01 1 01 1 01
1 10 1 10 1 10
(b) 1 11 1 11 1 11

P.L.Lai, VLSI Testing 2010 Chapter 4-19 P.L.Lai, VLSI Testing 2010 Chapter 4-20
 Easily Testable Designs Outline
 Parity tree  Introduction
R1100 R  Design for Testability Basics
T
S1010
1 T0110 S1010
S S  Ad Hoc DFT
2
(a)
T R
T
 Structured DFT
R1100 S
Labeling scheme R
Vi-1 S
Vi T (c)
Vi XOR Vi-1 S R
T
(b) R
Labeling process Labeled eight-inputs tree
Primary Inputs
Pattern R S T S R T S R
1 1 1 0 1 1 0 1 1
2 1 0 1 0 1 1 0 1
3 0 1 1 1 0 1 1 0
4 0 0 0 0 0 0 0 0

P.L.Lai, VLSI Testing 2010 Chapter 4-21 P.L.Lai, VLSI Testing 2010 Chapter 4-22

Structured Approach Structured Approach - Scan Design

 Scan design
 Convert the sequential design into a scan design  Assume that a stuck-at fault
 Three modes of operation f in the combinational logic
requires the primary input
» Normal mode
X3, flip-flop FF2, and flip-flop
− All test signals are turned off
FF3, to be set to 0, 1, and 0.
− The scan design operates in the original functional configuration
 The main difficulty in testing
» Shift mode a sequential circuit stems
» Capture mode from the fact that it is difficult
− In both shift and capture modes, a test mode signal TM is often used to control and observe the
to turn on all test-related fixes internal state of the circuit.

P.L.Lai, VLSI Testing 2010 Chapter 4-23 P.L.Lai, VLSI Testing 2010 Chapter 4-24
 Scan Basis (1/2) Scan Basis (2/2)
 Scan technology  Once initialized (first test mode), Normal mode is used to apply a
 Obtain Controllability and Observability for FFs pattern to the PIs, and the results are latched in the FFs
 It reduces sequential TPG to combinational TPG  The circuit is put in test mode again and the results scanned out
 With Scan, a synchronous sequential circuit works in two modes  Note that scan is usually inserted after the circuit is verified to be
 Normal mode and Test mode functionally correct
 In Test mode, all FFs are configured as a shift register, with Scan-
in and Scan-out routed to a (possibly dedicated) PI and PO
PIs POs PIs POs

PIs POs PIs POs

FFs FFs
FFs FFs

FFs FFs
Multiple Scan Partial Scan

Scan-in Scan-out
P.L.Lai, VLSI Testing 2010 Chapter 4-25 P.L.Lai, VLSI Testing 2010 Chapter 4-26

Scan-Path Design Scan Design Rules (1/2)

X1 Z1
X2
. Next State and Output Combinational Logic .
Z2  A designer needs to observe four rules during functional
. .
XK
. .
ZN
design:
 Only D-type master-slave FFs should be used
D Q D Q D Q
FF1 FF1 FF1 » No JK, toggle FFs or other forms of asynchronous logic
 At least on PI must be available for test
CLK
» As shown in previous circuit, the Scan-in and Scan-out pins can
be multiplexed (only one additional MUX is needed at Scan-out).
X1 Z1
X2 Z2 » Therefore, the only required extra pin is Scan-Enable, SE (or Test
.
. Next State and Output Combinational Logic .
. Control, TC)
. .
XK  All FFs must be controlled from PIs
SI
0
D Q
0
D Q
0
D Q
0 ZN » Simple circuit transformations can be used to change FFs whose
1 1 1 1
FF1 FF1 FF1 SO Clk is "gated" by an internal logic signal
 Clocks must not feed data inputs of the FFs
CLK
Scan-Enable (SE) » A race condition can result in normal mode otherwise
» This is generally considered good design practice anyway
P.L.Lai, VLSI Testing 2010 Chapter 4-27 P.L.Lai, VLSI Testing 2010 Chapter 4-28
 Scan Design Rules (2/2) Edge-triggered D flip-flop
 A trigger: Level and Edge Triggered  Master-slave D flip-flop
 The state of a latch or flip-flop is switched by a change of the  Two separate flip-flops
control input  A master flip-flop (positive-level triggered)
 Level triggered – latches  A slave flip-flop (negative-level triggered)
 Edge triggered – flip-flops

Master-slave D flip-flop

Clock response in latch and flip-flop

P.L.Lai, VLSI Testing 2010 Chapter 4-29 P.L.Lai, VLSI Testing 2010 Chapter 4-30

Scan Cell Designs (1/3) Storage Cells for Scan Designs (2/3)
 Common characteristics of all designs:  An implementation using two-port master-slave FF with a MUX
 Two mode: a normal input and a scan input
» Using a multiplexer or a two-clock system MD-FF
 A storage cell D 1D Q1
SI 2D Q2
» An edge-triggered FF, a master-slave FF or level-sensitive latches
Sel N’/T
controlled by clocks having ≧ 2 phases Q1’
 Focus only on D-FFs of the master-slave variety (edge-sensitive) CK Q2’

 Clocked D-latch and its symbol

CK D Next state of Q
D 0 X No change  A two-port clocked FF implementation
Q 1 0 Q=0; reset state 2P-FF
1 1 Q=1; set state D 1D
CK1 Q1
SI 2D Q2
Q’ D Q CK2
Q1’
CK
Q2’
CK Q’

P.L.Lai, VLSI Testing 2010 Chapter 4-31 P.L.Lai, VLSI Testing 2010 Chapter 4-32
 Storage Cells for Scan Designs (3/3) Scan Architectures
 To ensure race-free operation, use a 2-phase non-overlapping clk  Full-Scan Design
 All or almost all storage element are converted into scan cells
and combinational ATPG is used for test generation
 Partial-Scan Design
 A subset of storage elements are converted into scan cells and
sequential ATPG is typically used for test generation

MD-SR L
D 1D
SI 2D Q1
Sel N’/T Q2
Q1’
CK1
CK2 Q2’

P.L.Lai, VLSI Testing 2010 Chapter 4-33 P.L.Lai, VLSI Testing 2010 Chapter 4-34

Full-Scan Design Muxed-D Full-Scan Design

 All storage elements are replaced with scan cells  The three D flipflops, FF1, FF2 and FF3, are replaced with
 All inputs can be controlled three muxed-D scan cells, SFF1, SFF2 and SFF3,
 All outputs can be observed respectively
 Advantage
 Converts sequential ATPG into combinational ATPG
 Almost full-scan design
 A small percentage of storage elements are not replaced with
scan cells
» For performance reasons
− Storage elements that lie on critical paths
» For functional reasons
− Storage elements driven by a small clock domain that are deemed too
insignificant to be worth the additional scan insertion effort Sequential circuit example

P.L.Lai, VLSI Testing 2010 Chapter 4-35 P.L.Lai, VLSI Testing 2010 Chapter 4-36
 Muxed-D Full-Scan Design Muxed-D Full-Scan Design
 To form a scan chain, the scan input SI of SFF2 and SFF3 are connected  Primary inputs (PIs)  Primary outputs (POs)
to the output Q of the previous scan cell, SFF1 and SFF2, respectively. In  The external inputs to the circuit  The external outputs of the
addition, the scan input SI of the first scan cell SFF1 is connected to the  Can be set to any required logic circuit
primary input SI, and the output Q of the last scan cell SFF3 is connected values  Can be observed
to the primary output SO  Set directly in parallel from the  Are observed directly in
external inputs  Parallel from the external
X1 Z1  Pseudo primary inputs (PPIs, SI) outputs
X2 Z2
.
. Next State and Output Combinational Logic .
.  The scan cell outputs  Pseudo primary outputs (PPOs,
XK
. .  Can be set to any required logic SO)
values  The scan cell inputs
0 0 0 0
SI 1 D Q 1 D Q 1 D Q ZN  Are set serially through scan  Can be observed
1
FF1 FF2 FF2 SO chain inputs  Are observed serially through
scan chain outputs
CLK
Scan-Enable (SE)

(a) Muxed-D full-scan circuit

P.L.Lai, VLSI Testing 2010 Chapter 4-37 P.L.Lai, VLSI Testing 2010 Chapter 4-38

Muxed-D Full-Scan Design Muxed-D Full-Scan Design

X1 Z1
X2 Z2
.
. Next State and Output Combinational Logic .
.
. .
XK

0 0 0 0
SI 1 D Q 1 D Q 1 D Q 1
ZN Circuit Operation type Scan cell mode TM SE
FF1 FF1 FF1 SO
Normal Normal 0 0
CLK
Shift Operation Shift 1 1
Scan-Enable (SE)
Capture Operation Capture 1 0

Circuit operation type and scan cell mode

S: Shift operation / C: Capture operation / H: Hold cycle

P.L.Lai, VLSI Testing 2010 Chapter 4-39 P.L.Lai, VLSI Testing 2010 Chapter 4-40
 Example: Scan for Binary Counters Scan for Binary Counters
 3-bits Counter using D F/F: State table  3-bits Binary Counters
Next State and Output Combinational Logic
Present State Next State F/F Inputs As function of F(A,B,C)
DA=A⊕BC CUT
A B C +A +B +C DA DB DC
DA=A⊕BC
DB=B⊕C DB=B⊕C C
0 0 0 0 0 1 0 0 1 DC=C’
DC=C’
0 0 1 0 1 0 0 1 0 B
0 1 0 0 1 1 0 1 1 1
0 1 1 1 0 0 1 0 0
1 0 0 1 0 1 1 0 1
1 0 1 1 1 0 1 1 0
1 1 0 1 1 1 1 1 1 A
1 1 1 0 0 0 0 0 0 DC DB DA

CLK
P.L.Lai, VLSI Testing 2010 Chapter 4-41 P.L.Lai, VLSI Testing 2010 Chapter 4-42

S: Shift operation
Scan DFT of Binary Counters C: Capture operation
H: Hold cycle

C
B
IN/SI

V1:PI V2:PI

0 0 0 SE
0 S H C H S H C
1 1 1
1 CLK
A/SO
QC 0 1 0 0 H H 0 1 1 1 1

CLK QB × 0 1 1 H H H 0 1 1 1

SE QA × × 0 0 L L H H 0 0 1

V1:SI (PPI) V2:SI (PPI)

P.L.Lai, VLSI Testing 2010 Chapter 4-43 P.L.Lai, VLSI Testing 2010 Chapter
C (PO) observation SO 4-44
(PPO) observation
 Clocked Full-Scan Design Partial-Scan Design
 In a muxed-D fullscan circuit, a scan enable signal SE is used  Was once used in the industry long before full-scan design
 In a clocked fullscan design, two operations are distinguished by became the dominant scan architecture
properly applying the two independent clocks SCK and DCK during  Can also be implemented using muxed-D scan cells,
shift mode and capture mode clocked-scan cells, or LSSD scan cells
 Either combinational ATPG or sequential ATPG can be used

Clocked full-scan circuit

P.L.Lai, VLSI Testing 2010 Chapter 4-45 P.L.Lai, VLSI Testing 2010 Chapter 4-46

Partial-Scan Design Partial-Scan Design

 A scan chain is constructed with two scan cells SFF1 and SFF3,  Advantage
while flip-flop FF2 is left out  Reduce silicon area overhead
 It is possible to reduce the test generation complexity by splitting the single
clock into two separate clocks, one for controlling all scan cells, the other for  Reduce performance degradation
controlling all nonscan storage elements
 Disadvantage
 However, this may result in additional complexity of routing two separate clock
trees during physical implementation  Can result in lower fault coverage
 Longer test generation time
 Offers less support for debug, diagnosis and failure analysis

An example of muxed-D partialscan design

P.L.Lai, VLSI Testing 2010 Chapter 4-47 P.L.Lai, VLSI Testing 2010 Chapter 4-48