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8086 Microprocessor Overview

The 8086 is a 16-bit microprocessor designed by Intel in 1978. It has a 20-bit address bus that allows it to access up to 1MB of memory. It performs 16-bit arithmetic and logic operations in a single cycle, making it a 16-bit microprocessor. The block diagram shows its main components: the bus interface unit (BIU), execution unit (EU), registers, and control unit. The BIU calculates physical addresses to fetch instructions from memory. The control unit decodes opcodes and directs data movement and arithmetic logic unit (ALU) operations. Status and results are stored in flags registers.

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157 views10 pages

8086 Microprocessor Overview

The 8086 is a 16-bit microprocessor designed by Intel in 1978. It has a 20-bit address bus that allows it to access up to 1MB of memory. It performs 16-bit arithmetic and logic operations in a single cycle, making it a 16-bit microprocessor. The block diagram shows its main components: the bus interface unit (BIU), execution unit (EU), registers, and control unit. The BIU calculates physical addresses to fetch instructions from memory. The control unit decodes opcodes and directs data movement and arithmetic logic unit (ALU) operations. Status and results are stored in flags registers.

Uploaded by

Sukanti Pal
Copyright
© © All Rights Reserved
We take content rights seriously. If you suspect this is your content, claim it here.
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8086 Microprocessor

Definition: 8086 is a 16-bit microprocessor and was designed in 1978 by Intel.


Unlike, 8085, an 8086 microprocessor has 20-bit address bus. Thus, is able to
access 220 i.e., 1 MB address in the memory.
As we know that a microprocessor performs arithmetic and logic operations.
And an 8086 microprocessor is able to perform these operations with 16-bit data
in one cycle. Hence is a 16-bit microprocessor.
Block Diagram of 8086 Microprocessor

The figure below shows the block diagram of the architectural representation of
the 8086 microprocessor:
Working of 8086 Microprocessor

In the previous section, we have discussed the operation of various sections of


the BIU and EU. Now in this section, we will have a look at the overall
processing cycle of 8086 microprocessor.

So, basically, when an instruction is to be fetched from the memory, then firstly
its physical address must be calculated and this is done at the BIU.

The physical address of an instruction is given as:


PA = Segment address Χ 10 + Offset
For example: Suppose the segment address is 2000 H and the offset address is
4356 H. So, the generated physical address is 24356 H.
Here, the code segment register provides the base address of the code segment
which is combined with the offset address.
The code segment contains the instructions. Each time an instruction is fetched
the offset address inside the code segment gets incremented.

So, once the physical address of an instruction is calculated by the BIU of the
processor, it sends the memory location by the address bus to the memory.

Further, the desired instruction at that memory location which is present in the
form of the opcode is fetched by the microprocessor through the data bus.

Suppose the instruction is ADD BL, CL. But, inside the memory, it will be in
the form of an opcode. So, this opcode is sent to the control unit.
The control unit decodes the opcode and generates control signals that inform
the BL and CL register to release the value stored in it. Also, it signals the ALU
to perform the ADD operation on that particular data.
It is noteworthy that in any instruction, like ADD BL, CL. BL denotes the
destination of the result of the add operation.

This clearly shows that whatever, the operation is performed its result must be
stored in the first register i.e., BL for this particular example.

Let us take another example: Consider an instruction, ADD CL, 05H.


This means that the operand which is 05H is to be added with the data present in
the CL register and is stored in that particular register i.e., CL.

In such condition, the operand is not provided to the control unit as only the
opcode is required to be decoded by the CU. Hence the operand is directly
provided to the ALU.

Also, the status of this result is stored in the flag register. So, whenever, ALU
carries out an operation, it simultaneously generates the result as well as its
status.
It is to be noteworthy that in BIU, pipelining fails whenever there is branching
in the instruction. This is because generally instructions are present in a
sequential manner. But, sometimes the instructions are required to be executed
unsequentially.

However, in the queue, the instructions are stored sequentially. So, in case there
exist a need for any random instruction to be decoded. The opcode stored in the
queue will become invalid and must be cleared at that particular time.

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