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CMOS Logic: The Inverter

The document describes CMOS logic gates. It explains that a CMOS inverter consists of one nMOS transistor and one pMOS transistor. When the input is 0 the pMOS transistor is on and pulls the output high, and when the input is 1 the nMOS transistor is on and pulls the output low. It also describes a 2-input CMOS NAND gate using two nMOS transistors in series and two pMOS transistors in parallel, such that the output is 1 when any input is 0 and 0 when both inputs are 1. CMOS logic gates in general use nMOS transistors to pull the output low and pMOS transistors to pull it high.

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Carlos Saavedra
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100 views1 page

CMOS Logic: The Inverter

The document describes CMOS logic gates. It explains that a CMOS inverter consists of one nMOS transistor and one pMOS transistor. When the input is 0 the pMOS transistor is on and pulls the output high, and when the input is 1 the nMOS transistor is on and pulls the output low. It also describes a 2-input CMOS NAND gate using two nMOS transistors in series and two pMOS transistors in parallel, such that the output is 1 when any input is 0 and 0 when both inputs are 1. CMOS logic gates in general use nMOS transistors to pull the output low and pMOS transistors to pull it high.

Uploaded by

Carlos Saavedra
Copyright
© © All Rights Reserved
We take content rights seriously. If you suspect this is your content, claim it here.
Available Formats
Download as PDF, TXT or read online on Scribd

1.

4 CMOS Logic 9

1.4 CMOS Logic


1.4.1 The Inverter
Figure 1.11 shows the schematic and symbol for a CMOS inverter or NOT gate using one VDD
nMOS transistor and one pMOS transistor. The bar at the top indicates VDD and the trian-
gle at the bottom indicates GND. When the input A is 0, the nMOS transistor is OFF and
A Y
the pMOS transistor is ON. Thus, the output Y is pulled up to 1 because it is connected to
VDD but not to GND. Conversely, when A is 1, the nMOS is ON, the pMOS is OFF, and Y
is pulled down to ‘0.’ This is summarized in Table 1.1. GND
(a)
TABLE 1.1 Inverter truth table
A Y A Y
0 1
(b)
1 0
FIGURE 1.11
Inverter schematic
1.4.2 The NAND Gate (a) and symbol
(b) Y = A
Figure 1.12(a) shows a 2-input CMOS NAND gate. It consists of two series nMOS tran-
sistors between Y and GND and two parallel pMOS transistors between Y and VDD. If
either input A or B is 0, at least one of the nMOS transistors will be OFF, breaking the
path from Y to GND. But at least one of the pMOS transistors will be ON, creating a
path from Y to VDD. Hence, the output Y will be 1. If both inputs are 1, both of the nMOS Y
A
transistors will be ON and both of the pMOS transistors will be OFF. Hence, the output
will be 0. The truth table is given in Table 1.2 and the symbol is shown in Figure 1.12(b). B
Note that by DeMorgan’s Law, the inversion bubble may be placed on either side of the
gate. In the figures in this book, two lines intersecting at a T-junction are connected. Two (a)
lines crossing are connected if and only if a dot is shown.

TABLE 1.2 NAND gate truth table


(b)
A B Pull-Down Network Pull-Up Network Y
0 0 OFF ON 1 FIGURE 1.12 2-input NAND
gate schematic (a) and symbol
0 1 OFF ON 1 (b) Y = A · B
1 0 OFF ON 1
1 1 ON OFF 0

k-input NAND gates are constructed using k series nMOS transistors and k parallel Y
A
pMOS transistors. For example, a 3-input NAND gate is shown in Figure 1.13. When any
B
of the inputs are 0, the output is pulled high through the parallel pMOS transistors. When
C
all of the inputs are 1, the output is pulled low through the series nMOS transistors.

FIGURE 1.13 3-input NAND


1.4.3 CMOS Logic Gates gate schematic Y = A · B · C

The inverter and NAND gates are examples of static CMOS logic gates, also called comple-
mentary CMOS gates. In general, a static CMOS gate has an nMOS pull-down network to
connect the output to 0 (GND) and pMOS pull-up network to connect the output to 1
(VDD), as shown in Figure 1.14. The networks are arranged such that one is ON and the
other OFF for any input pattern.

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