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STA Screening Interview Questions

The document contains an interview transcript where the interviewee is asked questions about their experience with VLSI design and timing analysis. Some of the key topics discussed include the tools they worked with like Synopsys PrimeTime, timing constraints like multi-cycle paths, inputs for static timing analysis like libraries and SPEF files, and areas the interviewee needs to improve their knowledge such as specifying multi-cycle paths, timing loops, and suggestions given to physical design teams. The interviewer provides feedback that some of the interviewee's answers were incorrect or lacked detail.

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2K views2 pages

STA Screening Interview Questions

The document contains an interview transcript where the interviewee is asked questions about their experience with VLSI design and timing analysis. Some of the key topics discussed include the tools they worked with like Synopsys PrimeTime, timing constraints like multi-cycle paths, inputs for static timing analysis like libraries and SPEF files, and areas the interviewee needs to improve their knowledge such as specifying multi-cycle paths, timing loops, and suggestions given to physical design teams. The interviewer provides feedback that some of the interviewee's answers were incorrect or lacked detail.

Uploaded by

sunnygogineni
Copyright
© © All Rights Reserved
We take content rights seriously. If you suspect this is your content, claim it here.
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Download as DOCX, PDF, TXT or read online on Scribd
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1) Tell me about your academics and how you started your journey in VLSI?

2) Which tool you worked mostly on?


Ans) Synopsis Prime Time
3) But in resume you mentioned tempus also?
Ans) I have knowledge though I haven’t really worked in.
4) You mostly worked for Intel only right?
Ans) Yes
5) In resume you mentioned four projects with different technologies(7nm,10nm,16nm)? What is
the difference?
Ans) Latest technology means fast process technologies.
6) Is there any difference for your work routine?
Ans) Same kind of work no difference.
7) You mentioned portion level constraint development? What it means can you explain?
Ans) Mentioned timing constraints.
8) Those are timing constraints right?
Ans) Yes

I mentioned multi cycle paths and false paths.

9) How did you know is there requirement for multicycle paths?


Ans) I said what are multi cycle paths(failed).
10) Again I got Same question repeated?
Ans) I mentioned the command set_multicycle_path but wrong answer STA Engineer can’t
specify multicycle paths. The designer would do.
11) Where you see multicycle paths mentioned or how could you know requirement for multicycle
paths?
Ans) After timing report optimization I said. ( interviewer said if any requirement we suggest
the designer)
12) What are the different inputs required for STA?
Ans) Nellis
.lib files
SPEF
SDC
SDF(wrong mention)(interviewer mentioned we can prepare this file)

13) What are the contents of .lib files?Ans) Area,power,pin information.


14) What are power dissipation levels you seen in .lib files?
Ans) Skipped
15) What does SPEF file contains?
Ans) RC information
16) What do you mean by temperature inversion?
Ans) I explained PVT conditions( not justified with the answer)
17) What suggestions did you give to PD team as you mentioned in resume you closely worked with
PD team?
Ans) Skipped
18) What you mean by timing loops?
Ans) Skipped ( suggested me to learn about timing loops and combination loops)

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