EEB603: DIGITAL ELECTRONICS
LAB: 09
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Total Mark Awarded
[20 marks]
Student ID#:
Ritikh Deo: S2019006042
Title: Synchronous Counter
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EEB603: DIGITAL ELECTRONICS
LAB: 09
Aim: To design a synchronous counter using flip-flops.
Introduction:
A counter is a device which can count any particular event on the basis on how many times the
particular(s) events is occurred. In a digital logic system, this counter can count and store the number of
time any particular event or process have occurred, depending on a clock signal. Most common type of
counter is sequential digital logic circuit with a single clock input and multiple outputs. The outputs
represent binary or binary coded decimal numbers. Each clock pulse either increase the number or
decrease the number.
Synchronous generally refers to something which is coordinated with others based on time.
Synchronous signals occur at same clock rate and all the clocks follow the same clock rate and all the
clock follow the same reference clock. [1]
Materials:
DC Power Supply
Seven segment display ( Common Anode)
Resistors ( 11 x 270 and 1 x 1k )
LED ( x3)
Seven segment display driver (74LS47)
JK flip-flop ( x3)
AND gate
OR gate
CLOCK_VOLTAGE
Multisim software
Logic probe
Procedure:
A synchronous counter was designed using a JK flip-flop that would count in the sequence given in
table 01. The counter sequence 12 had been chosen. Which shows the sequence of (3, 2, 1, 7, 5), which
repeats itself. The circuit was connected using a Multisim software, using the components the decimal
output value of the circuit was displayed on a seven segment display. The K-map and further
calculations are shown in the result section.
Table 01
Group Counter Sequence Group Counter Sequence
1 1, 3, 7, 2, 0 7 7, 0, 3, 2, 1
2 2, 5, 0, 7, 3 8 6, 1, 5, 7, 2
3 0, 5, 3, 7, 1 9 3, 1, 5, 7, 0
4 4, 7, 5, 1, 6 10 5, 2, 7, 1, 4
5 7, 3, 0, 2, 4 11 0, 4, 3, 2, 7
6 5, 1, 3, 7, 2 12 3, 2, 1, 7, 5
The clock pulse was provided to the circuit and the binary output of the counter and the corresponding
output on the seven segment display was noted.
Result:
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EEB603: DIGITAL ELECTRONICS
LAB: 09
The design of a JK flip-flop circuit for the system given. [Counter Sequence: 3, 2, 1, 7, 5]
011
010
001
111
101
Truth table:
Counter q Q J2 K2 J1 K1 J0 K0
Sequenc Y2,Y1,Y0
e
3 011 010 0 d d 0 d 1
2 010 001 0 d d 1 1 d
1 001 111 1 d 1 d d 0
7 111 101 d 0 d 1 d 0
5 101 011 d 1 1 d d 0
Karnaugh Map:
_
J2= Y1Y0
Y1YO
Y2 00 01 11 10
X 1 0 0 0
X d d X 1
_
K2= Y1Y0
Y1YO
Y2 00 01 11 10
X d d d 0
X 1 0 X 1
J1= 1
Y1YO
Y2 00 01 11 10
X 1 d d 0
X 1 d X 1
_
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EEB603: DIGITAL ELECTRONICS
LAB: 09
K1= Y0 + Y2Y0
Y1YO
Y2 00 01 11 10
X d 0 1 0
X d 1 X 1
J0= 1
Y1YO
Y2 00 01 11 10
X d d 1 0
X d d X 1
_
K0= Y2Y1
Y1YO
Y2 00 01 11 10
X d d 1 0
X d d X 1
The circuit diagram:
File Information for: C:\Users\USER\Desktop\multisim\lab 09 synchronous counter
circuit.ms14Application: Multisim Application Version: 14.0.593Executable Version: 14.0.593.0
VCC
5.0V
J2
J1 J0
SET SET SET
J Q J Q J Q
CLK CLK CLK
KJK_FF ~Q
JK_FF ~Q
K KJK_FF ~Q
RESET RESET RESET
V1
1Hz
5V
Table 02:
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EEB603: DIGITAL ELECTRONICS
LAB: 09
Binary 7 segment display output
Output
011 3
010 2
001 1
111 7
101 5
Discussion:
Design a synchronous modulus 11 counter using JK flip-flops.
Truth table:
q Q J3 J2 J1 K 1 J0 K0
K3 K2
A B J K
0 0000 0001 0 d 0 d 0 d 1 d Karnaugh Map:
0 0 0 d
1 0001 0010 0 d 0 d 1 d d 1
0 1 1 d Y1Y0 J 3=
2 0010 0011 0 d 0 d d 0 1 d
1 0 d 1 Y2Y1Y0
3 0011 0100 0 d 1 d d 1 d 1
1 1 d 0 00 01 11 10
4 0100 0101 0 d d 0 0 d 1 d
5 0101 Y3Y2
0 0 0110
0 0 0 d d 0 1 d d 1
6 0110 0111 0 d d 0 d 0 1 d 00
0 0 1 0 01
7 0111 1000 1 d d 1 d 1 d 1
X X X X 11
8 1000 1001 d 0 0 d 0 d 1 d
d d d d 10
9 1001 1010 d 0 0 d 1 d d 1
10 1010 1011 d 0 0 d d 0 1 d
11 1011 0000 d 1 0 d d 1 d 1
Y1Y0 K 3= Y1Y0
00 01 11 10
Y3Y2
d d d d
00
d d d d 01
X X X X 11
0 0 1 0 10
_
Y1Y0 J 2=Y3Y1Y0
00 01 11 10
Y3Y2
0 0 1 0
00
d d d d 01
X X X X 11
0 0 0 0 10
_
Y1Y0 K 2=Y3Y1Y0
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EEB603: DIGITAL ELECTRONICS
LAB: 09
00 01 11 10
Y3Y2
d d d d
00
0 0 1 0 01
X X X X 11
d d d d 10
_ _
Y1Y0 J 1=Y3Y0+Y3Y2Y0
00 01 11 10
Y3Y2
0 1 d d
00
0 1 d d 01
X X X X 11
0 1 d d 10
_ _
Y1Y0 K1= Y3Y0+Y3Y2Y0
00 01 11 10
Y3Y2
d d 1 0
00
d d 1 0 01
X X X X 11
d d 1 0 10
Y1Y0 J0=1
00 01 11 10
Y3Y2
1 d d 1
00
1 d d 1 01
X X X X 11
1 d d 1 10
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EEB603: DIGITAL ELECTRONICS
LAB: 09
Y1Y0 K0=1
00 01 11 10
Y3Y2
d 1 1 d
00
d 1 1 d 01
X X X X 11
d 1 1 d 10
Circuit Diagram :( Modulus 11 Synchronous Counter)
File Information for: C:\Users\USER\Desktop\multisim\lab 09 synchronous counter
circuit.ms14Application: Multisim Application Version: 14.0.593Executable Version: 14.0.593.0
J3 J2 J0
SET SET J1 SET SET
J Q J Q J Q J Q
CLK CLK CLK CLK
JK_FF
K JK_FF
~Q KJK_FF ~Q K ~Q 5.0V K
JK_FF ~Q
RESET RESET RESET VCC RESET
V1
1Hz
5V
Conclusion:
To conclude, it can be said that synchronous counter has a common reference clock, that is, each JK
flip-flop has the same clock pulse. In designing the sequential counter in the lab 3-bits binary input has
been used, this is because if 4-bits are being used the last bit would always been low, thus it is not
included.
Reference:
[1]. Synchronous Counter: Definition Wikipedia
https://circuitdigest.com/tutorial/synchronus-counter
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EEB603: DIGITAL ELECTRONICS
LAB: 09
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