a 8-Bit 20 MSPS, 60 mW

Sampling A/D Converter

AD775
FEATURES FUNCTIONAL BLOCK DIAGRAM
CMOS 8-Bit 20 MSPS Sampling A/D Converter AV DD V IN DV DD

Low Power Dissipation: 60 mW 18 14 15 19 13 11

+5 V Single Supply Operation AV DD AD775 10 D7 (MSB)

Differential Nonlinearity: 0.3 LSB
9

3-STATE OUTPUT LATCHES

Differential Gain: 1% VRTS 16 15 COARSE 4

CORRECTION LOGIC
COMPARATORS 8
Differential Phase: 0.5 Degrees V RT 17
8 7
Three-State Outputs
On-Chip Reference Bias Resistors

RREF

LSB MULTIPLEXOR
FINE COMPARATORS 6
BANK A
Adjustable Reference Input 5

SWITCH
MATRIX
5

Video Industry Standard Pinout 255

4
V RB 23
Small Packages: FINE COMPARATORS
BANK B 3 D0 (LSB)
24-Pin 300 Mil SOIC Surface Mount V RBS 22

24-Pin 400 Mil Plastic DIP 1 OE

CLOCK LOGIC
AV SS

20 21 12 2 24

AV SS CLK DV SS

PRODUCT DESCRIPTION PRODUCT HIGHLIGHTS

The AD775 is a CMOS, low power, 8-bit, 20 MSPS sampling Low Power: The AD775 has a typical supply current of 12 mA,
analog-to-digital converter (ADC). The AD775 features a built- for a power consumption of 60 mW. Reference ladder current
in sampling function and on-chip reference bias resistors to pro- is also low: 6.6 mA typical, minimizing the reference power
vide a complete 8-bit ADC solution. The AD775 utilizes a consumption.
pipelined/ping pong two-step flash architecture to provide high Complete Solution: The AD775’s switched capacitor design
sampling rates (up to 35 MHz) while maintaining very low features an inherent sample/hold function: no external SHA is
power consumption (60 mW). required. On-chip reference bias resistors are included to allow
Its combination of excellent DNL, fast sampling rate, low dif- a supply-based reference to be generated without any external
ferential gain and phase errors, extremely low power dissipation, resistors.
and single +5 V supply operation make it ideally suited for a Excellent Differential Nonlinearity: The AD775 features a
variety of video and image acquisition applications, including typical DNL of 0.3 LSBs, with a maximum limit of 0.5 LSBs.
portable equipment. The AD775’s reference ladder may be con- No missing codes is guaranteed.
nected in a variety of configurations to accommodate different
input ranges. The low input capacitance (11 pF typical) provides Single +5 V Supply Operation: The AD775 is designed to oper-
an easy-to-drive input load compared to conventional flash ate on a single +5 V supply, and the reference ladder may be
converters. configured to accommodate analog inputs inclusive of ground.
The AD775 is offered in both 300 mil SOIC and 400 mil DIP Low Input Capacitance: The 11 pF input capacitance of the
plastic packages, and is designed to operate over an extended AD775 can significantly decrease the cost and complexity of
commercial temperature range (–20°C to +75°C). input driving circuitry, compared with conventional 8-bit flash
ADCs.

REV. 0
Information furnished by Analog Devices is believed to be accurate and
reliable. However, no responsibility is assumed by Analog Devices for its
use, nor for any infringements of patents or other rights of third parties
which may result from its use. No license is granted by implication or One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
otherwise under any patent or patent rights of Analog Devices. Tel: 617/329-4700 Fax: 617/326-8703
 (T = +258C with AV , DV = +5 V, AV , DV = 0 V, VRT = 2.6 V, VRB = +0.6 V,
AD775–SPECIFICATIONS CLOCK = 20 MHz unless otherwise noted)
A DD DD SS SS

AD775J
Parameter Min Typ Max Units
RESOLUTION 8 Bits
DC ACCURACY
Integral Nonlinearity (INL) +0.5 1.3 LSB
Differential Nonlinearity (DNL) ± 0.3 ± 0.5 LSB
No Missing Codes GUARANTEED
Offset
To Top of Ladder VRT –10 –35 –60 mV
To Bottom of Ladder VRB 0 +15 +45 mV
VIDEO ACCURACY1
Differential Gain Error 1.0 %
Differential Phase Error 0.5 Degrees
ANALOG INPUT
Input Range (VRT–VRB) 2.0 V p-p
Input Capacitance 11 pF
AC SPECIFICATIONS2
Signal-to-Noise and Distortion (S/(N + D))
fIN = 1 MHz 47 dB
fIN = 5 MHz 41 dB
Total Harmonic Distortion (THD)
fIN = 1 MHz –51 dB
fIN = 5 MHz –42 dB
REFERENCE INPUT
Reference Input Resistance (RREF) 230 300 450 Ω
Case 1: VRT = VRTS, VRB = VRBS
Reference Bottom Voltage (VRB) 0.60 0.64 0.68 V
Reference Span (VRT–VRB) 1.96 2.09 2.21 V
Reference Ladder Current (IREF) 4.4 7.0 9.6 mA
Case 2: VRT = VRTS, VRB = AVSS
Reference Span (VRT–VRB) 2.25 2.39 2.53 V
Reference Ladder Current (IREF) 5 8 11 mA
POWER SUPPLIES
Operating Voltages
AVDD +4.75 +5.25 Volts
DVDD +4.75 +5.25 Volts
Operating Current
IAVDD 9.5 mA
IDVDD 2.5 mA
IAVDD + IDVDD 12 17 mA
POWER CONSUMPTION 60 85 mW
TEMPERATURE RANGE
Operating –20 +75 °C
NOTES
1
NSTC 40 IRE modulation ramp, CLOCK = 14.3 MSPS.
2
fIN amplitude = 0.3 dB full scale.
Specifications subject to change without notice. See Definition of Specifications for additional information.

–2– REV. 0
 (TA = +258C with AVDD, DVDD = +5 V, AVSS, DVSS = 0 V, VRT = 2.6 V, VRB = +0.6 V, AD775
DIGITAL SPECIFICATIONS CLOCK = 20 MHz unless otherwise noted)
AD775J
Parameter Symbol DVDD Min Typ Max Units
LOGIC INPUT
High Level Input Voltage VIH 5.0 4.0 V
Low Level Input Voltage VIL 5.0 1.0 V
High Level Input Current
(VIH = DVDD) IIH 5.25 5 µA
Low Level Input Current
(VIL = 0 V) IIL 5.25 –5 µA
Logic Input Capacitance CIN 5 pF
LOGIC OUTPUTS
High Level Output Current
OE = DVSS, VOH = DVDD–0.5 V IOH 4.75 –1.1 mA
OE = DVDD, VOH = DVDD IOZ 5.25 16 µA
Low Level Output Current
OE = DVSS, VOL = 0.4 V IOL 4.75 3.7 mA
OE = DVDD, VOL = 0 V IOZ 5.25 16 µA

TIMING SPECIFICATIONS
Symbol Min Typ Max Units
Maximum Conversion Rate 20 35 MHz
Clock Period tC 50 ns
Clock High tCH 25 ns
Clock Low tCL 25 ns
Output Delay tOD 18 30 ns
Pipeline Delay (Latency) 2.5 Clock Cycles
Sampling Delay tDS 4 ns
Aperture Jitter 30 ps
Specifications subject to change without notice.

SAMPLE N+2
SAMPLE N SAMPLE N+1
VIN
tDS
tCH tCL

CLK

tC
tOD

OUT DATA N-3 DATA N-2 DATA N-1 DATA N

Figure 1. AD775 Timing Diagram

REV. 0 –3–
AD775
PIN DESCRIPTION

Pin No. Symbol Type Name and Function

1 OE DI OE = Low OE = High
Normal Operating Mode. High Impedance Outputs.
2, 24 DVSS P Digital Ground. Note: DVSS and AVSS pins should share a common ground plane on the circuit board.
3 D0 (LSB) DO Least Significant Bit, Data Bit 0.
4–9 D1–D6 DO Data Bits 1 Through 6.
10 D7 (MSB) DO Most Significant Bit, Data Bit 7.
11, 13 DVDD P +5 V Digital Supply. Note: DVDD and AVDD pins should share a common supply on the circuit board.
12 CLK DI Clock Input.
16 VRTS AI Reference Top Bias. Short to VRT for Self-Bias.
17 VRT AI Reference Ladder Top.
23 VRB AI Reference Ladder Bottom.
22 VRBS AI Reference Bottom Bias. Short to VRB for Self-Bias.
14, 15, 18 AVDD P +5 V Analog Supply. Note: DVDD and AVDD pins should share a common supply within 0.5 inches
of the AD775.
19 VIN AI Analog Input. Input Span = VRT–VRB.
20, 21 AVSS P Analog Ground. Note: DVSS and AVSS pins should share a common ground within 0.5 inches of the
AD775.
NOTE
Type: AI = Analog Input; DI = Digital Input; DO = Digital Output; P = Power.

PIN CONFIGURATION
MAXIMUM RATINGS*
(DIP and SOIC)
Supply Voltage (AVDD, DVDD) . . . . . . . . . . . . . . . . . . . . 7 V
Supply Difference (AVDD–DVDD) . . . . . . . . . . . . . . . . . . 0 V
Ground Difference (AVSS–DVSS) . . . . . . . . . . . . . . . . . . . 0 V
Reference Voltage (VRT, VRB) . . . . . . . . . . . . . . . . VDD to VSS
Analog Input Voltage (VIN) . . . . . . . . . . . . . . . . . . VDD to VSS
Digital Input Voltage (CLK) . . . . . . . . . . . . . . . . . VDD to VSS
Digital Output Voltage (VOH, VOL) . . . . . . . . . . . . VDD to VSS
Storage Temperature . . . . . . . . . . . . . . . . . . –55°C to +150°C
*Stresses above those listed under “Absolute Maximum Ratings” may cause
permanent damage to the device. This is a stress rating only and functional
operation of the device at these or any other conditions above those indicated in the
operational sections of this specification is not implied. Exposure to absolute
maximum rating conditions for extended periods may affect device reliability.

ORDERING GUIDE

Temperature Package Package

Model Range Description Option

AD775JN –20°C to +75°C 24-Pin 400 Mil Plastic DIP N-24B

AD775JR –20°C to +75°C 24-Pin 300 Mil SOIC R-24A

CAUTION
ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily
accumulate on the human body and test equipment and can discharge without detection. WARNING!
Although the AD775 features proprietary ESD protection circuitry, permanent damage may
occur on devices subjected to high energy electrostatic discharges. Therefore, proper ESD
ESD SENSITIVE DEVICE
precautions are recommended to avoid performance degradation or loss of functionality.

–4– REV. 0
 AD775
54 –30

48

42 –36

36
S/(N + D) – dB

THD – dB
30
–42
24

18
–48
12

0 –54
0.1 1 10 0.1 1 10
fIN – MHz fIN – MHz

Figure 2. S/(N + D) vs. Input Frequency at 20 MSPS Clock Figure 5. THD vs. Input Frequency at 20 MSPS Clock Rate
Rate (VIN = –0.3 dB) (VIN = –0.3 dB)

0 0

–10 –10

–20 –20

–30 –30

–40 –40
dB

–50
dB

–50

–60 –60

–70 –70

–80 –80

–90 –90

–100 –100
0 1.0 2.0 3.0 4.0 5.0 6.0 7.0 8.0 9.0 10.0 0 1.0 2.0 3.0 4.0 5.0 6.0 7.0 8.0 9.0 10.0
FREQUENCY – MHz FREQUENCY – MHz

Figure 3. Typical FFT at 1 MHz Input, 20 MSPS Clock Rate Figure 6. Typical FFT at 5 MHz Input, 20 MSPS Clock Rate
(VIN = –0.5 dB) (VIN = –0.5 dB)

+0.4 +1

+0.3

+0.2

+0.1
DNL – LSB

INL – LSB

0 0

–0.1

–0.2

–0.3

–0.4 –1
–FULLSCALE +FULLSCALE –FULLSCALE +FULLSCALE

Figure 4. Typical Differential Nonlinearity (DNL) Figure 7. Typical Integral Nonlinearity (INL)

REV. 0 –5–
AD775
DEFINITIONS OF SPECIFICATIONS Differential Phase
Integral Nonlinearity (INL) The difference in the output phase of a small high frequency
Integral nonlinearity refers to the deviation of each individual sine wave at two stated levels of a low frequency signal on which
code from a line drawn from “zero” through “full scale.” The it is superimposed.
point used as “zero” occurs 1/2 LSB before the first code tran-
Pipeline Delay (Latency)
sition. “Full scale” is defined as a level 1 1/2 LSB beyond the
The number of clock cycles between conversion initiation and
last code transition. The deviation is measured from the center
the associated output data being made available. New output
of each particular code to the true straight line.
data is provided every clock cycle.
Differential Nonlinearity (DNL, No Missing Codes)
Signal-to-Noise Plus Distortion Ratio (S/N+D)
An ideal ADC exhibits code transitions that are exactly 1 LSB
S/N+D is the ratio of the rms value of the measured input signal
apart. DNL is the deviation from this ideal value. It is often
to the rms sum of all other spectral components including har-
specified in terms of the resolution for which no missing codes
monics but excluding dc. The value for S/N+D is expressed in
(NMC) is guaranteed.
decibels.
Offset Error
Total Harmonic Distortion (THD)
The first code transition should occur at a level 1/2 LSB above
THD is the ratio of the rms sum of the first six harmonic com-
nominal negative full scale. Offset referred to the Bottom of
ponents to the rms value of the measured input signal and is ex-
Ladder VRB is defined as the deviation from this ideal. The last
pressed as a percentage or in decibels.
code transition should occur 1 1/2 LSB below the nominal
positive full scale. Offset referred to the Top of Ladder VRT is
defined as the deviation from this ideal.
Differential Gain
The percentage difference between the output amplitudes of a
small high frequency sine wave at two stated levels of a low fre-
quency signal on which it is superimposed.

THEORY OF OPERATION APPLYING THE AD775

The AD775 uses a pipelined two-step (subranging) flash archi- REFERENCE INPUT
tecture to achieve significantly lower power and lower input The AD775 features a resistive reference ladder similar to that
capacitance than conventional full flash converters while still found in most conventional flash converters. The analog input
maintaining high throughput. The analog input is sampled by range of the converter falls between the top (VRT) and bottom
the switched capacitor comparators on the falling edge of the (VRB) voltages of this ladder. The nominal resistance of the lad-
input clock: no external sample and hold is required. The coarse der is 300 ohms, though this may vary from 230 ohms to 450
comparators determine the top four bits (MSBs), and select the ohms. The minimum recommended voltage for VRB is 0 V; the
appropriate reference ladder taps for the fine comparators. With linearity performance of the converter may deteriorate for input
the next falling edge of the clock, the fine comparators determine spans (VRB–VRB) below 1.8 V. While 2.8 V is the recommended
the bottom four bits (LSBs). Since the LSB comparators require maximum ladder top voltage (VRT), the top of the ladder may be
a full clock cycle between their sampling instant and their deci- as high as the positive supply voltage (AVDD) with minimal lin-
sion, the converter alternates between two sets of fine compara- earity degradation.
tors in a “ping-pong” fashion. This multiplexing allows a new
input sample to be taken on every falling clock edge, thereby
providing 20 MSPS operation. The data is accumulated in the AVDD
correction logic and output through a three-state output latch 325Ω
on the rising edge of the clock. The latency between input sam- 16 AD775
pling and the corresponding converted output is 2.5 clock cycles.
17
All three comparator banks utilize the same resistive ladder for 0.1µF
their reference input. The analog input range is determined by
the voltages applied to the bottom and top of the ladder, and 300Ω
the AD775 can digitize inputs down to 0 V using a single sup-
ply. On-chip application resistors are provided to allow the *VALUES FOR
23 RESISTANCE
ladder to be conveniently biased by the supply voltage.
ARE TYPICAL
22
The AD775 uses switched capacitor autozeroing techniques to 0.1µF
cancel the comparators’ offsets and achieve excellent differential 90Ω

nonlinearity performance: typically ± 0.3 LSB. The integral AV SS

nonlinearity is determined by the linearity of the reference lad-

der and is typically +0.5 LSB. Figure 8. Reference Configuration: 0.64 V to 2.73 V
To simplify biasing of the AD775, on-chip reference bias resis-
tors are provided on Pins 16 and 22. The two recommended
configurations for these resistors are shown in Figures 8 and 9.

–6– REV. 0
 AD775
In the topology shown in Figure 8, the top of the ladder (VRT)
is shorted to the top bias resistor (VRTS) (Pin 17 shorted to Pin 10kΩ 10kΩ
NC 16 VRTS

16), while the bottom of the ladder (VRB) is shorted to the bot- +5V 0.1µF
17 VRT

tom bias resistor (VRBS) (Pin 23 shorted to Pin 22). This creates AD680 500pF
AD775
a resistive path (nominally 725 ohms) between AVDD and AVSS. 3 VIN
GND
VOUT 2
2
20Ω
422Ω
For nominal supply voltages (5 V and 0 V respectively), this 0.1µF
1 AD822 1

3
creates an input range of 0.64 V to 2.73 V. 0.1µF NC 22 VRBS
10kΩ
Both top and bottom of the reference ladder should be de- 23 VRB

500pF
coupled, preferably with a chip capacitor to ground to minimize 0.1µF

reference noise. 422Ω 10kΩ

6
NC = NO CONNECT

20Ω

The topology shown in Figure 9 provides a ground-inclusive 5

AD822 7

input range. The bottom of the ladder (VRB) is shorted to AVSS.

(0 V), while the top of the ladder (VRT) is connected to the on- 140Ω

board bias resistor (VRTS). This provides a nominal input range

of 0 V to +2.4 V for AVDD of 5 V. The VRBS pin may be left
floating, or shorted to AVSS. Figure 11. Reference Configuration: 0.7 V to 3.2 V

AVDD
ANALOG INPUT
325Ω The impedance looking into the analog input is essentially
16 AD775 capacitive, as shown in the equivalent circuit of Figure 12, typi-
cally totalling around 11 pF. A portion of this capacitance is
17
0.1µF parasitic; the remainder is part of the switched capacitor struc-
ture of the comparator arrays. The switches close on the rising
300Ω edge of the clock, acquire the input voltage, and open on the
clock’s falling edge (the sampling instant). The charge that must
*VALUES FOR
23 RESISTANCE
be moved onto the capacitors during acquisition will be a func-
AV SS ARE TYPICAL tion of the converter’s previous two samples, but there should be
22
no sample-to-sample crosstalk so long as ample driving imped-
90Ω
AVSS
ance and acquisition time are provided.

SWITCHES EACH
Figure 9. Reference Configuration: 0 V to +2.4 V AVDD
CLOCK CYCLE

More elaborate topologies can be used for those wishing to

provide an input span based on an external reference voltage. C2
The circuit in Figure 10 uses the AD780 2.5 V reference to
drive the top of the ladder (VRT), with the bottom (VRB) of the VIN
ladder grounded to provide an input span of 0 V to +2.5 V. This is C1 SWITCHES ON ALTERNATE
modified in Figure 11 to shift the 2.5 V span up 700 mV. CLOCK CYCLES

+5V AVSS C3

NC 1 AD780 8 NC C1 + C2 + C3 ≈ 11pF AD775

2 7 NC NC 16

NC 3 6 17 Figure 12. Equivalent Analog Input Circuit (VIN)

0.1µF
4 5 NC 0.1µF
AD775 For example, to ensure accurate acquisition (to 1/4 bit accuracy)
of a full-scale input step in less than 20 ns, a source impedance
NC 22 of less than 100 ohms is recommended. Figure 13 shows one
23 option of input buffer circuitry using the AD817. The AD817
NC = NO CONNECT
acts as both an inverting buffer and level shifting circuit. In
order to level shift the ground-based input signal to the dc level
Figure 10. Reference Configuration: 0 V to 2.5 V required by the input of the AD775, the supply voltage is resis-
tively divided to produce the appropriate voltage at the nonin-
The AD775 can accommodate dynamic changes in the reference verting input of the AD817. For most applications, the AD817
voltage for gain or offset adjustment. However, conversions that provides a low cost, high performance level shifter. The AD811
are in progress, including those in the converter pipeline, while is recommended for systems which require faster settling times.
the reference voltages are changing will be invalid.

REV. 0 –7–
AD775
1kΩ

100
1kΩ AD775
0V DC 1.5VDC 90
AD817 19 AIN

POWER DISSIPATION – mW
5.6kΩ
80
+5V

10µF 1kΩ 70

60

50
Figure 13. Level Shifting Input Buffer
The analog input range is set by the voltage at the top and bot- 40

tom of the reference ladder. In general, the larger the span

30
(VRT–VRB), the better the differential nonlinearity (DNL) of the 0 10 20 30 40
converter; a 1.8 V span is suggested as a minimum to realize CLOCK FREQUENCY – MHz
good linearity performance. AS the input voltage exceeds 2.8 V
(for AVDD = 4.75 V), the input circuitry may start to slightly Figure 15. Power Dissipation vs. Clock Frequency
degrade the acquisition performance. In applications sensitive to aperture jitter, the clock signal
should have a fall time of less than 3 ns. High speed CMOS
CLOCK INPUT logic families (HC/HCT) are recommended for their symmetri-
The AD775’s internal control circuitry makes use of both clock cal swing and fast rise/fall times. Care should be taken to mini-
edges to generate on-chip timing signals. To ensure proper mize the fanout and capacitive loading of the clock input line.
settling and linearity performance, both tCH and tCL times
should be 25 ns or greater. For sampling frequencies at or near DIGITAL INPUTS AND OUTPUTS
20 MSPS, a 50% duty cycle clock is recommended. For slower The AD775’s digital interface uses standard CMOS, with logic
sampling applications, the AD775 can accommodate a wider thresholds roughly midway between the supplies (DVSS, DVDD).
range of duty cycles, provided each clock phase is as least 25 ns. The digital output is presented in straight binary format, with
Under certain conditions, the AD775 can be operated at sam- full scale (1111 1111) corresponding to VIN = VRT, and zero
pling rates above 20 MSPS. Figure 14 shows the signal-to-noise (0000 0000) corresponding to VIN = VRB. Excessive capacitive
plus distortion (S/(N+D)) performance of a typical AD775 loading of the digital output lines will increase the dynamic
versus clock frequency. It is extremely important to note that the power dissipation as well as the on-chip digital noise. Logic
maximum clock rate will be a strong function of both temperature and fanout and parasitic capacitance on these lines should be mini-
supply voltage. In general, the part slows down with increasing mized for optimum noise performance.
temperature and decreasing supply voltage. The data output lines may be placed in a high output impedance
state by bringing OE (Pin 1) to a logic high. Figure 16 indicates
50 typical timing for access and float delay times (tHL and tDD
respectively). Note that even when the outputs are in a high
impedance state, activity on the digital bus can couple back to
40
the sensitive analog portions of the AD775 and corrupt conver-
sions in progress.
S(N + D) – dB

30

OE
20
tDD tHL

10 DATA DATA ACTIVE

OUTPUT THREE-STATE
(HIGH IMPEDANCE)

0 tDD = 18ns TYPICAL tHL = 12ns TYPICAL

0.1 1 10 100
CLOCK FREQUENCY – MHz
Figure 16. High Impedance Output Timing
Figure 14. S(N + D) vs. Clock Frequency (Temperature
= +25°C)
A significant portion of the AD775’s power dissipation is pro-
portional to the clock frequency: Figure 15 illustrates this
tradeoff for a typical part.

–8– REV. 0
 AD775
POWER SUPPLY CONNECTIONS AND DECOUPLING APPLICATIONS
The analog and digital supplies of the AD775 have been sepa- AD775 EVALUATION BOARD
rate to prevent the typically large transients associated with the Figures 17 through 22 show the schematic and printed circuit
on-chip digital circuitry from coupling into the analog supplies board (PCB) layout for the AD775 evaluation board. Referring
(AVDD, AVSS). However, in order to avoid possible latch-up to Figure 17, the input signal is buffered by U3, an AD817 op
conditions, AVDD and DVDD must share a common supply amp configured as a unity-gain follower. The signal is then ac-
external to the part, preferably a common source somewhere on coupled and dc-biased by adjusting potentiometer R14. Video
the PC board. and imaging applications would typically use a dc-restoration
Each supply should be decoupled by a 0.1 µF capacitor located circuit instead of the manual potentiometer adjustment. Q1, an
as close to the device pin as possible. Surface-mount capacitors, emitter-follower, buffers the input signal and provides ample
by virtue of their low parasitic inductance, are preferable to current to drive a simple low-pass filter. The filtering is included
through-hole types. A larger capacitor (10 µF electrolytic) to limit wideband noise and highlight the fact that the AD775
should be located somewhere on the board to help decouple can be driven from a nonzero source impedance.
large, low frequency supply noise. For specific layout informa- The reference circuit is similar to the one shown in Figure 11
tion, refer to the AD775 Evaluation Board section of the data with the exception that R1 and R2 allow precise adjustment of
sheet.
+5VA +5VA J8
CLOCK
( ) TP10
R15 CR1 5 6 9 8
499 1N4148
R14 TP9 R16 1/6 1/6
500 49.9 U7 U7
A
VCC D
J1 2
U3 R13 TP5
ANALOG TP2 20 VIN
INPUT Q1
AD817 6 2N3904
3 7 C8
4 22µF
TP1 R4
49.9 R11 C7 TP13
R12 75 10pF +5VA +5V ENABLE
C6 4.99k
C5 A C15 C18 P2-40 PIN IDC
A
VEE A VCC VEE 1
+5V
D D
AD775 74ALS541 C22
13 DVDD CLK 12 D

J10 1 20
14 AVDD DV DD 11 D G1 VCC D
TP4 2 19
VRT 15 AVDD D7 10 A1 G2
3 18
R8 R9 16 VRTS D6 9 A2 Y1
10k 10k J3 J6 U5 4 17
17 VRT D5 8 A3 Y2
C4 5 U6 16
A 390pF C13 18 AVDD D4 7 A4 Y3
+5VA
U1 A 6 15
19 VIN D3 6 A5 Y4
AD680 1/2 U2 R10 7 14
3 2 2 20 C14 20 AVSS D2 5 A6 Y5
VIN VOUT
AD822 1 8 13
GND 21 AVSS D1 4 A7 Y6
3 8 C9 A
C12 9 12
C2 1 J4 22 VRBS D0 3 A8 Y7
J5 11
A A 10
A 23 VRB DV SS 2 GND Y8
R3 +5VA
499 J2 24 DVSS OE 1
J9
C1 TP3 D D
VRB
R6 C3
A 10k 390pF
R2 R7 D
500 R5
10k 20
1/2 U2
6
A AD822 7
R1 5
500 4

A TP12 +5V
A J7
NOTES 40
D
VCC 78M05 C21 = 47µF ELECTROLYTIC CAPACITOR
TP6 +5VA UNLESS OTHERWISE NOTED
2 TP7 VCC U4 D
= 0.1µF CERAMIC CAPACITOR
1 VIN VOUT UNLESS OTHERWISE NOTED
C16 GND C11
4 TP8
3
C19 C20 A
6 TP11 VEE
5

VEE

Figure 17. AD775 Evaluation Board Schematic

REV. 0 –9–
AD775
VRT and VRB. Note that the VRT and VRB traces (see Figures 19 portant aspect is the power and ground distribution. While the
and 20) are run in parallel and in the same proximity. Any noise AD775 has separate analog and digital power and ground pins,
coupling is likely to be common mode to both signals and would the AD775 should be treated as an entirely analog component.
result in an offset error but not a gain error. The entire reference The ground plane is joined close to the ADC in order to main-
circuit is powered by a single +5 V supply. The minimum volt- tain a low potential difference across the analog and digital
age for VRB is determined by the impedance of the AD822 out- ground pins. Because the power and grounds are derived from a
put stage and the amount of current flowing through the common point, a slit in the ground plane is used to minimize
internal resistor ladder of the AD775. any interaction between the analog and digital return currents.
The sampling clock is buffered by U7, a 74HC04 inverter. It is The power for the AD775, AVDD and DVDD, are derived from
recommended that the output loading of the inverter is mini- the same supply. Separate traces are run to AVDD and DVDD
mized in order to maintain fast transition times on the clock. An and joined together at the source. While not used on the evalua-
additional inverter is used to provide a buffered clock signal tion board, a ferrite bead or inductor can effectively isolate noise
whose rising edges indicate that data is valid. A 74ALS541 generated by digital circuitry such as the output buffers. In cases
buffers the eight digital data outputs of the AD775 to improve where only a single supply is available, the inductor should not
the load driving capability. be placed between AVDD and DVDD. Instead, both supplies of
the AD775 should be connected together and isolated from
The multilayer PCB board layout shows some of the important entirely digital components.
design guidelines recommended for the AD775. The most im-

Table I. Components List

Reference Designator Description Quantity

R1, R2, R14 Potentiometer 3
R3, R15 Resistor, 1%, 499 Ω 2
R4, R13, R16 Resistor, 1%, 49.9 Ω 3
R5, R10 Resistor, 1%, 20 Ω 2
R6–R9 Resistor, 1%, 10 kΩ 4
R11 Resistor, 1%, 75 Ω 1
R12 Resistor, 1%, 4.99 kΩ 1
CR1 Diode, 1N4148 1
C1, C2, C5, C6, C9, C12–C15, C18
C20, C22, C23 Ceramic Cap, Z5U, 0.1 µF 13
C3, C4 Capacitor, Mica, 390 pF 2
C7 Capacitor, Mica, 10 pF 1
C8 Capacitor, Tantalum, 22 µF, 16 V 1
C11, C16, C19, C21 Capacitor, Alum. Electrolytic, 47 µF, 16 V 4
Q1 Transistor, 2N3904 1
U1 AD680JT 1
U2 AD822AN 1
U3 AD817AN 1
U4 78M05 1
U5 AD775 1
U6 74ALS541N 1
U7 74HC04N 1
J1, J8 BNC Jack 2

–10– REV. 0
 AD775

Figure 18. Silkscreen Layer (Not to Scale) Figure 20. Solder Side PCB Layout (Not to Scale)

Figure 19. Component Side PCB Layout (Not to Scale) Figure 21. Ground Plane PCB Layout (Not to Scale)

REV. 0 –11–
AD775

C1830–18–8/93
Figure 22. Power Plane PCB Layout (Not to Scale)

OUTLINE DIMENSIONS
Dimensions shown in inches and (mm).

Plastic DIP (N-24B) SOIC (R-24A)

24 13
0.346 (8.80) 24 13
PIN 1 0.221 (5.6)
0.330 (8.40)
PIN 1 0.205 (5.2)
1 12
1 12 0.327 (8.3)
0.295 (7.5)

PRINTED IN U.S.A.
1.205 (30.60)
0.020 0.400 (10.16)
1.185 (30.10)
(0.50)
MIN 0.089 (2.25)
0.200 (5.05) 0.195 (4.95)
0.606 (15.4) 0.067 (1.70)
0.125 (3.18) 0.125 (3.18) 0.586 (14.9) 0.272 (6.9)
0.118 (3.00)
MIN
15° 0.014 (0.35)
0.024 (0.60) 0.100 0.053 (1.35) SEATING 0° 0.008 (0.20)
0.016 (0.40) (2.54) 0.041 (1.05) PLANE 0.012 (0.12) 0.050 (1.27) 0.022 (0.55) 0.028 (0.7)
BSC 0.012 (0.30)
0.002 (0.05) BSC 0.014 (0.35) 0.012 (0.3)
0.006 (0.15)

–12– REV. 0