Session 2019-20 (Even Semester)
EC 562 Digital Design and Modeling with VHDL
ASSIGNMENT NO. – 1
Date of Release: June 15, 2020
Date of Final submission: June 21, 2020
Q.1 Explain with examples different data types available in VHDL.
Q.2 What is difference between signal and variable? Explain their usage with an appropriate
example.
Q.3 Draw schematic diagram and write a structural code for 3:8 decoder. How will you use it
as a component and design a 5:32 decoder?
Q.4 Explain various looping constructs available in VHDL with suitable examples.
Q.5 Write three different architectures for a single entity of 8:3 priority encoder. Explain use
of configuration construct under such a scenario.
Instruction to Submit Assignment:
1. You must answer all questions with legitimate hand writing.
2. Take a photograph of self-written solution sheets.
3. Convert the file in PDF format and upload your solution.