IEEE Journal on Exploratory Solid-State Computational Devices and Circuits

Received 14 April 2020; revised 14 May 2020; accepted 27 May 2020.

Date of publication 1 June 2020; date of current version 2 July 2020.
Digital Object Identifier 10.1109/JXCDC.2020.2999270

Benchmarking and Optimization of

Spintronic Memory Arrays
YU-CHING LIAO 1 (Graduate Student Member, IEEE), CHENYUN PAN 2 (Member, IEEE),
and AZAD NAEEMI1
1 School of Electrical and Computer Engineering, Georgia Institute of Technology, Atlanta, GA 30332 USA
2 Department of Electrical Engineering, The University of Texas at Arlington, Arlington, TX 76010 USA

CORRESPONDING AUTHOR: Y.-C. LIAO (yliao48@[Link])

This research is supported by ASCENT in the JUMP program through Semiconductor Research Corporation. The task number are 2667.060
and 2776.061.

ABSTRACT In this article, we present a cross-layer optimization and benchmarking of various spintronic
memory devices, including spin-transfer-torque magnetic random access memory (STT-MRAM), spin-orbit-
torque (SOT) MRAM, voltage-controlled exchange coupling (VCEC) MRAM, and magnetoelectric (ME)
MRAM. Various material, device, and circuit parameters are optimized to maximize array-level READ and
WRITE performances and to benchmark spintronic devices against static random access memory (SRAM). It is
shown that the optimized parameters, such as magnetic tunnel junction (MTJ) oxide thickness or transistor
size, are quite different for various device options. The optimal oxide thickness of VCEC-MRAM is 1.6 nm
because it is a voltage-controlled device; thus, thicker oxide gives smaller READ energy-delay product (EDP),
whereas, for STT-MRAM, the optimal oxide thickness is 1.3 nm to keep the WRITE voltage low while avoiding
READ disturbs. In addition, we find that the co-optimization of material, device, and circuit analyses are critical
because it is not enough to identify the most promising material for various device options with only material-
or device-level metrics. For instance, SOT materials with the highest spin conductivity may not result in the
best array-level WRITE performance because of their large resistivity and, in some cases, READ disturb issues.
We also present a new design and cell layout for ME-MRAM in which the number of access transistors
depends on the WRITE voltage. The benchmarking results show that SOT-MRAM can be fast and low energy
but would suffer from a 25% larger cell area compared with STT-MRAM. VCEC-MRAM can be denser than
STT-MRAM (2T1MTJ) and dissipate less energy but would suffer from slower READ operations because of
its large oxide thickness. ME-MRAM can be fast, low energy, and dense compared with all other options.

INDEX TERMS Magnetoelectric (ME), nonvolatile memory, spintronics, spin-orbit torque (SOT),
spin-transfer torque (STT), voltage-controlled exchange coupling (VCEC).

I. INTRODUCTION challenges remain for the creation of scalable and reliable

S PINTRONIC devices are promising candidates for

embedded memory due to their nonvolatility and small
footprint compared with static random access memory
STT-MRAM. It is generally not energy efficient to switch
a magnet using spin-transfer torque because large WRITE
currents for several nanoseconds are required. Hence, rela-
(SRAM) [1]. They also offer high endurance and faster WRITE tively large access transistors must be used, and reliability
operations compared with resistive random access mem- issues may arise when large currents pass through the oxide
ory (RRAM) and embedded nand flash and better scalability layers in MTJs [4]. Finally, the fact that the WRITE and
of their WRITE currents compared with phase-change memory READ currents pass through the same path does not allow
(PCRAM) [2]. Spin-transfer-torque magnetic random access for the independent optimization of the READ and WRITE
memory (STT-MRAM), which is gradually moving into pro- operations.
duction, uses a two-terminal magnetic tunnel junction (MTJ). To address these challenges, other MRAM device options
When large currents pass through the device, spin-polarized have been proposed based on various WRITE mechanisms,
electrons are injected from a fixed ferromagnet to a free such as spin-orbit torque (SOT-MRAM), voltage-controlled
ferromagnet. The switching of the free ferromagnet depends magnetic anisotropy (VCMA-MRAM) [5], voltage-
on the direction of the current and the magnetic order of controlled exchange coupling (VCEC-MRAM) [6], and
the fixed ferromagnet. Recently, perpendicular MTJs with magnetoelectric effect (ME-MRAM) [7]. In all these devices,
diameters as small as 16 nm and WRITE currents as low as the READ operation is based on the tunnel magnetoresis-
∼40–90 µA [3] have been reported. However, several major tance (TMR) effect [8], [9].

This work is licensed under a Creative Commons Attribution 4.0 License. For more information, see [Link]
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 IEEE Journal on Exploratory Solid-State Computational Devices and Circuits

FIGURE 1. Schematics and layouts of various spintronic memory cells. (a) STT-MRAM or VCEC-MRAM. (b) SOT-MRAM. (c) ME-MRAM.

SOT-MRAM utilizes an inherently more energy-efficient and ME materials have been reported since then, and several
mechanism compared with STT-MRAM; hence, it may important factors, such as current splitting between the SOT
permit faster and more energy-efficient operations. and ferromagnet layers, domain nucleation/propagation and
Theoretically, when a charge current IC passes through an thermal noise during the switching process, and the impact of
SOT channel, the generated spin current IS is written as field-like torque, have not been considered in these studies.
} WFM The array-level potential performances of VCEC-MRAM
IS = θSH IC (1) and ME-MRAM have not been quantified. Finally, a com-
2e tSO
prehensive cross-layer optimization and benchmarking of
where e is the electron charge, h̄ is the reduced Planck’s all MRAM technology options are lacking. Each spintronic
constant, WFM is the width of the ferromagnet, tSO is the memory option offers vastly different tradeoffs at the mate-
thickness of the SOT material, θSH is the spin Hall angle of rial, device, and circuit levels, and a fair comparison requires
the SOT material, and the length of the free layer ferromagnet comprehensive modeling and optimization at all levels.
is equal to the width of the SOT material. With the right To fill these gaps, this article presents a uniform cross-
geometrical and material parameters, this spin current can layer optimization and benchmarking of various spintronic
be several times larger than the spin-polarized current in memory devices in a 256 × 128 bits array. The simula-
STT-MRAM whose upper limit is [10] tion framework uses SPICE simulations, analytical equations,
} a macrospin model, and micromagnetic simulations. We also
Is = Ic . (2)
2e explore various material candidates for SOT-MRAM, such as
In addition to the current-controlled devices, researchers are heavy metals, alloys, semimetals, and topological insulators.
pursuing voltage-controlled devices that are potentially more Note that VCMA-MRAM has not been considered in this
energy efficient because of the much lower WRITE currents work since it requires precise pulsewidth control [18], [19],
involved. VCEC-MRAM is a bidirectional voltage-controlled or it needs to be combined with STT [19], [20] or SOT for
device in which the polarity of the applied voltage across a deterministic magnetization switching. The parameters for
the MTJ determines the magnetization direction of the free each type of MRAM are chosen from the recent state-of-the-
ferromagnet. The ab initio calculations show that the applied art experiments, as will be discussed in Table 2.
voltage close to the oxide interface can modulate the inter- The rest of this article is organized as follows. Section II
layer exchange coupling in the synthetic antiferromagnet, shows the schematics and layout of various types of memory
thus changing the magnetization direction of the free ferro- cells. Section III describes the modeling methods for the
magnet [6]. Another candidate is ME-MRAM that uses multi- READ and WRITE operations. Section IV discusses the results
ferroic materials, such as BiFeO3 [11], [12] or Cr2 O3 [13], in and comparisons in terms of READ/WRITE delay/energy for
contact with a free ferromagnet of an MTJ. Once the applied various spintronic memory cells. Section V summarizes the
voltage across the ME layer is larger than its coercive volt- findings and suggests future directions.
age, its ferroelectric polarization and the antiferromagnetic
order will switch. If the interface exchange coupling or the II. SCHEMATICS AND LAYOUT
exchange bias effect is large enough, the magnetic order of The two key factors needed for array-level modeling of
the adjacent ferromagnet will also switch. MRAM options are the cell area and the number of transistors
To understand the limits and opportunities offered by per cell as they determine the interconnect lengths and para-
these novel WRITE mechanisms, various materials, technol- sitic capacitances. The schematics and the layout designs of
ogy, and design parameters must be optimized, and var- the spintronic memory cells are shown in Fig. 1. We define
ious tradeoffs must be evaluated. Prior publications have F = 30 nm as the half-metal pitch in the 15-nm CMOS
compared the potential performance of SOT-MRAM versus technology is consistent with the beyond-CMOS benchmark-
STT-MRAM [14], [10]. In addition, researchers have studied ing presented in [21]. We also consider various numbers of
several spintronic device candidates and have quantified their WRITE transistors with a fixed current flowing per transistor
array level performances [15]–[17]. However, many new SOT to evaluate the WRITE speed.

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Liao et al.: Benchmarking and Optimization of Spintronic Memory Arrays

FIGURE 3. Schematic of the ME-MRAM in an array level with

(a) one-access transistor or (b) separated access transistors for
READ and WRITE operations. (a) 2T1MTJ. (b) 1T1MTJ.
TABLE 1. Modeling parameters used in READ and WRITE
operations.
FIGURE 2. Layout of STT-MRAM with (a) one, (b) two, (c) three,
and (d) four access transistors, and their cross-sectional areas
at line A. (a) 1T1MTJ. (b) 2T1MTJ. (a) 3T1MTJ. (a) 4T1MTJ.

For the STT-MRAM and the VCEC-MRAM, the layout

area can be as small as 12 F 2 if only one-access transistor
is used since the READ and WRITE operations share the same
path. Layout designs of STT-MRAM with one to four access
transistors are shown in Fig. 2, as will be discussed later
in Section IV For the SOT-MRAM, since the READ and the
WRITE operations are separated, two transistors are needed to
avoid sneak currents. The layout area unavoidably increases
to 20 F 2 in the case of one WRITE access transistor.
For the ME-MRAM, the READ and WRITE operations are we simulate the READ and WRITE performances of SRAM
separated by two access transistors to prevent READ disturb, considering that the fin ratio of the pull-down, pass gate,
as shown in Fig. 3(a). The cell area is 20 F 2 , which is similar and the pull-up transistors is [Link] using a 16-nm predictive
to the SOT-MRAM using one WRITE and one READ access technology model (PTM) established by Arizona State Uni-
transistor, as shown in the right-hand side of Fig. 1(c). Inter- versity [23]. The current-latch-based sense amplifier is used
estingly, when the WRITE voltage (VWRITE ) of the ME material to simulate the READ performance of SRAM.
is as large as 0.4–0.5V, which is higher than the typical READ
voltage of an MTJ (∼0.1–0.15 V), a single access transistor A. READ OPERATION
can be used for both READ and WRITE operations, as shown Following our previous work [15], [16], we use HSPICE to
in Fig. 3(b). In this one-access transistor scheme, a leakage simulate the READ delay and energy with the READ circuit
current passes through the MTJ during the WRITE operation adapted from [24], and the offset voltages of the sense ampli-
and the READ voltage is applied to the ME stack. As will fier are chosen to be 50 mV. The READ delay time is estimated
be discussed later, the leakage current during the WRITE as tREAD = tWL + tsense , where tWL = 0.7 Rdrive CWL +
operation can be kept small by a proper choice of MTJ oxide 0.4RWL CWL is the delay time of the word line (WL), and
thickness, and a WRITE voltage larger than 0.4 V would ensure tsense is the delay time of the sense amplifier. Here, Rdrive is the
no READ disturbs. The benefit of using a one-access transistor resistance of the driver that is a 5× minimum-sized inverter,
comes with a smaller layout area of the ME-MRAM down to RWL is the interconnect resistance, and CWL is the intercon-
12 F 2 , as shown in the left-hand side of Fig. 1(c). nect capacitance.
III. MODELING APPROACHES
The READ energy is estimated as
We consider a 256 × 128-bits array memory, including EREAD = 2VREAD Ibias tREAD + EWL + ESA (3)
the memory cells, sense amplifiers, and parasitics, such as where the first term is the Joule heating associated with the
wire resistances and wire capacitances in our simulations. currents passing through the controlled and the reference
The simulation parameters are listed in Table 1. To com- MTJs, EWL = (CWL /Nbit + Ctran )VREAD 2 is the energy dissi-
pare various spintronic memory cells using different WRITE pation to charge the WL and the associated gate capacitance
mechanisms, the oxide thickness must be optimized since per cell, and ESA = PSA tREAD is the energy dissipation of the
it affects the READ performances of all the options and the output latch of the sense amplifier. PSA is the sense amplifier
WRITE performances of STT-MRAM and VCEC-MRAM. power, which is estimated to be 0.3 µW based on the previous
We will later show that the oxide thickness of SOT-MRAM SPICE simulation results [15]. Note that the READ energy is
and ME-MRAM can be optimized especially for the READ calculated for a single cell in a row by averaging the READ
operation to take advantage of the separated READ and WRITE energy of the selected row per column.
paths. As we vary the MTJ oxide thickness, we use the
measured resistance–area (RA) product reported in [22]. B. WRITE OPERATION
In addition, to compare the performances of spintronic The WRITE delay and energy of a single bit in an array
memory devices in the embedded memory application, are calculated specifically for each type of memory cells,
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TABLE 2. Model dimensions and parameters of various spintronic memory cells.

as explained in the following. We assume that bits in each row such as spin scattering and spin mixing, which become
are written simultaneously and calculate the WRITE energy prominent when the thickness of the SOT material is too
per bit by dividing the WRITE energy of an entire row by the thin [32]–[35]. To switch a ferromagnet with perpendicular
number of cells per row. The parameters that we use and the magnetic anisotropy (PMA) using spin-orbit torque, an exter-
corresponding references are listed in Table 2. nal magnetic field is needed to break the symmetry. Other
approaches, such as using antiferromagnet/ferromagnet het-
1) STT-MRAM AND VCEC-MRAM erostructures [36], wedging the interface [37], or utilizing
For both the STT-MRAM and the VCEC-MRAM, the WRITE interlayer exchange coupling [38], have also been proposed.
current passes through the MTJ, and the set and reset are However, much work is needed in this area, and here, we only
determined by the applied voltage on the BL and the SL. consider SOT-MRAM with in-plane ferromagnets.
For the set operation, BL is biased to VWRITE , while SL is The WRITE access time is estimated as tWRITE = tWL +
connected to the ground, and the reset operation is done the tBL + tmag , where tmag is calculated by micromagnetic simu-
other way around. The WRITE access time is estimated as lations using the Object Oriented MicroMagnetic Framework
tWRITE = tWL + tBL + tmag where tWL is the delay time to (OOMMF) [39]. This is because macrospin models tend to
charge WL, tBL is the delay time to charge or discharge BL, overestimate the required currents for spin-orbit switching
and tmag is the magnet switching time that is calculated by of ferromagnets since they neglect the domain nucleation
a macrospin model [25]. We have validated the models with and propagation during switching [40]. We also validate
the experimental results from [3]. Note that since there are our micromagnetic model by comparing it with the magnet
no experimental data available on the magnet switching time switching times reported in the experiments in [26]. The
of the VCEC-MRAM, three hypothetical values of 5, 10, and WRITE access energy is then calculated as
20 ns are considered.
The WRITE access energy is calculated as 2
EWRITE = IWRITE (RBL + RSL + Rtran + RSOT )
2
EWRITE = IWRITE (RBL +RSL +Rtran +RMTJ )·tmag ·tmag + (CWL /Nbit + Ctran )Vdd
2 2
+ (CBL + Ctran )VWRITE
+(CWL /Nbit +Ctran )Vdd
2
+ (CBL +Ctran /3)VWRITE
2
. (5)
(4) where RSOT is the resistance of the SOT material, and the
effective spin-polarized current is IS = }/2e(WFM /tSO )θSH IC
The first term is the Joule heating energy associated with
and Ic = Ic,tot × 1/(1 + s). Here, IC,tot is the total charge
the WRITE current (IWRITE ) flowing through the corresponding
current flowing through the WRITE access transistor, IC is the
BL, SL, select transistor, and MTJ. The second term is the
effective charge current flowing through the SOT channel,
energy dissipation to charge the WL capacitance and the
and the ratio of the shunting current (Ishunt ) to IC can be
associated gate capacitance (Ctran ) to Vdd . The last term is
written as
the energy dissipation to charge the capacitance associated
with the BL and the total capacitance associated with the Ishunt ρSO tFM
s= = (6)
source/drain of transistors connected to the BL, which is Ic tSO ρFM
approximately Ctran /3 per transistor. where ρSO is the resistivity of the SOT material, ρFM is the
2) SOT-MRAM resistivity of the ferromagnet, tFM is the thickness of the
We consider four types of SOT materials: 1) heavy metals ferromagnet, and tSO is the thickness of the SOT material.
such as W [26], [27]; 2) alloys such as Au0.25 Pt0.75 [28]; To reduce the current shunting effect, the thickness of the
3) semimetals such as WTe2 [29]; and 4) topological insu- ferromagnet is chosen to be 2 nm except for the case of
lators such as Bi0.9 Sb0.1 [30] and Bix Se1−x [31]. To perform Bi0.9 Sb0.1 , and a 4-nm-thick MnGa is used. The ratio between
the WRITE operation, the WRITE access transistor is turned on, the length and the width of the ferromagnet must be increased
and a charge current flows through the SOT channel, which to four in order to maintain a sufficient energy barrier of
generates a transverse spin current into the MTJ. The ferro- Eb ∼ 40 kT.
magnet shunts a fraction of the current flowing in the SOT
channel. This shunt current needs to be accounted for when 3) ME-MRAM
the conductivity of the magnet is comparable to or smaller Although current experiments on multiferroic materials have
than that of the channel. Another factor that affects the current been on micrometer samples, here, we assume that the device
efficiency is the spin transparency at the interface effects, lateral dimensions can be scaled down to below 100 nm to

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Liao et al.: Benchmarking and Optimization of Spintronic Memory Arrays

fit in our compact layout designs. We also assume the ME

material to be intrinsically an insulator (such as BiFeO3 or
Cr2 O3 ).
The total WRITE access time is estimated as
tWRITE = tWL + tBL + 0.7 (RBL + Rtran ) CAFM + tmag (7)
where CAFM is the capacitance of the antiferromagnet.
In this study, CAFM is calculated as κAFM · A/d, where
κAFM = 40 is the dielectric constant of BiFeO3 [41], A is
the area of BiFeO3 , and d = 30 nm is the thickness of
BiFeO3 thin film. Since there is no experimental report about
the switching time of the ferromagnet using the ME effect,
we consider three hypothetical tmag values of 1, 2, and 5 ns,
which are longer than the theoretical switching time limit
from the previous study [42].
The total WRITE access energy of ME-MRAM depends
FIGURE 4. (a) and (c) WRITE and (b) and (d) READ performance of
on the WRITE voltage of the ME material as discussed pre- STT-MRAM with varying number of access transistors.
viously. The WRITE voltage depends on the coercive field
and the thickness. Ideally, one can make the multiferroic access transistors (4T1MTJ) offer the fastest WRITE operation
material very thin to achieve low WRITE voltages. However, since the magnet switching time is inversely proportional to
thin ME layers may suffer from large leakage currents, or they the overdrive spin-polarized current passing through the free
may lose their multiferroic properties. Here, we assume that layer. Next, for the WRITE performance, Fig. 4(c) presents
the ME layer is insulating, and we consider WRITE voltages that the WRITE energy increases exponentially with increasing
ranging from 0.1 to 0.5 V. For the case in which VWRITE = oxide thicknesses because of the exponential increase in the
0.4∼0.5 V, the WRITE access energy is calculated as resistance. In addition, as the number of access transistors
EWRITE increases, the layout area increases, leading to larger para-
sitic resistances and capacitances and higher WRITE energy.
2
= VWRITE / (RBL + RSL + Rtran + RMTJ ) ·tmag
Similarly, Fig. 4(b) shows that the READ delay also increases
+(CWL /Nbit + Ctran )Vdd
2 2
+ (CBL + Ctran )VWRITE with the increase of oxide thickness and the number of access
2 transistors. However, as shown in Fig. 4(d), the READ energy
+CAFM VWRITE (8)
initially decreases with the increase in the oxide thickness
For the other case of VWRITE = 0.1 ∼ 0.3 V, the WRITE energy because of a larger READ voltage and then increases as the
is the same as the case of VWRITE = 0.4 ∼ 0.5 V except that MTJ resistance and the READ time become too large.
we need to exclude the first term since there is no leakage A previous study [15] has demonstrated that using an oxide
current from the MTJ during the WRITE operation. thickness below 1.3 nm may lead to READ disturb issues.
To achieve the best tradeoff among fast READ access time
IV. RESULTS AND DISCUSSION and low READ/WRITE access energies, we choose an oxide
To compare the READ and WRITE performances of various thickness of 1.3 nm for STT-MRAM. It should be noted that
MRAM options, we first quantify the impact of the MTJ for very large oxide thicknesses (>1.7 nm), the READ current
oxide thickness on the READ delay and energy. Next, we cal- is too low for typical sense amplifiers. Also, the WRITE volt-
culate the WRITE delay and energy based on the physical age becomes prohibitively large. Hence, there are practical
models described in Section III and reported experimental reasons to avoid such large oxide thicknesses in addition to
parameters. Afterward, we study various tradeoffs to select the very large WRITE/READ energies and delays.
the optimal oxide thickness and discuss the READ disturb To summarize, using 2T1MTJ for the STT-MRAM pro-
issue for each memory type. Finally, we compare various vides a minimum WRITE energy-delay product (EDP) at the
spintronic memory cells and summarize the pros and cons of cost of a small increase in READ and WRITE energies. Note that
each cell in terms of density, READ and WRITE delay, and READ this 2T1MTJ scheme of STT-MRAM had also been proved to
and WRITE energies. Note that while the WRITE mechanism is increase WRITE speed in [43].
different for each cell, the READ operation is the same for all
options even though the parasitic resistance and capacitance B. VCEC-MRAM
values may vary depending on the layout area and cell design. VCEC-MRAM has the same READ performance as the
STT-MRAM for any given oxide thicknesses since they use
A. STT-MRAM the same layout designs. For the WRITE operation, we con-
To improve the WRITE speed of STT-MRAM, the number of sider three hypothetical magnet switching times (tmag ) of 5,
access transistors is varied from 1 to 4, and the corresponding 10, and 20 ns due to the lack of physical models or experi-
layouts are shown in Fig. 2. The WRITE current per transistor mental data at this point. The electric field is kept fixed as we
is kept constant as the MTJ oxide thickness varies such increase the oxide thickness such that the magnet switching
that the magnet switching time remains constant, as shown time is not affected as shown in Fig. 5(a). Fig. 5(b) reveals that
in Fig. 4(a) (by increasing the WRITE voltage linearly as the the WRITE energy increases with the oxide thickness when the
MTJ resistance increases). Fig. 4(a) also shows that four oxide is thicker than 2 nm. This is due to the increase in the

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FIGURE 5. (a) WRITE access time with a varying oxide thickness

of VCEC-MRAM. (b) Comparison of the WRITE access energy
with varying oxide thickness for VCEC-MRAM and STT-MRAM.

WRITE voltage. However, when the oxide thickness is thinner

than 2 nm, the WRITE energy again increases because the Joule
heating term (EJ )
EJ = V 2WRITE / (RBL + RSL + Rtran + RMTJ ) · tmag (9) FIGURE 6. (a) READ access energy versus the READ access time
of the SOT-RAM. (b) Switching time of a 60-nm-long,
becomes dominant compared with the dynamic energy, which 15-nm-wide, and 2-nm-thick ferromagnet with varying spin
2 current after 100 tests. (c) WRITE access energy versus WRITE
is equal to (CBL +Ctran )VWRITE . We choose an oxide thickness
access time when spin current increases from 25 to 75 µA.
of 1.6 nm to achieve both low WRITE and READ EDP since the (d) Comparison of the WRITE energy and delay time of various
READ delay time increases when the oxide thickness is too SOT materials using optimum WRITE voltages.
thick, as shown in Fig. 4(b).
Next, we compare the WRITE energy of VCEC-MRAM and conductivity of the ferromagnet MnGa σ = 5 × 105 −1 m−1 ;
STT-MRAM in Fig. 5(b). A large reduction in the WRITE hence, a small shunting factor s = 0.8 is obtained.
energy is evident even for a large tmag of 20 ns. This is Next, to evaluate the charge to spin conversion efficiency
because VCEC-MRAM is a voltage-controlled device, and without considering the current shunting problem, the spin
its WRITE voltage increases linearly with the oxide thickness, conductivity σs is used, which is expressed as the prod-
whereas STT-MRAM is a current-controlled device, and the uct of conductivity and θSH . Our calculations show that
WRITE voltage increases exponentially with resistance at a Bi0.9 Sb0.1 with a high σ and θSH has the highest σs . More-
constant overdrive current. Note that since VCEC-MRAM over, we incorporate the current shunting effect, as shown
is a voltage-controlled device, it only needs a one-access in Fig. 7 by considering the normalized WRITE current flowing
transistor during the WRITE operation, leading to a high cell through the SOT channel, which is defined as IWRITE,nor =
density. Overall, VCEC-MRAM offers lower WRITE energy, (s + 1)tSO /(θSH WFM ). It is noticed that Bi0.9 Sb0.1 still
small layout area, and better READ disturb margin compared shows the lowest IWRITE,nor , and a 4-nm-thick Bix Se1−x
with STT-MRAM. However, its READ access time is two to shows the second lowest IWRITE,nor . However, if we compare
three times larger because of the larger MTJ resistance. the ratio of the READ current IREAD to the WRITE current
IWRITE , we find that IREAD is 4× larger than IWRITE for
C. SOT-MRAM the case of Bi0.9 Sb0.1 . Generally, IREAD /IWRITE should be
Fig. 6(a) presents the READ performance of the SOT-MRAM lower than 0.1 such that there is enough margin to sep-
considering one or two WRITE access transistors. The results arate the READ and WRITE operations. The READ current
show that the READ access time increases exponentially with is typically on the order of a few µA. In the case of
the oxide thickness. The cell with two WRITE access transis- Bi0.9 Sb0.1 , the READ current flowing through the MTJ and
tors (3T1MTJ) has a higher READ delay time and READ energy the topological insulator may generate a spin current as large
compared with the cell with one WRITE access transistor as 100 µA, which could flip the free layer ferromagnet.
(2T1MTJ) because of the larger footprint area and the larger Therefore, Bi0.9 Sb0.1 may not be a suitable candidate
gate capacitance, which results in a higher RC delay. for real applications. Finally, to compare the total WRITE
To study the WRITE operation, we consider four categories energy of these SOT materials, we calculate the normalized
2
of SOT materials: heavy metals, alloys, Weyl semimetals, RIWRITE ,nor , where R includes the resistance of ferromagnet
and topological insulators. Heavy metals, Weyl semimetals, and SOT channel following the layout design in Fig. 1(b).
and alloys usually have higher conductivities but lower spin Table 3 indicates that Aux Pt1−x has the second-lowest nor-
Hall angles, whereas topological insulators are quite resis- malized WRITE energy and the second-lowest IREAD /IWRITE
tive but have larger spin Hall angles. Table 3 summarizes of 0.06. Note that even though 4-nm-thick Bix Se1−x has
important parameters for various SOT materials studied in the second-lowest IWRITE,nor , it has a higher SOT channel
this work.
From Table 3, Aux Pt1−x has the smallest s = 0.64 because
it has the lowest resistivity among all the candidates, whereas
topological insulators, such as Bix Se1−x , have the largest s of
47.34, when the thickness is 4 nm. This is because the thinner
Bix Se1−x suffers from a more severe current shunting prob-
lem. Note that Bi0.9 Sb0.1 has an exceptionally high bulk con- FIGURE 7. Schematic of the current shunting problem in
ductivity σ = 2.5 × 105 −1 m−1 , which is comparable to the SOT-MRAM using a topological insulator.
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TABLE 3. Comparison of various materials for SOT-MRAM.

resistivity compared with Aux Pt1−x ; thus, it generally has

larger WRITE energy. Also, while the 4-nm-thick Bix Se1−x
channel offers higher spin conductivity compared with the
8-nm-thick Bix Se1−x channel, it suffers from very poor
resistivity, which results in a higher energy dissipation due
to the large voltage drop across the channel.
To further evaluate the total WRITE performance of various
SOT candidates in an array, the optimal WRITE voltages
or WRITE currents are calculated to achieve the minimum FIGURE 8. (a) WRITE access time and (b) WRITE access energy
WRITE EDP for each option. The magnet switching time with a varying oxide thickness of ME-MRAM.
of a 60-nm-long, 15-nm-wide, and 2-nm-thick ferromagnet
with varying spin currents after 100 tests are simulated in RC delay. To reduce the READ EDP, we choose the oxide
OOMMF marked as black squares in Fig. 6(b). Next, we fit thickness to be 1.4 nm. For the WRITE operation, we consider
the sample data at each WRITE voltage under thermal noise (T hypothetical magnet switching delay of 1, 2, and 5 ns. Simi-
= 300 K) and extract the switching time based on three times larly, the WRITE voltage of the ME material is assumed to vary
a standard deviation above the median value. With varying from 0.1 to 0.5 V. Fig. 8(b) illustrates that the WRITE access
applied WRITE voltages, the corresponding magnetization energy is dominated by the WRITE voltage that charges or
switching time is fit to calculate the total WRITE access energy. discharges BL and SL since there is no charge current flowing
Fig. 6(c) shows that Aux Pt1−x and 8-nm-thick Bix Se1−x have through the MTJ. For VWRITE = 0.4∼0.5 V, the WRITE access
lower WRITE energy compared with W and WTe2 when IS time is smaller than the case of VWRITE = 0.1∼0.3 V because
varies from 25 to 75 µA. We then use the optimal WRITE of the smaller layout area. Overall, the WRITE access energy
voltages to calculate the total WRITE access time versus the of the ME-MRAM can be reduced to a few femtojoules if the
total WRITE energy, as shown in Fig. 6(d). Similar to the WRITE voltage is as small as 0.1 to 0.2 V.
calculation that we discuss in Table 3, Bi0.9 Sb0.1 has the
lowest WRITE energy and WRITE delay time, but it suffers E. COMPARISON OF THE READ AND WRITE
from the READ disturb issue. It is interesting to note that while PERFORMANCE OF SPINTRONIC MEMORY CELLS
Aux Pt1−x offers a spin conductivity almost three times larger Using the optimal oxide thickness and WRITE voltage for each
than 8-nm-thick Bix Se1−x , the two channels offer almost type of memory cell, we compare the READ and WRITE per-
similar WRITE energies at the array level. This is because of formances of various devices. Fig. 9 shows that STT-MRAM
the smaller current needed in the case of Bix Se1−x , which has higher WRITE access energy compared with other spin-
results in smaller voltage drop and energy dissipation in the tronic memory cells. Although the READ access energy of
select transistor and the BL. This fact highlights the need for the STT-MRAM is small in the 1T1MTJ case, its WRITE
array-level evaluations of various materials. delay is large, and 2T1MTJ is a better option when the
We then quantify the WRITE performances of SOT-MRAM WRITE speed is a primary concern, as seen in the litera-
when the number of WRITE access transistors increases from ture [43]. The VCEC-MRAM shows much lower WRITE
one to two such that the total spin current is doubled. It can access energy compared with STT-MRAM, especially when
be seen in Fig. 6(d) that the WRITE delay time goes down the magnet switching time is fast. The READ access energy
when the number of WRITE access transistors increases, but of VCEC-MRAM is also small because of its small foot-
the WRITE energy increases by 2× because of the larger lay- print area, but the READ delay time is larger because of a
out area, larger gate capacitances, and longer interconnects. thicker oxide. SOT-MRAM can offer smaller WRITE delay
Overall, the WRITE EDP of the two WRITE access transistor and energy values than those of STT-MRAM, as seen in [10]
case is larger than the one-access transistor case. Therefore, and [14]–[17]; however, the READ delay time is longer, and
using one WRITE access transistor (2T1MTJ) is better for the layout area is larger than STT-MRAM since SOT-MRAM
SOT-MRAM in terms of area and WRITE energy efficiency. is a three-terminal device. Furthermore, SOT-MRAM using
alloy SOT channels presents the lowest WRITE energy among
D. ME-MRAM all the SOT materials since it has a larger spin Hall angle
For the ME-MRAM, we consider the READ delay and energy compared with heavy metals and Weyl semimetals and higher
with two different numbers of access transistors, as shown conductivity compared with topological insulators, leading to
in Fig. 8(a). The results show that both the READ delay and a weaker current shunting effect. ME-MRAM has a poten-
energy increase as the number of access transistors increased tially small WRITE access energy and higher cell density com-
because of the larger layout area and the associated higher pared with other candidates. Because of the small footprint
VOLUME 6, NO. 1, JUNE 2020 15
 IEEE Journal on Exploratory Solid-State Computational Devices and Circuits

FIGURE 9. Total (a) WRITE and (b) READ performance and (c) layout area of various spintronic memory cells.

TABLE 4. Comparison of various spintronic memory cells and magnetic memory devices is presented based on experi-
SRAM. mentally validated physical models considering a range of
recently reported materials and devices. For material choices
of SOT-MRAM, our cross-layer optimization and bench-
marking highlight that common metrics, such as the spin Hall
conductivity (σs ) and normalized WRITE current (IWRITE,nor ),
may not be sufficient. For instance, Aux Pt1−x offers a spin
conductivity more than three times larger than 8-nm-thick
Bix Se1−x . However, the two-channel materials offer almost
area, the READ access energy of ME-MRAM can be as low similar WRITE energies at the array level. This is because of
as that of the VCEC-MRAM when the same oxide thickness the smaller current needed in the case of Bix Se1−x , which
is used. Overall, voltage-controlled devices, such as VCEC- results in smaller voltage drop and energy dissipation in the
MRAM and ME-MRAM, have lower WRITE access energy select transistor and the bitline. The extraordinarily high spin
and also lower READ access energy because of their thicker Hall efficiency reported for Bi0.9 Sb0.1 and its high electrical
oxide thicknesses and small footprints compared with other conductivity result in a very high spin conductivity. However,
devices. the very low WRITE current can cause high READ disturb rates.
Finally, we perform a comprehensive benchmarking for A 4-nm-thick Bix Se1−x layer offers a very large spin Hall
all spintronic devices investigated in this article and CMOS angle but suffers from large current shunting effects because
SRAM in terms of the READ and WRITE performances. of its high resistivity and is not a promising option. In general,
Fig. 9 shows that SRAM still offers the fastest WRITE and alloys with large spin Hall angles and high conductivity are
READ delay because it is a charge-based device with positive
promising SOT channel materials.
feedback, whereas spintronic memory devices have slow The design of the ME-MRAM cell can be simplified from
WRITE and READ operations because of the precessional
2T1MTJ to 1T1MTJ if the WRITE voltage of the ME layer is
switching behavior of ferromagnets and their inherently low adequately larger than the READ voltage, which is typically
TMR ratio. Nevertheless, SRAM consumes more energy and around 0.1–0.2V. Hence, there is a tradeoff between memory
area compared with the spintronic memory devices, including density and WRITE energy. The benchmarking results show
STT-MRAM with 2T1MTJ, VCEC-MRAM, SOT-MRAM that SOT-MRAM can be fast and low energy but would suffer
using Au0.25 Pt0.75 , and ME-MRAM with VWRITE = 0.5 V, as from a 25% larger cell area compared with STT-MRAM.
shown in Table 4. Our results exhibit that spintronic memory VCEC-MRAM can be denser than STT-RMAM (2T1MTJ)
devices using novel physical mechanisms, such as VCEC- and dissipate less energy but would suffer from slower READ
MRAM, SOT-MRAM, and ME-MRAM, are promising operations because of its large oxide thickness. ME-MRAM
options to be used in the last level of cache because of the can be fast, low energy, and dense compared with all other
nonvolatility, low WRITE and READ energies, and smaller options. Although spintronic memory devices have slower
layout area. WRITE and READ operations compared with SRAM, the char-
It is important to note that the studied MRAM technol- acteristics of nonvolatility and smaller layout area make them
ogy options are at different levels of maturity. SOT-MRAM promising options for memory applications.
using β-W as the SOT channel has been successfully fab-
ricated in 55-nm CMOS technology with a thermal budget ACKNOWLEDGMENT
of 400 ◦ C [44]. Therefore, SOT-MRAM is a promising The authors would like to thank Dr. Wilman Tsai,
candidate that may be adopted in the near future. On the other Dr. Carlos Diaz, Dr. Ian Young, Dr. Dmitri E. Nikonov,
hand, VCEC-MRAM and ME-MRAM that offer the largest Prof. Arijit Raychowdhury, Prof. Jian-Ping Wang,
benefits in terms of density and possibly energy are still at the Dr. Xiang Li, Dr. Mahendra DC, and Dr. Delin Zhang for
early stages of research and may be considered as long-term the fruitful discussion.
potential candidates.
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