BANGLADESH UNIVERSITY OF ENGINEERING & TECHNOLOGY (BUET)
DEPARTMENT OF ELECTRICAL & ELECTRONIC ENGINEERING (EEE)
COURSE NO.: EEE 202 (S)
COURSE NAME: ELECTRONIC CIRCUITS-I LABORATORY (SIMULATION)
EXPERIMENT NO. 03
NAME OF THE EXPERIMENT: DC CHARACTERISTICS STUDY AND BIASING OF JUNCTION FIELD
EFFECT TRANSISTOR (JFET) WITH SMALL SIGNAL AMPLIFIER
OBJECTIVES
The objectives of this experiment are to simulate
Studying the DC characteristics of JFETs
Biasing of JFETs
Studying the performance of the Common Source (CS) and Common Drain (CD)
JFET small signal amplifiers
THEORY
1. THE JUNCTION FIELD EFFECT TRANSISTOR (JFET)
The input impedance of the JFET is very high since the gate-to-channel junction is always
reverse biased. FET’s are therefore useful in the design of high-input-impedance amplifiers. In
this experiment we shall study two configurations of FET amplifiers: the common-source
circuit, and the common-drain or source follower. In addition to its application in amplifier
design, JFETs are very useful as voltage controlled resistances. In the triode, region, the ID-
VDS characteristics have high slope and approximate straight lines for small VDS. Furthermore,
these straight lines pass through the origin. This linear resistance region of operation enables
the application of the JFET as an analog switch. Switching of analog signals is required in
many applications such as the multiplexing of a number of signal sources, onto single pair of
wires, and the chopping of a low frequency square wave. The Junction Field Effect Transistor
(JFET). As with other FET types, the JFET is available in 2 polarities: n-channel and p-channel.
The basic structure of a n channel JFET is shown in Figure 1. The p-channel can be fabricated
simply by reversing all the semiconductor types.
Figure 1: The Junction Field Effect Transistor (JFET)
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The n region is the channel and the p-type regions are electrically connected together the gate.
Thus the JFET is a 3 terminal device. When VGS=0V, the application of VDS causes current
to flow from the drain to the source. When a negative VGS is applied, the depletion region of
the gate-channel junction widens and the channel becomes correspondingly narrower; thus the
channel resistance increases and the current ID decreases for a given VDS. One way to think
of a JFET is as a resistance whose value is controlled by VGS. If VGS is increased in the
negative direction, eventually a value is reached at which the depletion region occupies the
entire channel. The channel has in effect disappeared (i.e. the channel is pinched), as shown in
Figure 2.
Figure 2: Pinch-off (VGS=0V, VDS=VP)
The JFET characteristics are displayed in Figure 3 and Figure 4, for threshold voltage Vt=Vp=-
4V, IDSS=8mA. Although Figure 4, shows ID to be independent of VDS in the saturation
region, this is an ideal situation. In fact JFETs also suffer from channel-length modulation. For
JFETs the threshold voltage is usually called the pinch-off voltage and is denoted by Vp, thus
Vp=Vt. For n-channel JFET Vp is negative.
Figure 3: n-Channel JFET characteristics with IDSS=8mA and Vp = - 4V
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Figure : 4
Figure 4: JFET biasing circuits
2. THE JFET AS AN AMPLIFIER
To understand the basis for the operation of the JFET as an Amplifier, consider the circuit of
Figure 1.
VDD
ID Rd
vD
+ +
vgs vgs
-
+
VGS -
-
Figure 5: JFET amplifier
vGS VGS v gs (1)
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Assuming that the FET will remain in pinch off at all times, which is achieved by keeping vDS
higher than vGS by at least Vp (pinch-off voltage), that is
v DS vGS V p (2)
It can be shown that
VGS 2
I D I DSS (1 ) (3)
Vp
And for
v gs
1 (4)
VP
2 I DSS V
id ( )(1 GS )v gs (5)
VP VP
Thus, the signal current is linearly related to the signal voltage vgs, which is a requirement in a
linear amplifier and which is obtained under the small signal condition of equation (4). The
constant relating id to vgs is the trans-conductance gm,
id 2I V
gm ( DSS )(1 GS ) (6)
vgs Vp Vp
Recalling that for n-channel FET’s Vp is a negative number and VGS is also negative, it is seen
that gm is positive; a comforting result. Note that gm is determined by the FET parameters IDSS
and Vp, as well as by the DC operating point. We may write.
2 I DSS ID
gm ( ) (7)
VP I DSS
It follows that gm will be highest if the FET is biased at VGS= 0 (or, ID = IDSS). This maximum
value of gm is denoted gmo and is given by.
2I
g mo ( DSS ) (8)
VP
3. THE COMMON SOURCE AMPLIFIER
Fig. 2 shows the common source amplifier where the FET is biased using a combination of
fixed bias and self-bias. The fixed bias voltage VGG is derived from VDD via the voltage divider
RG1, RG2.
RG 2
VGG VDD (9)
RG1 RG 2
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The self-bias is obtained by connecting a resistance RS in the source load. We shall assume that
a DC drain current ID is established and that the value of Rd is such that the FET remains in
pinch-off at all times. The signal Vi is obtained from a source having a resistance ‘R’ and is
coupled to the gate through a capacitor C1 should be chosen such that its reactance is very small
at the frequency band of interest.
The output voltage signal at the drain is coupled to a load resistance RL through another
capacitor C2. The value of Cs should be chosen such that its reactance is very small at the
frequencies of interest. At low frequencies CS will no longer be a perfect signal bypass.
To evaluate the gain of the common source amplifier we ignore all capacitive effects. The input
resistance Rin is given by (see Fig. 2),
R R
Rin RG1 // RG 2 G1 G 2 (10)
RG1 RG 2
Thus, we may use the voltage divider rule to evaluate the signal vgs,
Rin
v gs vi (11)
R Rin
The drain current signal id will be id= gmvgs, and will flow into and effective load resistance RL
given by,
RL Rd // RL // ro (12)
Thus, the stage gain is given by,
vo Rin
( ) g m RL (13)
vi R Rin
4. THE COMMON DRAIN AMPLIFIER
Fig. 3 shows the JFET used in a source follower (common-drain) configuration. Because of its
high impedance the JFET is an ideal device for such an application. Note, however, that since
the signal is capacitively coupled to the gate, a resistor RG had to be introduced in order to
provide DC continuity for the gat. The input resistance of the source follower will be
approximately equal to GG. Thus, the signal voltage at the gate will be,
RG
v g vi (14)
R RG
And the output voltage is obtained as,
RS // RL
vo v g (15)
(1 / g m ) RS // RL
Equations (14) and (15) can be combined to obtain the gain,
vo RG RS // RL
(16)
vi R RG (1 / g m ) RS // RL
Thus the gain is less than, but usually close to unity.
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To calculate the output resistance of the source follower we ground the signal source, the result
is
Rout RS //(1 / g m ) (17)
Which is usually quite small.
PROCEDURE
DC Characteristics of JFET J2N3819
R2
1k
Vdd
J1 0Vdc
J2N3819
0Vdc
Vgg
Fig.6. Circuit for DC analysis of JFET
Draw the circuit shown in Fig. 1 in PSpice schematics.
Plot of Transfer Curve of JFET
Set Vdd = 10V.
Set DC Sweep (linear) of Vgg from -5 to 0.7 volts in 0.01 volt steps.
Place a voltage marker on the drain of JFET. Run the simulation.
The transfer Curve will appear on the screen.
Plot of Output Characteristics of JFET
Here, for determining the output characteristics a nested DC Sweep of Vdd and
Vgg is required. For achieving this, Select Setup Analysis and then DC Sweep from
the pop-up window. Sweep first Vdd from 0 to 20V in 0.1V increments. Then click
on the Nested Sweep button for sweeping Vgg from -4 to 0V in 1V increments.
Mark the Enable Nested Sweep box.
After placing a current marker in the drain of the JFET, run the simulation.
Change the X-axis settings. [Plot Axis settings Axis variable. Then select
V(J1:d) as axis variable]
Output characteristic of the JFET will appear in the probe.
Determine the pinch-off voltage of JFET for different Vgg.
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Small Signal Analysis of JFET as CS amplifier
Fig.7.
Rin
Fig.8. Circuit for Small signal analysis using JFET as CS Amplifier
Draw the circuit shown in Fig. 8.
By choosing Setup analysis, mark Bias Point Detail and Transient.
Choose appropriate step and stop time.
Run the simulation and click on the Enable Bias Voltage Display and Enable Bias
Current Display icons. Note IDSQ and VGSQ. Compare this with theoretical values.
Draw the small signal equivalent circuit [Homework]
Obtain the voltage gain for the circuit (v0/vs) from the display in probe.
Remove CS and calculate the voltage gain. Compare it with the result of step 6. What
is the effect of CS on the gain?
Reconnect CS and connect a resistance of 100 k of in series with the source. Calculate
the new voltage gain.
From step 6 and 8 calculate input resistance of the amplifier.
With CS connected, set the load resistance RL = 1M and calculate the voltage gain.
Use the result of step 8 to calculate the output resistance.
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Small Signal Analysis of JFET as CD amplifier
Rin
Fig.9. Circuit for Small signal analysis using JFET as CD Amplifier
Draw the circuit shown in Fig. 9.
By choosing Setup analysis, mark Bias Point Detail and Transient.
Choose appropriate step and stop time.
Run the simulation and click on the Enable Bias Voltage Display and Enable Bias
Current Display icons. Note IDSQ and VGSQ. Compare this with theoretical values.
Draw the small signal equivalent circuit [Homework]
Obtain the voltage gain for the circuit (v0/vs) from the display in probe.
Simulate the circuit of Fig. 3 for obtaining the gain-frequency characteristic for the
frequency range 10Hz-1MHz.
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