With help from David Szmyd, Silicon Labs
Design Wafer Fab Assembly
Test
Wafer Fab is easily the biggest
component of our COGS
$$$
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3 decades/step
$3B
$3M
$3K
$3
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metal
oxide
gate (at zero Volts)
source drain
n-type Electrons in source cannot flow to the
semiconductor drain because p-type region is a barrier.
p-type Transistor is OFF.
gate (at + Volts)
source drain Apply positive voltage to gate. Attracts
n-type electrons to oxide, forming n-type
channel. Now, electrons have a
continuous path from source to drain.
p-type
Transistor is ON.
channel
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NMOS: S, D and channel are n-type PMOS: S, D and channel are p-type
gate gate
source drain source drain
n-type p-type
p-type n-type
• Can combine NMOS and PMOS so that when one is on, the other is off.
• No current flows because one device is always off. Saves power!!
• Exception: Current flows only when devices are switching.
• Devices are complementary CMOS.
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PMOS NMOS
metal
Interconnect
ILD
(oxide) contact layers
STI
(oxide)
Nwell Pwell Silicon
wafer
p-substrate
• Devices are built into a common p-type substrate (wafer).
• Shallow Trench Isolation (STI) provides electrical isolation between devices.
• Metal and contacts provide access to the device terminals S, D, G.
• Multiple levels of metal lines are routed to interconnect the devices form a
circuit on a chip.
• Capacitors, resistors and inductors can also be integrated.
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NMOS with separate well tap NMOS with well tap shorted
to source by the silicide
poly crossing
G STI edge. Gate
G
S D oxide weakest S D
here.
cross
section
P-tap N+ P-tap N+
contacts to poly must be
field oxide
over field oxide
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Technology defined by minimum allowed gate length.
gate
source drain Shorter gates faster transistors (100 GHz) and
n-type denser circuits. Each node increases density by ~2x.
Lmin 0.5µm 0.35µm 0.25µm 0.18µm 0.13µm
• At finer nodes, all features shrink: contact size, metal width, oxide thickness, etc.
• In 0.13um, gate oxide thickness is only 20A (about a dozen SiO2 molecules).
Part Function Tech Contact M1 L/S # metals # masks Size
chip1 example1 0.5µm 0.5µm 0.6/0.6µm 3 16 4.62 mm2
chip2 Example2 0.35µm 0.4µm 0.5/0.45µm 4 21 6.07 mm2
chip3 Example3 0.35µm 0.4µm 0.5/0.45µm 4 30 8.95 mm2
chip4 Example4 0.25µm 0.3µm 0.32/0.32µm 4 23 5.5 mm2
chip5 Example5 0.18µm 0.22µm 0.23/0.23µm 5 23 6.51 mm2
chip6 Example6 0.13µm 0.16µm 0.16/0.18µm 8 37 2.93 mm2
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♦ Armed with photomasks and starting substrates, the foundry
can now fabricate the wafers.
– Starting substrates are cut and polished from huge single crystals of
silicon. Not done by the foundries.
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.
♦ Photolithography – transfer mask pattern to wafer
♦ Implant – shoot impurities into the silicon
♦ Diffusion – anneal implant damage, grow oxide
♦ Deposition – deposit layers (oxides, metals, etc.)
♦ Etch – remove unwanted material
♦ CMP – chemo-mechanical polishing. Removes unwanted
material by polishing, leaving the wafer flat.
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Expose with UV light
Spin photoresist onto wafer Develop and bake
mask
photoresist
wafer wafer wafer
Process (etch or implant)
Strip resist
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Ionize and accelerate impurity atoms Profile is Gaussian. Peak is not at surface
into the silicon. 100eV – 1 MeV.
Must anneal crystal damage
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Chemical Vapor Deposition Sputter material from a target onto the wafer
• RF plasma + magnetron.
• Argon ions physically dislodge target
atoms.
• React source gases inside chamber.
• Good for depositing metals.
• RF plasma (usually)
• Can add O2 for reactive sputtering.
• Reduced pressure
• Used for oxides and polysilicon, epitaxy.
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Wet Etch RIE – Reactive Ion Etch
• Use reactive ions like Cl- or F- to etch material.
• Single wafer tool.
• Want high selectivity.
• Dip wafers boat in HF acid to remove oxide • Usually want high anisotropy.
• Isotropic
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Furnace RTP- Rapid Thermal Process
• Heat wafer extremely fast with IR lamps.
Soak time of a few seconds.
• Used for impurity activation. Impurities
have no time to move.
• Used for long anneal or alloy
• Uniform
• Grow gate oxide
• Can grow films
• Batch mode
• Single wafer tool
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Nonplanar wafer surface Polish oxide flat first
rotating polishing pad
hard to etch away metal in valleys
M2 M1 oxide
wafer
M1 oxide
wafer
M1 oxide
• Lowers yields. wafer
• Limits number of interconnect
layers to 2 or 3. • Can also polish metal
• Limits spacing between lines.
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CMP Tool
• Dirty - kept apart from other tools
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Large open areas get overpolished Wide metal lines get overpolished
dishing!
wafer
wafer
Solution. Add dummy lines to meet
minimum density requirements. wafer
Solution: Restrict width. Slot line.
create high points
wafer
• can be done automatically
• increases parasitic capacitance wafer
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♦ Integrate all the previous process steps top make realize a
fully processed wafer with an array of functional die.
♦ 0.13um process with Cu interconnect.
♦ Two halves
– Frontend: from bare wafer to transistors with S/D/G electrodes.
– Backend: interconnect layers (metals and vias) for wiring the devices.
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Starting Oxide
700µm
Substrate, non-epi, low resistivity
p-type, p~1e15 cm-3 (10 Ω-cm)
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“global”
silicon
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* 3" * &
P+, MeV, 1e12
DNW resist
3-5µm
Substrate, non-epi, low resistivity
DNW
p-type, p~1e15 cm-3 (10 Ω-cm)
Isolated PMOS NMOS
NMOS
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Active Region
Field Region OD resist
nitride
oxide
etch away Si
p-type substrate
DNW
Isolated PMOS NMOS
NMOS
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LOCOS NEW: STI
(Local Oxidation of Silicon) (Shallow Trench Isolation)
• High temperature oxidation • Si etch, Oxide overfill, CMP back
• Bird’s beak edge ill-defined • Flat, planar
• Coarse pitch. No narrow field oxide • Low temperature
• Partially Recessed. Non-planar • Fine pitch
• Old, 0.35um and higher • New, 0.25um and lower
Need corner
rounding, but
not too much
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• 2-3 implants/mask, B/In for Pwell, As/P for Nwell
• If process has dual Vdd, then core and I/O have separate wells
• Also, Vt adjust implants for LV and HV flavors of core transistors
STI
Pwell Nwell Pwell
p-type substrate
DNW
Isolated PMOS NMOS
NMOS
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• Grow gate oxide (could be dual oxide)
• Deposit Polysilicon (gate material)
• Etch Poly. Width is the transistor L. Control is critical (CD = Critical Dimension)
gate oxide
STI
Pwell Nwell Pwell
p-type substrate
DNW
Isolated PMOS NMOS
NMOS
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Core (thin) I/O (thick)
• Grow partial oxide
• Remove oxide in core
region (mask I/O)
• Grow 2nd oxide
• Deposit Poly
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• Self-aligned to gate poly.
• Pocket: extra well doping to prevent Vt rolloff. Angled to get under gat poly.
• LDD: Lightly-Doped Drain. Reduces electric field and hot-carriers at drain.
pocket
p-type n-type
STI
Pwell Nwell Pwell
p-type substrate
DNW
Isolated PMOS NMOS
NMOS
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• Spacer protects LDD. About 0.1um – 0.2um wide.
• Spacer: TEOS only or nitride/oxide bilayer stack.
• Heavy extrinsic implants for low Rseries. Also dopes the poly.
spacer
p-type n-type
STI
Pwell Nwell Pwell
p-type substrate
DNW
Isolated PMOS NMOS
NMOS
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• Self-aligned to diffusion regions and poly.
• TiSi (0.25um and above), CoSi (0.18um to 90nm), NiSi (65nm)
• Deposit React Strip Convert to low resistance phase
STI
Pwell Nwell Pwell
p-type substrate
DNW
Isolated PMOS NMOS
NMOS
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♦ Before sputtering silicide metal, deposit oxide.
♦ Remove oxide where silicide is needed. Block oxide etch
with RPO mask for resistors.
before strip after conversion
resistor top view
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• Deposit ILD oxide and CMP flat
• Usually W-plug
• Etch hole Deposit W CMP flat
ILD contact
(oxide)
STI
Pwell Nwell Pwell
p-type substrate
DNW
Isolated PMOS NMOS
NMOS
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• Aluminum: Deposit metal, mask and etch.
• Copper: Deposit oxide (IMD), etch trench, deposit metal, CMP flat
metal
ILD
(oxide)
contact
STI
Pwell Nwell Pwell
p-type substrate
DNW
Isolated PMOS NMOS
NMOS
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Aluminum Copper
start with flat oxide start with flat oxide
sputter Al film pattern photoresist
pattern photoresist etch trenches in
oxide, strip resist
easy to etch oxide
etch Al
hard to etch fine electroplate Cu
lines
strip photoresist CMP Cu flat
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Tungsten Copper
start with flat oxide start with flat oxide
on top Al on top Cu
pattern photoresist pattern photoresist
etch holes in etch holes to etch
oxide, strip resist stop layer, strip
resist
deposit W pattern and etch
metal line trenches
CMP W flat electroplate Cu
deposit and CMP Cu flat
pattern Al lines
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• Repeat metal and via processing steps to complete interconnect.
• Deposit passivation (nitride) and etch.
• For Cu, deposit Al wirebond layer and etch.
• For P49, route Al layer to bump (redistribution of bondpads)
passivation
MT
via
MT-1
via
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Top View Cross Section (4 metal stack)
via
metal
M1-M5 stacked and tied together with vias
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metal5
CTM
oxide
metal4
♦ Above MIMcap uses existing metal for bottom plate. This style found in
0.18um and higher. Requires one mask for CTM
♦ For 0.13um process, cannot use copper as a bottom plate. Instead,
separate CBM layer is added. Two masks required.
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