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CMOS Circuit Design Tutorial

This document contains a tutorial on CMOS combinational circuit design led by Professor Sudeb Dasgupta. It includes 10 questions for students to solve related to designing optimal differential signals, analyzing the purpose of a PMOS transistor, calculating pull-up and pull-down times, determining minimum voltage thresholds, implementing logic functions with minimum transistors, and designing the same circuit using transmission gates. It also lists the students enrolled in the ECN-573 course.

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Tanishq Varshney
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67 views6 pages

CMOS Circuit Design Tutorial

This document contains a tutorial on CMOS combinational circuit design led by Professor Sudeb Dasgupta. It includes 10 questions for students to solve related to designing optimal differential signals, analyzing the purpose of a PMOS transistor, calculating pull-up and pull-down times, determining minimum voltage thresholds, implementing logic functions with minimum transistors, and designing the same circuit using transmission gates. It also lists the students enrolled in the ECN-573 course.

Uploaded by

Tanishq Varshney
Copyright
© © All Rights Reserved
We take content rights seriously. If you suspect this is your content, claim it here.
Available Formats
Download as PDF, TXT or read online on Scribd

Tutorial: CMOS Combinational Circuit Design

Instructor: Sudeb Dasgupta


Note:​ Please solve all the questions. TA will verify your problem
solving skills.

Q1. Design a circuit that generates an optimal differential signal as


shown in Figure. Make sure the rise and fall times are equal.

Q2. If the PMOS were removed, would the circuit still function
correctly? Does the PMOS transistor serve any useful purpose?
Q3. Consider the circuit as shown below. Let Cx = 50 fF, Mr has W/L =
0.375/0.375, Mn has W/Leff = 0.375/0.25. Assume the output inverter
doesn’t switch until its input equals VDD/[Link] long will it take Mn
to pull down node x from 2.5 V to 1.25 V if In is at 0 V and B is at
2.5V ?
Q4. Consider the parameters given in Q3, and calculate how long will
it take Mn to pull up node x from 0 V to 1.25 V if VIn is 2.5 V and
VB is 2.5 V?

Q5. Consider the parameters given in Q3, and determine What is the
minimum value of VB necessary to pull down Vx to 1.25 V when VIn =
0V?

Q6. Suppose we wish to implement the two logic functions given by F =


A + B + C and G = A + B + C + D. Assume both true and complementary
signals are available. Implement these functions in dynamic CMOS as
cascaded stages so as to minimize the total transistor count.
Q7. Consider the parameters given in Q6, and design an np-CMOS
implementation of the same logic functions.

Q8.
Q9. Consider the parameters given in Q8,

Q10. Consider the parameters given in Q8,

Student Task For Today!


Implement the same circuit shown above using TG
ECN-573 List of students

adoneria@[Link]
a_kumar1@[Link]
a_singh1@[Link]
chirag@[Link]
e_tarun@[Link]
i_verma@[Link]
ksriram@[Link]
lr_gannavarapu@[Link]
n_goma@[Link]
n_gupta@[Link]
p_jain@[Link]
r_shah@[Link]
ss_nayakanti@[Link]
skhan@[Link]
sj_tembhre@[Link]
s_manna@[Link]
t_varshney@[Link]
u_kumar@[Link]
a_singh@[Link]
alok_31711218@[Link]
[Link].01@[Link]
ia_khan@[Link]
p_kumar1@[Link]
s_singh@[Link]

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