LTC1235

Microprocessor
Supervisory Circuit

FEATURES DESCRIPTION
n Guaranteed Reset Assertion at VCC = 1V The LTC®1235 provides complete power supply monitoring
n 1.5mA Maximum Supply Current and battery control functions for microprocessor reset,
n Fast (35ns Max.) Onboard Gating of RAM Chip battery backup, RAM write protection, power failure warn-
Enable Signals ing and watchdog timing. The LTC1235 has all the LTC695
n Conditional Battery Backup Extends Battery Life features plus conditional battery backup and external reset
n 4.65V Precision Voltage Monitor control. When an out-of-tolerance power supply condition
n Power OK/Reset Time Delay: 200ms occurs, the reset outputs are forced to active states and
n External Reset Control the Chip Enable output write-protects external memory.
n Minimum External Component Count The RESET output is guaranteed to remain logic low with
n 1μA Maximum Standby Current VCC as low as 1V. External reset control is provided by a
n Voltage Monitor for Power Fail or Low Battery debounced pushbutton reset input.
Warning The LTC1235 powers the active CMOS RAMs with a charge
n Thermal Limiting pumped NMOS power switch to achieve low dropout and
n Performance Specified Over Temperature low supply current. When primary power is lost, auxiliary
n All the LTC695 Features Plus Conditional Battery power, connected to the battery input pin, provides backup
Backup and External Reset Control power to the RAMs. The LTC1235 can be programmed by
a P signal to either back up the RAMs or not. This extends
APPLICATIONS the battery life in situations where RAM data need not
n Critical μP Power Monitoring always be saved when power goes down.
n Intelligent Instruments For an early warning of impending power failure, the
n Battery-Powered Computers and Controllers LTC1235 provides an internal comparator with a user-
n Automotive Systems defined threshold. An internal watchdog timer is also
L, LT, LTC and LTM are registered trademarks of Linear Technology Corporation. All other available, which forces the reset pins to active states when
trademarks are the property of their respective owners.
the watchdog input is not toggled prior to the time-out
period.

TYPICAL APPLICATION Battery Life vs

Backup Duty Cycle
10
LT1086-5
VIN ≥ 7.5V +5V 9
VIN VOUT VCC VOUT POWER TO μP LTC1235
+ +
BATTERY LIFE (NORMALIZED)

0.1μF 0.1μF CMOS RAM POWER 8

10μF ADJ 100μF
LTC1235
7
VBATT BACKUP I/O LINE
6
+3V RESET
51k μP RESET
5 LTC695
PFO μP NMI μP (WITHOUT
PFI SYSTEM 4
CONDITIONAL
PB RST WDI I/O LINE 3 BATTERY
10k BACKUP)
2
1235 TA1 1
0
THE LTC1235 EXTENDS BATTERY LIFE BY PROVIDING BATTERY POWER ONLY WHEN REQUIRED TO BACK UP RAM DATA. 0 20 40 60 80 100
IT SAVES THE BATTERY WHEN NO DATA BACKUP IS NEEDED. THE μP REQUESTS BACKUP WITH THE BACKUP PIN.
BACKUP DUTY CYCLE (%)
1235 TA02

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LTC1235
ABSOLUTE MAXIMUM RATINGS
(Notes 1 and 2)
Terminal Voltage VOUT Output Current ................... Short Circuit Protected
VCC ....................................................... –0.3V to 6.0V Power Dissipation ...............................................500mW
VBATT .................................................... –0.3V to 6.0V Operating Temperature Range
All Other Inputs ........................–0.3V to (VCC + 0.3V) LTC1235C ................................................ 0°C to 70°C
Input Current Storage Temperature Range................... –65°C to 150°C
VCC ..................................................................200mA Lead Temperature (Soldering, 10 sec.) ................. 300°C
VBATT .................................................................50mA

PIN CONFIGURATION
TOP VIEW TOP VIEW

VBATT 1 16 RESET VBATT 1 16 PRESET

VOUT 2 15 RESET VOUT 2 15 PRESET
VCC 3 14 WDO VCC 3 14 WDO

GND 4 13 CE IN GND 4 13 CE IN
LTC1235 LTC1235
BATT ON 5 12 CE OUT BATT ON 5 12 CE OUT
LOW LINE 6 11 WDI LOW LINE 6 11 WDI

PB RST 7 10 PFO PB RST 7 10 PFO

BACKUP 8 9 PFI BACKUP 8 9 PFI

N PACKAGE SW PACKAGE
16-LEAD PLASTIC DIP 16-LEAD PLASTIC SOL
TJMAX = 110°C, θJA = 130°C/W TJMAX = 110°C, θJA = 130°C/W

CONDITIONS:PCB MOUNT ON FR4 MATERIAL,

STILL AIR AT 25°C COPPER TRACE

ORDER INFORMATION
LEAD FREE FINISH TAPE AND REEL PART MARKING PACKAGE DESCRIPTION TEMPERATURE RANGE
LTC1235CN#PBF LTC1235CN#TRPBF LTC1235CN 16-Lead Plastic DIP 0°C to 70°C
LTC1235CSW#PBF LTC1235CSW#TRPBF LTC1235CSW 16-Lead Plastic SOL 0°C to 70°C
Consult LTC Marketing for parts specified with wider operating temperature ranges.
Consult LTC Marketing for information on non-standard lead based finish parts.
For more information on lead free part marking, go to: [Link]
For more information on tape and reel specifications, go to: [Link]

PRODUCT SELECTION GUIDE

WATCHDOG BATTERY POWER FAIL RAM WRITE PUSH-BUTTON CONDITIONAL
PINS RESET TIMER BACKUP WARNING PROTECT RESET BATTERY BACKUP
LTC1235 16 X X X X X X X
LTC690 8 X X X X
LTC691 16 X X X X X
LTC694 8 X X X X
LTC695 16 X X X X X
LTC699 8 X X
LTC1232 8 X X X
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 LTC1235
ELECTRICAL CHARACTERISTICS The l denotes the specifications which apply over the full operating
temperature range, otherwise specifications are at TA = 25°C. VCC = Full Operating Range, VBATT = 2.8V, Backup = No Connection,
TA = 25°C, unless otherwise noted.
PARAMETER CONDITIONS MIN TYP MAX UNITS
Battery Backup Switching
Operating Voltage Range
VCC 4.75 5.50 V
VBATT 2.00 4.25 V
VOUT Output Voltage IOUT = 1mA VCC – 0.05 VCC – 0.005 V
l VCC – 0.1 VCC – 0.005 V
IOUT = 50mA VCC – 0.5 VCC – 0.25 V
BACKUP Input Threshold VCC > Reset Voltage Threshold
Logic Low 0.8 V
Logic High 2.0 V
BACKUP Pullup Current (Note 4) 3 μA
VOUT in Battery Backup Mode (Note 5) IOUT = 250μA, VCC < VBATT VBATT – 0.1 VBATT – 0.02 V
VOUT in Battery Saving Mode (Note 5) VCC < VBATT 0 V
1MΩ Pulldown on VOUT V
VCC Supply Current (excluding IOUT ) IOUT ≤ 50mA 0.6 1.5 mA
l 0.6 2.5 mA
Battery Supply Current in Battery Backup Mode VCC = 0V, VBATT = 2.8V 0.04 1 μA
and Battery Saving Mode (Note 5) l 0.04 5 μA
Battery Standby Current 5.5 > VCC > VBATT + 0.2V –0.1 +0.02 μA
(+ = Discharge, – = Charge) l –1.0 +0.10 μA
Battery Switchover Threshold Power-Up 70 mV
VCC – VBATT Power-Down 50 mV
Battery Switchover Hysteresis 20 mV
BATT ON Output Voltage (Note 6) ISINK = 3.2mA 0.4 V
BATT ON Output Short Circuit Current (Note 6) BATT ON = VOUT Sink Current 35 mA
BATT ON = 0V Source Current 0.5 1 25 μA
Push-Button Reset
PB RST Input Threshold Logic Low 0.8 V
Logic High 2.0 V
PB RST Input Low Time (Notes 4, 7) l 40 ms
Reset and Watchdog Timer
Reset Voltage Threshold l 4.5 4.65 4.75 V
Reset Threshold Hysteresis 40 mV
Reset Active Time VCC = 5V 60 200 240 ms
l 140 200 280 ms
Watchdog Time-out Period VCC = 5V 1.2 1.6 2.00 sec
l 1.0 1.6 2.25 sec
Reset Active Time PSRR 1 ms/V
Watchdog Time-out Period PSRR 8 ms/V
Minimum WDI Input Pulse Width VIL = 0.4V, VIH = 3.5V l 200 ns
RESET Output Voltage At VCC = 1V ISINK = 10μA, VCC = 1V 4 200 mV
RESET and LOW LINE Output Voltage ISINK = 1.6mA, VCC = 4.25V 0.4 V
(Note 6) ISOURCE = 1μA, VCC = 5V 3.5 V
RESET and WDO Output Voltage ISINK = 1.6mA, VCC = 5V 0.4 V
(Note 6) ISOURCE = 1μA, VCC = 4.25V 3.5 V

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LTC1235
ELECTRICAL CHARACTERISTICS The l denotes the specifications which apply over the full operating
temperature range, otherwise specifications are at TA = 25°C. VCC = Full Operating Range, VBATT = 2.8V, Backup = No Connection,
TA = 25°C, unless otherwise noted.
PARAMETER CONDITIONS MIN TYP MAX UNITS
RESET, RESET, WDO, LOW LINE Output Source Current 1 3 25 μA
Output Short Circuit Current (Note 6) Output Sink Current 25 mA
WDI Input Threshold Logic Low 0.8 V
Logic High 2.0 V
WDI Input Current WDI = VOUT l 4 50 μA
WDI = 0V l –50 –8 μA
Power Fail Detector
PFI Input Threshold VCC = 5V l 1.25 1.3 1.35 V
PFI Input Threshold PSRR 0.3 mV/V
PFI Input Current ±0.01 ±25 nA
PFO Output Voltage (Note 6) ISINK = 3.2mA 0.4 V
ISOURCE = 1A 3.5 V
PFO Short Circuit Source Current PFI = HIGH, PFO = 0V 1 3 25 μA
(Note 6) PFI = LOW, PFO = VOUT 30 mA
PFI Comparator Response Time (falling) ΔVIN = –20mV, VOD = 15mV 2 μs
PFI Comparator Response Time (rising) ΔVIN = 20mV, VOD = 15mV 40 μs
(Note 6) with 10kΩ Pullup 8 μs
Chip Enable Gating
CE IN Threshold VIL 0.8 V
VIH 2.0 V
CE IN Pullup Current (Note 4) 3 μA
CE OUT Output Voltage ISINK = 3.2mA 0.4 V
ISOURCE = 3.0mA VOUT – 1.50 V
ISOURCE = 1μA, VCC = 0V VOUT – 0.05 V
CE Propagation Delay VCC = 5V, CL = 20pF 20 35 ns
l 20 45 ns
CE OUT Output Short Circuit Current Output Source Current 30 mA
Output Sink Current 35 mA
Note 1: Stresses beyond those listed under Absolute Maximum Ratings VOUT will be in Battery Backup Mode and will be switched to VBATT when
may cause permanent damage to the device. Exposure to any Absolute VCC falls below VBATT. If the latched logic level of the BACKUP pin is low,
Maximum Rating condition for extended periods may affect device VOUT will be in Battery Saving Mode when VCC falls below VBATT.
reliability and lifetime. Note 6: The output pins of BATT ON, LOW LINE, PFO, WDO, RESET and
Note 2: All voltage values are with respect to GND. RESET have weak internal pullups of typically 3A. However, external
Note 3: For military temperature range parts, consult the factory. pullup resistors may be used when higher speed is required.
Note 4: The input pins of PB RST, BACKUP and CE IN, have weak internal Note 7: The push-button reset input requires an active low signal.
pullups which pull to the supply when the input pins are floating. Internally, this input signal is debounced and timed for a minimum of
Note 5: The LTC1235 can be programmed either to provide or not to 40ms. When this condition is satisfied, the reset outputs go to the active
provide battery backup power to the VOUT pin during power failure. states. The reset outputs will remain in active states for a minimum of
The power down condition of VOUT is selected by the logic level of the 140ms from the moment the push-button reset input is released from
BACKUP pin which is latched internally when VCC falls through the reset logic low level.
voltage threshold. If the latched logic level of the BACKUP pin is high,

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 LTC1235
TYPICAL PERFORMANCE CHARACTERISTICS
Power Failure Input Threshold
VOUT vs IOUT VOUT vs IOUT vs Temperature
5.00 2.80 1.308
VCC = 5V VCC = 0V VCC = 5V
VBATT = 2.8V VBATT = 2.8V 1.306
4.95 TA = 25°C TA = 25°C

PFI INPUT THRESHOLD (V)

2.78

OUTPUT VOLTAGE (V)

OUTPUT VOLTAGE (V)

BACKUP MODE 1.304

4.90 SELECTED
SLOPE = 125Ω
1.302
SLOPE = 5Ω 2.76
4.85 1.300

1.298
2.74
4.80
1.296

4.75 2.72 1.294

0 10 20 30 40 50 0 100 200 300 400 500 –50 –25 0 25 50 75 100 125
LOAD CURRENT (mA) LOAD CURRENT (μA) TEMPERATURE (˚C)
1235 G01 1235 G02 1235 G03

RESET Output Voltage vs Reset Active Time vs Reset Voltage Threshold vs

SupplyVoltage Temperature Temperature
5 232 4.66
TA = 25°C VCC = 5V
EXTERNAL PULLUP = 10μA

RESET VOLTAGE THRESHOLD (V)

224 4.65
4 VBATT = 0V
RESET OUTPUT VOLTAGE (V)

RESET ACTIVE TIME (ms)

216 4.64
3

208 4.63
2
200 4.62

1
192 4.61

0 184 4.60
0 1 2 3 4 5 –50 –25 0 25 50 75 100 125 –50 –25 0 25 50 75 100 125
SUPPLY VOLTAGE (V) TEMPERATURE (°C) TEMPERATURE (°C)
1235 G04 1235 G05 1235 G06

Power Fail Comparator Power Fail Comparator Power Fail Comparator Response
Response Time Response Time Time with Pullup Resistor
6 6 6
PFO OUTPUT VOLTAGE (V)

PFO OUTPUT VOLTAGE (V)

PFO OUTPUT VOLTAGE (V)

VCC = 5V VCC = 5V VCC = 5V

5 TA = 25°C 5 5 TA = 25°C
TA = 25°C
4 4 4
3 VPFI + 3 3
PFO
2 1.3V – 30pF 2 VPFI + 2
PFO +5V
1 1 1.3V – 30pF 1
VPFI + 10k
0 0 0 PFO
1.3V – 30pF

1.305V 1.315V 1.315V

VPFI = 20mV STEP VPFI = 20mV STEP VPFI = 20mV STEP
1.285V 1.295V 1.295V

0 1 2 3 4 5 6 7 8 0 20 40 60 80 100 120 140 160 180 0 2 4 6 8 10 12 14 16 18

TIME (μs) TIME (μs) TIME (μs)
1235 G07 1235 G08 1235 G09

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LTC1235
PIN FUNCTIONS
VBATT (Pin 1): Backup battery input. When VCC falls below from the moment the push-button reset input is released
VBATT, the status of the BACKUP pin stored in the Memory from logic low level. Pulled to VCC with 60k.
Logic controls M2. If the status is high, auxiliary power,
Backup (Pin 8): Logic input to control the PMOS switch,
connected to VBATT is delivered to VOUT through M2. If the
M2, when VCC is lower than VBATT. While VCC is falling
status is low, the Memory Logic keeps M2 off and VOUT
through the reset voltage threshold, the status of the
is in Battery Saving Mode. If backup battery or auxiliary
BACKUP pin (logic low or logic high) is latched in Memory
power is not used, VBATT should be connected to GND.
Logic and used to turn on or off M2 when VCC is below
VOUT (Pin 2): Voltage output for backed up memory. By- VBATT. If the latched status of the BACKUP pin is high,
pass with a capacitor of 0.1μF or greater. During normal the Memory Logic turns on M2 when VCC falls to 50mV
operation, VOUT obtains power from VCC through an NMOS greater than VBATT. If the latched status of the BACKUP
power switch, M1, which can deliver up to 50mA and has a pin is low, the Memory Logic keeps M2 off even after VCC
typical on resistance of 5Ω. When VCC is lower than VBATT, falls below VBATT. If the BACKUP pin is left floating it will
the status of the BACKUP pin stored in Memory Logic be pulled high by an internal pullup and the LTC1235 will
controls M2. If the status is high, the Memory Logic turns provide battery backup when VCC falls.
on M2 and VOUT is internally switched to VBATT through
PFI (Pin 9): Power Failure Input. PFI is the noninverting
M2. If the status is low, the Memory Logic keeps M2 off
input to the Power Fail Comparator, C3. The inverting input
and VOUT is in Battery Saving Mode. If VOUT and VBATT
is internally connected to a 1.3V reference. The Power
are not used, connect VOUT to VCC.
Failure Output remains high when PFI is above 1.3V and
VCC (Pin 3): +5V supply input. The VCC pin should be goes low when PFI is below 1.3V. Connect PFI to GND or
bypassed with a 0.1μF capacitor. VOUT when C3 is not used.
GND (Pin 4): Ground pin. PFO (Pin 10): Power Failure Output from C3. PFO remains
BATT ON (Pin 5): Battery on logic output from comparator high when PFI is above 1.3V and goes low when PFI is
C2. BATT ON goes low when VOUT is internally connected below 1.3V. When VCC is lower than VBATT, C3 is shut
to VCC. The output typically sinks 35mA and can provide down and PFO is forced low.
base drive for an external PNP transistor to increase the WDI (Pin 11): Watchdog Input, WDI, is a three level
output current above the 50mA rating of VOUT. BATT ON input. Driving WDI either high or low for longer than the
goes high when VCC falls below VBATT, if the status of the watchdog time-out period, forces both RESET and WDO
BACKUP pin stored in Memory Logic is high and VOUT is low. Floating WDI disables the Watchdog Timer. The timer
switched to VBATT. resets itself with each transition of the Watchdog Input
LOW LINE (Pin 6): Logic output from comparator C1. (see Figure 11).
LOW LINE indicates a low line condition at the VCC input. CE OUT (Pin 12): Logic output from the Chip Enable gating
When VCC falls below the reset voltage threshold (4.65V circuit. When VCC is above the reset voltage threshold, CE
typically), LOW LINE goes low. As soon as VCC rises above OUT is a buffered replica of CE IN. When VCC is below
the reset voltage threshold, LOW LINE returns high (see the reset voltage threshold CE OUT is forced high (see
Figure 1). LOW LINE goes low when VCC drops below VBATT Figure 6).
(see Table 1).
CE IN (Pin 13): Logic input to the Chip Enable gating cir-
PB RST (Pin 7): Logic input for direct connection to a push- cuit. CE IN can be derived from microprocessor’s address
button. The push-button reset input requires an active low line and/or decoder output. See Applications Information
signal. Internally, this input signal is debounced and timed Section and Figure 6 for additional information.
for a minimum of 40ms. When this condition is satisfied,
WDO (Pin 14): Watchdog logic output. When the watch-
the reset pulse generator forces RESET to active low. The
dog input remains either high or low for longer than the
RESET signal will remain active low for a minimum of 140ms
watchdog time-out period, WDO goes low. WDO is set
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 LTC1235
PIN FUNCTIONS
high when ever there is a transition on the WDI pin, or prior to the time-out period, the reset pulse generator
LOW LINE goes low. The watchdog timer can be disabled also forces RESET to active low for a minimum of 140ms
by floating WDI (see Figure 11). for every time-out period (see Figure 11). Third, when the
PB RST pin stays active low for a minimum of 40ms,
RESET (Pin 15): Logic output for μP reset control. The
LTC1235 provides three ways to generate μP reset. First, RESET is forced low by reset pulse generator. The RESET
whenever VCC falls below either the reset voltage threshold signal will remain active low for a minimum of 140ms from
(4.65V, typically) or VBATT, RESET goes active low. After the moment the push-button reset input is released from
VCC returns to 5V, the reset pulse generator forces RESET logic low level.
to remain active low for a minimum of 140ms. Second, RESET (Pin 16): RESET is an active high logic output. It
when the watchdog timer is enabled but not serviced is the inverse of RESET.

BLOCK DIAGRAM

M2
VBATT VOUT

M1
VCC
BACKUP MEMORY
LOGIC
CHARGE
PUMP
–
C2 BATT ON
+

LOW LINE
+
C1
–
CE OUT
1.3V

GND
CE IN

–
PFO
PFI +
VCC OSC
60k
RESET
LEVEL SENSE
PB RST AND RESET PULSE
DEBOUNCE GENERATOR
RESET

TRANSITION WATCHDOG
WDI WDO
DETECTOR TIMER

1235 BD

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LTC1235
APPLICATIONS INFORMATION
Power Monitoring To help prevent mistriggering due to transient loads, VCC
pin should be bypassed with a 0.1μF capacitor with the
The LTC1235 uses a bandgap voltage reference and a
leads trimmed as short as possible.
precision voltage comparator C1 to monitor the 5V supply
input on VCC (see Block Diagram). When VCC falls below LOW LINE is the output of the precision voltage compara-
the reset voltage threshold, the reset outputs are forced tor C1. When VCC falls below the reset voltage threshold,
to active states. The reset voltage threshold accounts for LOW LINE goes low. LOW LINE returns high as soon as
a 5% variation on VCC, so the reset outputs become active VCC rises above the reset voltage threshold.
when VCC falls below 4.75V (4.65V typical). On power-up,
the reset signals are held active states for a minimum Push-Button Reset
of 140ms after the reset voltage threshold is reached to The LTC1235 provides an logic input pin for direct con-
allow the power supply and microprocessor to stabilize. nection to a push-button. The push-button reset input,
On power-down, the RESET signal remains active low PB RST, requires an active low signal. Internally, this input
even with VCC as low as 1V. This capability helps hold signal is debounced and timed for a minimum of 40ms.
the microprocessor in stable shutdown condition. Figure When this condition is satisfied, the reset pulse generator
1 shows the timing diagram of the RESET signal. forces the reset outputs to active states. The reset signals
The precision voltage comparator, C1, typically has 40mV will remain in active states for a minimum of 140ms from
of hysteresis which ensures that glitches at VCC pin do not the moment the push-button reset input is released from
activate the reset outputs. Response time is typically 10μs. logic low level (Figure 2).

V2 V2
VCC V1 V1 = RESET VOLTAGE THRESHOLD V1
V2 = RESET VOLTAGE THRESHOLD +
RESET THRESHOLD HYSTERESIS

RESET t1 t1

t1 = RESET ACTIVE TIME

LOW LINE

1235 F01

Figure 1. Reset Active Time

VCC = 5V
t1 LOGIC
PB RST
LOGIC LOW HIGH

t2

RESET
LOGIC HIGH
LOGIC LOW
RESET
1235 F02

t1 = PUSH-BUTTON RESET LOW TIME

t2 = RESET ACTIVE TIME

Figure 2. Push-Button Reset

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 LTC1235
APPLICATIONS INFORMATION
Voltage Output the battery which can damage lithium batteries. LTC1235
uses a charge pumped NMOS power switch to eliminate
During normal operation, the LTC1235 uses a charge
unwanted charging current while achieving low dropout
pumped NMOS power switch to achieve low dropout and
and low supply current. Since no current goes to the
low supply current. This power switch can deliver up to
substrate, the current collected by VBATT pin is strictly
50mA to VOUT from VCC and has a typical on resistance
junction leakage.
of 5. The VOUT pin should be bypassed with a capacitor of
0.1μF or greater to ensure stability. Use of a larger bypass Conditional Battery Backup
capacitor is advantageous for supplying current to heavy
transient loads. LTC1235 provides an unique feature to either allow VOUT to
be switched to VBATT or to disable the CMOS RAM battery
When operating currents larger than 50mA are required backup function when primary power is lost. Disabling
from VOUT, or a lower dropout (VCC - VOUT voltage differ- the battery backup function is useful in conserving the
ential) is desired, the LTC1235 provides BATT ON output backup battery’s life when the SRAM doesn’t need battery
to drive the base of external PNP transistor (Figure 3). backup during long term storage of a computer system,
Another alternative to provide higher current is to connect or delivery of the computer system to the end user.
a high current Schottky diode from the VCC pin to the VOUT
pin to supply the extra current. The BACKUP pin (Pin 8) is used to serve this feature on
power-down. When VCC is falling through the reset volt-
ANY PNP POWER TRANSISTOR
age threshold, the status of the BACKUP pin (logic low
or logic high) is stored in the Memory Logic (see Block
R1 Diagram). If the stored status is logic high and VCC fall to
50mV greater than VBATT, a 125Ω PMOS switch, M2, con-
BATT ON
+5V VCC VOUT nects the VBATT input to VOUT and the battery switchover
0.1μF LTC1235 0.1μF comparator, C2, shuts off the NMOS power switch, M1. M2
VBATT is designed for very low dropout voltage (input-to-output
+3V GND differential). This feature is advantageous for low current
1235 F03
applications such as battery backup in CMOS RAM and
other low power CMOS circuitry. If the stored status is
Figure 3. Using BATT ON to Drive External PNP Transistor logic low and VCC falls to 50mV greater than VBATT, the
Memory Logic keeps M2 off and C2 shuts off M1. VOUT is
The LTC1235 is protected for safe area operation with short in Battery Saving Mode (see Figure 4). The supply current
circuit limit. Output current is limited to approximately in both mode is 1μA maximum.
200mA. If the device is overloaded for a long period of On power-ups, C2 keeps M1 off before VCC reaches 70mV
time, thermal shutdown turns the power switch off until higher than VBATT. On the first power-up after the bat-
the device cools down. The threshold temperature for tery is replaced (with power off), the status stored in the
thermal shutdown is approximately 155°C with about 10°C Memory Logic is undetermined. VOUT could be either in
of hysteresis which prevents the device from oscillating Battery Backup Mode or in Battery Saving Mode. When
in and out of shutdown. VCC is 70mV greater than VBATT, M1 connects VOUT to VCC.
The PNP switch was not chosen for the internal power C2 has typically 20mV of hysteresis to prevent spurious
switch because it injects unwanted current into the switching when VCC remains nearly equal to VBATT and the
substrate. This current is collected by the VBATT pin in status stored in the Memory Logic is high. The response
competitive devices and adds to the charging current of time of C2 is approximately 20μs.

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LTC1235
APPLICATIONS INFORMATION
VOUT IN BATTERY SAVING MODE Replacing the Backup Battery with Power On
BACKUP When changing the backup battery with system power on,
LOGIC LOW
spurious resets can occur while battery is removed due to
battery standby current. Although battery standby current
VCC
RESET VOLTAGE THRESHOLD is only a tiny leakage current, it can still charge up the
VBATT stray capacitance on the VBATT pin. The oscillation cycle
is as follows: When VBATT reaches within 50mV of VCC,
VOUT
the LTC1235 switches to battery backup or battery sav-
Hi-Z ing mode. In either case, the battery supply current pulls
VBATT low and the device goes back to normal operation.
The leakage current then charges up the VBATT pin again
VOUT IN BATTERY BACKUP MODE
and the cycle repeats.
LOGIC
BACKUP
HIGH
If spurious resets during battery replacement pose no
problems, then no action is required. Otherwise, two
methods can be used to eliminate this problem. First, a
VCC RESET VOLTAGE THRESHOLD capacitor from VBATT to GND will allow time for battery
VBATT
replacement by slowing the charge rate. For example,
the battery standby current is 1μA maximum over tem-
perature and the external capacitor required to slow the
VOUT
VOUT = VBATT charge rate is:
1235 F04
 1μA 
CEXT
TREQ'D  
 VCC ± VBATT 
Figure 4. Conditional Battery Backup Operation

The operating voltage at the VBATT pin ranges from 2.0V where TREQ’D is the maximum time required to replace the
to 4.25V. High value capacitors, such as electrolytic or backup battery. With VCC = 4.5V, VBATT = 3V and TREQ’D
faradsize double layer capacitors, can be used for short = 3 sec, the value for external capacitor is 2μF. Second,
term memory backup instead of a battery. For capacitor a resistor from VBATT to GND will hold the pin low while
changing the battery. For example, the battery standby
backup, see Typical Applications. The charging resistor
current is 1μA maximum over temperature and the external
for recharging rechargeable batteries should be con-
resistor required to hold VBATT below VCC is:
nected to VOUT through a diode since this eliminates the
discharge path that exists when VCC collapses and RAM VCC ± 50mV
R≤
is not backed up (Figure 5). 1μA
V
I = OUT
– VBATT – VD With VCC = 4.5V, a 4.3M resistor will work. With a 3V bat-
R
1N4148 tery, this resistor will draw only 0.7μA from the battery,
R which is negligible in most cases.
+5V VCC VOUT
0.1μF RAM
If the battery connections are made with long wires or PC
0.1μF
LTC1235
traces, inductive spikes can be generated during battery
BACKUP I/O LINE
replacement. Even if a resistor is used to prevent spurious
VBATT μP resets as described above, these spikes can take the VBATT
GND
+3V
4 1235 F05
pin below GND violating the LTC1235 absolute maximum
ratings. A 0.1μF capacitor from VBATT to GND is recom-
mended to eliminate these potential spikes when battery
Figure 5. Charging External Battery Through VOUT replacement is made through long wires.
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10
 LTC1235

Table 1 shows the state of each pin during battery backup. IN and CE OUT, control the Chip Enable or Write inputs of
If the backup battery is not used, connect VBATT to GND CMOS RAM. When VCC is +5V, CE OUT follows CE IN with
and VOUT to VCC. a typical propagation delay of 20ns. When VCC falls below
the reset voltage threshold or VBATT, CE OUT is forced
Table 1. Input and Output Status in Battery Backup Mode
high, independent of CE IN. CE OUT is an alternative signal
SIGNAL STATUS
to drive the CE, CS, or Write input of battery-backed up
VCC C2 monitors VCC for active switchover.
CMOS RAM. CE OUT can also be used to drive the Store
BACKUP BACKUP is ignored.
or Write input of an EEPROM, EAROM or NOVRAM to
VOUT VOUT is connected to VBATT through an internal PMOS switch.
achieve similar protection. Figure 6 shows the timing
VBATT The supply current is 1μA maximum.
diagram of CE IN and CE OUT.
BATT ON Logic high. The open circuit output voltage is equal to VOUT.
PFI Power Failure Input is ignored. CE IN can be derived from the microprocessor’s address
PFO Logic low
decoder output. Figure 7 shows a typical nonvolatile CMOS
PB RST PB RST is ignored.
RAM application.
RESET Logic low
RESET Logic high. The open circuit output voltage is equal to VOUT.
+5V VCC VOUT VCC
LOW LINE Logic low + 0.1μF
0.1μF 10μF 62512
LTC1235 RAM
WDI Watchdog Input is ignored.
CE OUT CS
WDO Logic high. The open circuit output voltage is equal to VOUT. 20ns PROPAGATION DELAY
GND
VBATT
CE IN Chip Enable Input is ignored. CE IN FROM DECODER
+3V BACKUP
CE OUT Logic high. The open circuit output voltage is equal to VOUT.
GND RESET
TO μP 1235 F07

Memory Protection
The LTC1235 includes memory protection circuitry which Figure 7. A Typical Nonvolatile CMOS RAM Application
ensures the integrity of the data in memory by preventing
write operations when VCC is at invalid level. Two pins, CE

BACKUP = VCC

V2
VCC V1 V1 = RESET VOLTAGE THRESHOLD
V2 = RESET VOLTAGE THRESHOLD +
RESET THRESHOLD HYSTERESIS

CE IN

CE OUT VOUT = VBATT

VOUT = VBATT

1235 F06

Figure 6. Timing Diagram for CE IN and CE OUT

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11
LTC1235
APPLICATIONS INFORMATION
Power Fail Warning R1
VHYST = 5V = 850mV
The LTC1235 generates a Power Failure Output (PFO) for R3
early warning of failure in the microprocessor’s power sup-
ply. This is accomplished by comparing the Power Failure R3 ≈ 5.88 R1
Input (PFI) with an internal 1.3V reference. PFO goes low Choose R3 = 300k and R1 = 51k. Also select R4 = 10k
when the voltage at PFI pin is less than 1.3V. Typically which is much smaller than R3.
PFI is driven by an external voltage divider (R1 and R2 in
51k (5V ± 1.3V)51k 
Figures 8 and 9) which senses either an unregulated DC 7.5V = 1.3V 1+ ± 
input or a regulated 5V output. The voltage divider ratio can  R2 1.3V(310k) 
be chosen such that the voltage at PFI pin falls below 1.3V R2 = 9.7k, Choose nearest 5% resistor 10k and recalculate
several milliseconds before the +5V supply falls below the VL,
maximum reset voltage threshold 4.75V. PFO is normally

51k (5V ± 1.3V)51k 
used to interrupt the microprocessor to execute shutdown VL =1.3V 1+ ±  = 7.32V
procedure between PFO and RESET or RESET.  10k 1.3V(310k) 
The power fail comparator, C3, does not have hysteresis.
51k 51k 
Hysteresis can be added however, by connecting a resistor VH =1.3V 1+ +  = 8.151V
 10k 300k 
between the PFO output and the noninverting PFI input
pin as shown in Figures 8 and 9. The upper and lower trip (7.32V – 6.25V)
points in the comparator are established as follows: = 10.7ms
100mV/ms
When PFO output is low, R3 sinks current from the sum-
ming junction at the PFI pin. VHYST = 8.151V – 7.32V = 831mV

R1 R1 
VH = 1.3V 1+ +  LT1086-5
 R2 R3  VIN ≥ 7.5V
VIN VOUT +5V
VCC
+ + 0.1μF
10μF
When PFO output is high, the series combination of R3
ADJ 100μF
R4 LTC1235
R3 10k
R1 300k
and R4 source current into the PFI summing junction. 51k PFO BACKUP
TO μP
PFI GND

R1 (5V ± 1.3V)R1 
VL =1.3V 1+ ±  R2
 R2 1.3V(R3+R4)  10k
1235 F08

R1 Figure 8. Monitoring Unregulated DC Supply with the

Assuming R4«R3,VHYST = 5V
R3 LTC1235 Power Fail Comparator

Example 1: The circuit in Figure 8 demonstrates the use VIN ≥ 6.5V LT1086-5 10μF 0.1μF
+5V
of the power fail comparator to monitor the unregulated +
VIN VOUT
+
VCC
10μF ADJ R1 R4
power supply input. Assuming the rate of decay of the 27k 10k
LTC1235
R3
supply input VIN is 100mV/ms and the total time to execute 2.7M
PFO BACKUP
a shut-down procedure is 8ms. Also the noise of VIN is PFI GND TO μP

200mV. With these assumptions in mind, we can reason- R2

8.2k
ably set VL = 7.5V which 1.25V greater than the sum of R5
1235 F09

maximum reset voltage threshold and the dropout voltage 3.3k

of LT1086-5 (4.75V + 1.5V) and VHYST = 850mV.

Figure 9. Monitoring Regulated DC Supply with the
LTC1235 Power Fail Comparator
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12
 LTC1235
APPLICATIONS INFORMATION
The 10.7ms allows enough time to execute shut-down time-out period and reset active time. The watchdog time-
procedure for microprocessor and 831mV of hysteresis out period is restarted as soon as the reset outputs are
would prevent PFO from going low due to the noise of VIN. inactive. When either a high-to-low or low-to-high transi-
Example 2: The circuit in Figure 9 can be used to mea- tion occurs at the WDI pin prior to time-out, the watchdog
sure the regulated 5V supply to provide early warning of time is reset and begins to time out again. To ensure the
power failure. Because of variations in the PFI threshold, watchdog time does not time out, either a high-to-low or
this circuit requires adjustment to ensure that the PFI low-to-high transition on the WDI pin must occur at or
comparator trips before the reset threshold is reached. less than the minimum time-out period. If the input to the
Adjust R5 such that the PFO output goes low when the WDI pin remains either high or low, reset pulses will be
VCC supply reaches the desired level (e.g., 4.85V). issued every 1.6 seconds typically. The watchdog timer
can be deactivated by floating the WDI pin. The timer
Monitoring the Status of the Battery is also disabled when VCC falls below the reset voltage
threshold or VBATT.
C3 can also monitor the status of the memory backup
battery (Figure 10). If desired, the CE OUT can be used to The Watchdog Output, WDO, goes low if the watchdog timer
apply a test load to the battery. Since CE OUT is forced high is allowed to time out and remains low until set high by the
in battery backup mode, the test load will not be applied next transition on the WDI pin. WDO is also set high when
to the battery while it is in use, even if the microprocessor VCC falls below the reset voltage threshold or VBATT.
is not powered. +5V

Watchdog Timer VBATT VCC

LOW BATTERY SIGNAL
R1 PFO
The LTC1235 provides a watchdog timer function to monitor 1M
LTC1235
TO μP I/O PIN

the activity of the microprocessor. If the microprocessor PFI

BACKUP
does not toggle the Watchdog Input (WDI) within the +3V R2 TO μP I/O PIN
1M CE IN
time-out period, the reset outputs are forced to active
states for a minimum of 140ms. The watchdog time-out CE OUT GND

period is fixed at 1.0 second minimum on the LTC1235.

RL 20k
This time-out period provides adequate time for many
systems to service the watchdog timer immediately after OPTIONAL TEST LOAD
1235 F10

a reset. Figure 11 shows the timing diagram of watchdog

Figure 10. Backup Battery Monitor with Optional Test Load

VCC = 5V
WDI

t1 = RESET ACTIVE TIME

t2 = WATCHDOG TIME-OUT PERIOD

WDO

t2 t2

RESET t1 t1 t1
1235 F11

Figure 11. Watchdog Time-out Period and Reset Active Time

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13
LTC1235
TYPICAL APPLICATIONS
Capacitor Backup with 74HC4016 Switch

+5V
VCC VOUT
0.1μF 0.1μF
R1
10 11 12 14 LTC1235
10k
1 2
74HC4016 VBATT LOW LINE

R2
30k 7 13
+ GND
100μF

1235 TA3

Write Protect for Additional RAMs

0.1μF
+5V VCC VOUT VCC
+
0.1μF 10μF 62512
LTC1235 RAMA
CE OUT CS
VBATT 20ns
PROPAGATION
BACKUP CE IN DELAY
+3V
LOW LINE

GND
0.1μF
VCC
62128
RAMB
CSA CSB
CS1
CS2
CSC 0.1μF
VCC
62128
μP RAMC
SYSTEM CS1
CS2

OPTIONAL CONNECTION FOR

ADDITIONAL RAMs
LTC1235 TA4

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14
 LTC1235
PACKAGE DESCRIPTION
N Package
16-Lead PDIP (Narrow .300 Inch)
(Reference LTC DWG # 05-08-1510)
.770*
(19.558)
MAX

16 15 14 13 12 11 10 9

.255 ± .015*
(6.477 ± 0.381)

1 2 3 4 5 6 7 8

.300 – .325 .130 ± .005 .045 – .065

(7.620 – 8.255) (3.302 ± 0.127) (1.143 – 1.651)

.020
(0.508)
MIN .065
.008 – .015
(1.651)
(0.203 – 0.381) TYP
+.035
.325 –.015
.120 .100 .018 ± .003

( 8.255
+0.889
–0.381 ) (3.048)
MIN
(2.54)
BSC
(0.457 ± 0.076)

NOTE:
INCHES
1. DIMENSIONS ARE N16 1002
MILLIMETERS
*THESE DIMENSIONS DO NOT INCLUDE MOLD FLASH OR PROTRUSIONS.
MOLD FLASH OR PROTRUSIONS SHALL NOT EXCEED .010 INCH (0.254mm)

SW Package
16-Lead Plastic Small Outline (Wide .300 Inch)
(Reference LTC DWG # 05-08-1620)
.030 ±.005 .050 BSC .045 ±.005 .398 – .413
TYP (10.109 – 10.490)
NOTE 4
N 16 15 14 13 12 11 10 9

.420 .325 ±.005

MIN
NOTE 3 .394 – .419
(10.007 – 10.643)

1 2 3 N/2 N/2

RECOMMENDED SOLDER PAD LAYOUT

1 2 3 4 5 6 7 8

.291 – .299
(7.391 – 7.595)
NOTE 4 .037 – .045
.093 – .104
.010 – .029 × 45° (0.940 – 1.143)
(2.362 – 2.642)
(0.254 – 0.737)
.005
(0.127)
RAD MIN 0° – 8° TYP

.050
.009 – .013 (1.270) .004 – .012
(0.229 – 0.330) NOTE 3 BSC (0.102 – 0.305)
.014 – .019
.016 – .050
(0.356 – 0.482)
(0.406 – 1.270)
TYP
NOTE:
INCHES
1. DIMENSIONS IN S16 (WIDE) 0502
(MILLIMETERS)
2. DRAWING NOT TO SCALE
3. PIN 1 IDENT, NOTCH ON TOP AND CAVITIES ON THE BOTTOM OF PACKAGES ARE THE MANUFACTURING OPTIONS.
THE PART MAY BE SUPPLIED WITH OR WITHOUT ANY OF THE OPTIONS
4. THESE DIMENSIONS DO NOT INCLUDE MOLD FLASH OR PROTRUSIONS.
MOLD FLASH OR PROTRUSIONS SHALL NOT EXCEED .006" (0.15mm)
1235fa

15
Information furnished by Linear Technology Corporation is believed to be accurate and reliable.
However, no responsibility is assumed for its use. Linear Technology Corporation makes no representa-
tion that the interconnection of its circuits as described herein will not infringe on existing patent rights.
LTC1235
RELATED PARTS
PART NUMBER DESCRIPTION COMMENTS
LTC690 Single Channel Supervisor UL recognized battery backup
LTC691 Single Channel Supervisor UL recognized and conditional battery backup, RAM protect
LTC692 Single Channel Supervisor UL recognized battery backup
LTC693 Single Channel Supervisor UL recognized and conditional battery backup, RAM protect
LTC694 Single Channel Supervisor UL recognized battery backup
LTC695 Single Channel Supervisor UL recognized and conditional battery backup, RAM protect
LTC699 Single Channel Supervisor Microprocessor Supervisory Circuit

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LT 0708 REV A • PRINTED IN USA

16 Linear Technology Corporation

1630 McCarthy Blvd., Milpitas, CA 95035-7417
(408) 432-1900 ● FAX: (408) 434-0507 ● [Link] © LINEAR TECHNOLOGY CORPORATION 1992
Mouser Electronics

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