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VHDL Dataflow Coding Guide

This document provides an introduction to VHDL coding using the dataflow style. It explains the basic format of a VHDL file including the library information, entity, and architecture. The entity defines the input and output ports and the architecture contains the concurrent statements that define the output expressions in terms of the inputs. It provides examples of half adder, full adder, half subtractor, full subtractor, multiplexer, and demultiplexer circuits coded in VHDL dataflow style to illustrate the concepts.

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anupnaskar naskar
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100 views6 pages

VHDL Dataflow Coding Guide

This document provides an introduction to VHDL coding using the dataflow style. It explains the basic format of a VHDL file including the library information, entity, and architecture. The entity defines the input and output ports and the architecture contains the concurrent statements that define the output expressions in terms of the inputs. It provides examples of half adder, full adder, half subtractor, full subtractor, multiplexer, and demultiplexer circuits coded in VHDL dataflow style to illustrate the concepts.

Uploaded by

anupnaskar naskar
Copyright
© © All Rights Reserved
We take content rights seriously. If you suspect this is your content, claim it here.
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Download as PDF, TXT or read online on Scribd
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**Study the Bhaskar books notes (page1-24, 54-72) to

learn the language better


Format of VHDL Coding (dataflow style)
Library ieee;
use ieee.std_logic_1164.all;

entity entity_name is port(A,B,C :in bit;


X,Y :out bit);
end entity_name;

architecture architecture_name of entity_name is


begin
----------------
concurrent statements (output boolean expressions)
----------------
end architecture_name;
Points to remember
1. First two lines give the library information
2. Program has two major parts-Entity and Architecture.
Entity gives the information of Input and output ports like the port name,
number of ports, type of ports (IN,OUT etc. )
Architecture gives the information about the operation of the circuit, the
final Boolean expression of the output in terms of the input is written in the
architecture body.

3. Entity name should be same in all three places. It should not be any
reserved words used in VHDL (find the list in the Bhaskar Book notes-page
20)
4. Architecture name should be different from entity name. No reserved
words are allowed to use.
Some examples:
1. Half adder (dataflow style)

Library ieee;
use ieee.std_logic_1164.all;

entity half_adder is
port(A,B:in bit;
SUM,CARRY:out bit);
end half_adder;

architecture data of half_adder is


begin
SUM<= A xor B;
CARRY <= A and B;
end data
2. Full adder (dataflow style)

Library ieee;
use ieee.std_logic_1164.all;

entity full_adder is port(A,B,C :in bit;


S,Cout:out bit);
end full_adder;

architecture data of full_adder is


begin
S<= A xor B xor C;
Cout <= ((A and B) or (B and C) or (A and C));
end data;

3. Half subtractor (Dataflow modeling style)


Library ieee;
use ieee.std_logic_1164.all;

entity half_sub is
port(A,B:in bit;
D,Br:out bit);
end half_sub;

architecture data of half_sub is


begin
D<= A xor B;
Br<= (B and (not A));
end data;

4. Full Subtractor

Library ieee;
use ieee.std_logic_1164.all;

entity full_sub is
port(A,B,C: in bit;
DIFF,BORROW:out bit);
end full_sub;
architecture data of full_sub is
begin
DIFF<= A xor B xor C;
BORROW <= (B and (not A)) or (B and C) or (C and (not A));
end data;

5. Multiplexer (4:1 MUX)

Library ieee;
use ieee.std_logic_1164.all;

entity mux is
port(S1,S0,I0,I1,I2,I3:in bit; Y:out bit);
end mux;

architecture data of mux is


begin
Y<= ((not S0) and (not S1) and I0) or
(S0 and (not S1) and I1) or
((not S0) and S1 and I2) or
(S0 and S1 and I3);
end data;
6. Demultiplexer

Library ieee;
use ieee.std_logic_1164.all;

entity demux is
port(B,A,X:in bit; D0,D1,D2,D3:out bit);
end demux;

architecture data of demux is


begin
D0<= ((Not B) and (Not A) and X);
D1<= ((Not B) and A and X);
D2<= (B and (Not A) and X);
D3<= (B and A and X);
end data;

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