Features

• Fast Read Access Time – 90 ns

• 5-volt Only Reprogramming
• Sector Program Operation
– Single Cycle Reprogram (Erase and Program)
– 2048 Sectors (256 Bytes/Sector)
– Internal Address and Data Latches for 256 Bytes
• Internal Program Control and Timer
• Hardware and Software Data Protection
• Two 16K Bytes Boot Blocks with Lockout
•
•
Fast Sector Program Cycle Time – 10 ms
DATA Polling for End of Program Detection
4-megabit
• Low Power Dissipation
– 40 mA Active Current
(512K x 8)
– 100 µA CMOS Standby Current
• Typical Endurance > 10,000 Cycles 5-volt Only
• Single 5V ± 10% Supply
• CMOS and TTL Compatible Inputs and Outputs 256-byte Sector
Description
Flash Memory
The AT29C040A is a 5-volt only in-system Flash Programmable and Erasable Read
Only Memory (PEROM). Its 4 megabits of memory is organized as 524,288 words by
8 bits. Manufactured with Atmel’s advanced nonvolatile CMOS EEPROM technology,
AT29C040A
the device offers access times up to 90 ns, and a low 220 mW power dissipation.
When the device is deselected, the CMOS standby current is less than 100 µA. The
device endurance is such that any sector can typically be written to in excess of
10,000 times. The programming algorithm is compatible with other devices in Atmel’s
5-volt only Flash family.

PLCC Top View

Pin Configurations
VCC
A18
A12
A15
A16

A17
WE

Pin Name Function

4
3
2
1
32
31
30

A7 5 29 A14
A0 - A18 Addresses A6 6 28 A13
A5 7 27 A8
CE Chip Enable A4 8 26 A9
A3 9 25 A11
A2 10 24 OE
OE Output Enable A1 11 23 A10
A0 12 22 CE
WE Write Enable I/O0 13 21 I/O7
14
15
16
17
18
19
20

I/O0 - I/O7 Data Inputs/Outputs

I/O1
I/O2
GND
I/O3
I/O4
I/O5
I/O6

NC No Connect
TSOP Top View – Type 1
DIP Top View
A11 1 32 OE
A18 1 32 VCC A9 2 31 A10
A16 2 31 WE A8 3 30 CE
A15 3 30 A17 A13 4 29 I/O7
A12 4 29 A14 A14 5 28 I/O6
A7 5 28 A13 A17 6 27 I/O5
A6 6 27 A8 WE 7 26 I/O4
A5 7 26 A9 VCC 8 25 I/O3
A4 8 25 A11 A18 9 24 GND
A3 9 24 OE A16 10 23 I/O2
A2 10 23 A10 A15 11 22 I/O1
A1 11 22 CE A12 12 21 I/O0
A0 12 21 I/O7 A7 13 20 A0
I/O0 13 20 I/O6 A6 14 19 A1
I/O1 14 19 I/O5 A5 15 18 A2
I/O2 15 18 I/O4 A4 16 17 A3
Rev. 0333I–FLASH–05/02
GND 16 17 I/O3

1
 To allow for simple in-system reprogrammability, the AT29C040A does not require high input
voltages for programming. Five-volt-only commands determine the operation of the device.
Reading data out of the device is similar to reading from an EPROM. Reprogramming the
AT29C040A is performed on a sector basis; 256 bytes of data are loaded into the device and
then simultaneously programmed.
During a reprogram cycle, the address locations and 256 bytes of data are internally latched,
freeing the address and data bus for other operations. Following the initiation of a program
cycle, the device will automatically erase the sector and then program the latched data using
an internal control timer. The end of a program cycle can be detected by DATA polling of I/O7.
Once the end of a program cycle has been detected, a new access for a read or program can
begin.

Block Diagram

Device READ: The AT29C040A is accessed like an EPROM. When CE and OE are low and WE is
high, the data stored at the memory location determined by the address pins is asserted on
Operation
the outputs. The outputs are put in the high impedance state whenever CE or OE is high. This
dual-line control gives designers flexibility in preventing bus contention.
BYTE LOAD: Byte loads are used to enter the 256 bytes of a sector to be programmed or
the software codes for data protection. A byte load is performed by applying a low pulse on the
WE or CE input with CE or WE low (respectively) and OE high. The address is latched on the
falling edge of CE or WE, whichever occurs last. The data is latched by the first rising edge of
CE or WE.
PROGRAM: The device is reprogrammed on a sector basis. If a byte of data within a sector
is to be changed, data for the entire sector must be loaded into the device. Any byte that is not
loaded during the programming of its sector will be erased to read FFH. Once the bytes of a
sector are loaded into the device, they are simultaneously programmed during the internal
programming period. After the first data byte has been loaded into the device, successive
bytes are entered in the same manner. Each new byte to be programmed must have its high
to low transition on WE (or CE) within 150 µs of the low to high transition of WE (or CE) of the
preceding byte. If a high to low transition is not detected within 150 µs of the last low to high
transition, the load period will end and the internal programming period will start. A8 to A18
specify the sector address. The sector address must be valid during each high to low transition
of WE (or CE). A0 to A7 specify the byte address within the sector. The bytes may be loaded
in any order; sequential loading is not required. Once a programming operation has been initi-
ated, and for the duration of tWC, a read operation will effectively be a polling operation.

2 AT29C040A
0333I–FLASH–05/02
 AT29C040A

SOFTWARE DATA PROTECTION: A software controlled data protection feature is avail-

able on the AT29C040A. Once the software protection is enabled a software algorithm must
be issued to the device before a program may be performed. The software protection feature
may be enabled or disabled by the user; when shipped from Atmel, the software data protec-
tion feature is disabled. To enable the software data protection, a series of three program
commands to specific addresses with specific data must be performed. After the software data
protection is enabled the same three program commands must begin each program cycle in
order for the programs to occur. All software program commands must obey the sector pro-
gram timing specifications. The SDP feature protects all sectors, not just a single sector. Once
set, the software data protection feature remains active unless its disable command is issued.
Power transitions will not reset the software data protection feature, however the software fea-
ture will guard against inadvertent program cycles during power transitions.
After setting SDP, any attempt to write to the device without the three-byte command
sequence will start the internal write timers. No data will be written to the device; however, for
the duration of tWC, a read operation will effectively be a polling operation.
After the software data protection’s 3-byte command code is given, a byte load is performed
by applying a low pulse on the WE or CE input with CE or WE low (respectively) and OE high.
The address is latched on the falling edge of CE or WE, whichever occurs last. The data is
latched by the first rising edge of CE or WE. The 256 bytes of data must be loaded into each
sector by the same procedure as outlined in the program section under device operation.
HARDWARE DATA PROTECTION: Hardware features protect against inadvertent pro-
grams to the AT29C040A in the following ways: (a) VCC sense – if VCC is below 3.8V (typical),
the program function is inhibited; (b) VCC power on delay – once VCC has reached the V CC
sense level, the device will automatically time out 5 ms (typical) before programming; (c) Pro-
gram inhibit – holding any one of OE low, CE high or WE high inhibits program cycles; and (d)
Noise filter – pulses of less than 15 ns (typical) on the WE or CE inputs will not initiate a pro-
gram cycle.
PRODUCT IDENTIFICATION: The product identification mode identifies the device and
manufacturer as Atmel. It may be accessed by hardware or software operation. The hardware
operation mode can be used by an external programmer to identify the correct programming
algorithm for the Atmel product. In addition, users may wish to use the software product identi-
fication mode to identify the part (i.e. using the device code), and have the system software
use the appropriate sector size for program operations. In this manner, the user can have a
common board design for 256K to 4-megabit densities and, with each density’s sector size in
a memory map, have the system software apply the appropriate sector size.
For details, see Operating Modes (for hardware operation) or Software Product Identification.
The manufacturer and device code is the same for both modes.
DATA POLLING: The AT29C040A features DATA polling to indicate the end of a program
cycle. During a program cycle an attempted read of the last byte loaded will result in the com-
plement of the loaded data on I/O7. Once the program cycle has been completed, true data is
valid on all outputs and the next cycle may begin. DATA polling may begin at any time during
the program cycle.
TOGGLE BIT: In addition to DATA polling the AT29C040A provides another method for
determining the end of a program or erase cycle. During a program or erase operation, suc-
cessive attempts to read data from the device will result in I/O6 toggling between one and
zero. Once the program cycle has completed, I/O6 will stop toggling and valid data will be
read. Examining the toggle bit may begin at any time during a program cycle.
OPTIONAL CHIP ERASE MODE: The entire device can be erased by using a 6-byte soft-
ware code. Please see Software Chip Erase application note for details.

3
0333I–FLASH–05/02
 BOOT BLOCK PROGRAMMING LOCKOUT: The AT29C040A has two designated memory
blocks that have a programming lockout feature. This feature prevents programming of data in
the designated block once the feature has been enabled. Each of these blocks consists of 16K
bytes; the programming lockout feature can be set independently for either block. While the
lockout feature does not have to be activated, it can be activated for either or both blocks.
These two 16K memory sections are referred to as boot blocks. Secure code which will bring
up a system can be contained in a boot block. The AT29C040A blocks are located in the first
16K bytes of memory and the last 16K bytes of memory. The boot block programming lockout
feature can therefore support systems that boot from the lower addresses of memory or the
higher addresses. Once the programming lockout feature has been activated, the data in that
block can no longer be erased or programmed; data in other memory locations can still be
changed through the regular programming methods. To activate the lockout feature, a series
of seven program commands to specific addresses with specific data must be performed.
Please see Boot Block Lockout Feature Enable Algorithm.
If the boot block lockout feature has been activated on either block, the chip erase function will
be disabled.
BOOT BLOCK LOCKOUT DETECTION: A software method is available to determine
whether programming of either boot block section is locked out. See Software Product Identifi-
cation Entry and Exit sections. When the device is in the software product identification mode,
a read from location 00002H will show if programming the lower address boot block is locked
out while reading location 7FFF2H will do so for the upper boot block. If the data is FE, the cor-
responding block can be programmed; if the data is FF, the program lockout feature has been
activated and the corresponding block cannot be programmed. The software product identifi-
cation exit mode should be used to return to standard operation.

Absolute Maximum Ratings*

Temperature Under Bias................................ -55°C to +125°C *NOTICE: Stresses beyond those listed under “Absolute
Maximum Ratings” may cause permanent dam-
Storage Temperature ..................................... -65°C to +150°C age to the device. This is a stress rating only and
functional operation of the device at these or any
All Input Voltages (including NC Pins) other conditions beyond those indicated in the
with Respect to Ground ...................................-0.6V to +6.25V operational sections of this specification is not
implied. Exposure to absolute maximum rating
All Output Voltages conditions for extended periods may affect
with Respect to Ground .............................-0.6V to VCC + 0.6V device reliability.

Voltage on OE
with Respect to Ground ...................................-0.6V to +13.5V

4 AT29C040A
0333I–FLASH–05/02
 AT29C040A

DC and AC Operating Range

AT29C040A-90 AT29C040A-12 AT29C040A-15 AT29C040A-20
Operating Com. 0°C - 70°C 0°C - 70°C 0°C - 70°C 0°C - 70°C
Temperature (Case)
Ind. -40°C - 85°C -40°C - 85°C -40°C - 85°C -40°C - 85°C
VCC Power Supply 5V ± 10% 5V ± 10% 5V ± 10% 5V ± 10%

Note: Not recommended for New Designs.

Operating Modes
Mode CE OE WE Ai I/O
Read VIL VIL VIH Ai DOUT
(2)
Program VIL VIH VIL Ai DIN
Standby/Write Inhibit VIH X(1) X X High Z
Program Inhibit X X VIH
Program Inhibit X VIL X
Output Disable X VIH X High Z
Product Identification
Hardware VIL VIL VIH A1 - A18 = VIL, A9 = VH,(3) A0 = V IL Manufacturer Code(4)
A1 - A18 = VIL, A9 = VH,(3) A0 = VIH Device Code(4)
Software(5) A0 = VIL Manufacturer Code(4)
A0 = VIH Device Code(4)
Notes: 1. X can be VIL or VIH.
2. Refer to AC Programming Waveforms.
3. VH = 12.0V ± 0.5V.
4. Manufacturer Code: 1F, Device Code: A4.
5. See details under Software Product Identification Entry/Exit.

DC Characteristics
Symbol Parameter Condition Min Max Units
ILI Input Load Current VIN = 0V to VCC 10 µA
ILO Output Leakage Current VI/O = 0V to VCC 10 µA
ISB1 VCC Standby Current CMOS CE = V CC - 0.3V to VCC Com. 100 µA
Ind. 300 µA
ISB2 VCC Standby Current TTL CE = 2.0V to VCC 3 mA
ICC VCC Active Current f = 5 MHz; IOUT = 0 mA 40 mA
VIL Input Low Voltage 0.8 V
VIH Input High Voltage 2.0 V
VOL Output Low Voltage IOL = 2.1 mA 0.45 V
VOH1 Output High Voltage IOH = -400 µA 2.4 V
VOH2 Output High Voltage CMOS IOH = -100 µA; VCC = 4.5V 4.2 V

5
0333I–FLASH–05/02
AC Read Characteristics
AT29C040A-90 AT29C040A-12 AT29C040A-15 AT29C040A-20
Symbol Parameter Min Max Min Max Min Max Min Max Units
tACC Address to Output Delay 90 120 150 200 ns
(1)
tCE CE to Output Delay 90 120 150 200 ns
tOE(2) OE to Output Delay 0 40 0 50 0 70 0 80 ns
(3)(4)
tDF CE or OE to Output Float 0 25 0 30 0 40 0 50 ns
tOH Output Hold from OE, CE or 0 0 0 0 ns
Address, whichever occurred first

Note: Not recommended for New Designs.

AC Read Waveforms(1)(2)(3)(4)

Notes: 1. CE may be delayed up to tACC - tCE after the address transition without impact on tACC.
2. OE may be delayed up to tCE - tOE after the falling edge of CE without impact on tCE or by tACC - tOE after an address change
without impact on tACC.
3. tDF is specified from OE or CE whichever occurs first (CL = 5 pF).
4. This parameter is characterized and is not 100% tested.

6 AT29C040A
0333I–FLASH–05/02
 AT29C040A

Input Test Waveforms and Measurement Level

tR, t F < 5 ns

Output Test Load

Pin Capacitance
f = 1 MHz, T = 25°C(1)
Symbol Typ Max Units Conditions
CIN 4 6 pF VIN = 0V
COUT 8 12 pF VOUT = 0V
Note: 1. This parameter is characterized and is not 100% tested.

7
0333I–FLASH–05/02
AC Byte Load Characteristics
Symbol Parameter Min Max Units
tAS, tOES Address, OE Setup Time 10 ns
tAH Address Hold Time 50 ns
tCS Chip Select Setup Time 0 ns
tCH Chip Select Hold Time 0 ns
tWP Write Pulse Width (WE or CE) 90 ns
tDS Data Setup Time 50 ns
tDH, tOEH Data, OE Hold Time 10 ns
tWPH Write Pulse Width High 100 ns

AC Byte Load Waveforms(1)

WE Controlled

CE Controlled

Note: 1. A complete sector (256 bytes) should be loaded using the waveforms shown in these byte load waveform diagrams.

8 AT29C040A
0333I–FLASH–05/02
 AT29C040A

Program Cycle Characteristics

Symbol Parameter Min Max Units
tWC Write Cycle Time 10 ms
tAS Address Setup Time 10 ns
tAH Address Hold Time 50 ns
tDS Data Setup Time 50 ns
tDH Data Hold Time 10 ns
tWP Write Pulse Width 90 ns
tBLC Byte Load Cycle Time 150 µs
tWPH Write Pulse Width High 100 ns

Program Cycle Waveforms(1)(2)(3)

Notes: 1. A8 through A18 must specify the sector address during each high to low transition of WE (or CE).
2. OE must be high only when WE and CE are both low.
3. All bytes that are not loaded within the sector being programmed will be indeterminate.

9
0333I–FLASH–05/02
Software Data Protection Software Data Protection
Enable Algorithm(1) Disable Algorithm(1)
LOAD DATA AA LOAD DATA AA
TO TO
ADDRESS 5555 ADDRESS 5555

LOAD DATA 55 LOAD DATA 55

TO TO
ADDRESS 2AAA ADDRESS 2AAA

LOAD DATA A0 LOAD DATA 80

TO TO
ADDRESS 5555 WRITES ENABLED ADDRESS 5555

LOAD DATA LOAD DATA AA

TO ENTER DATA TO
PAGE (256 BYTES)(4) PROTECT STATE(2) ADDRESS 5555

LOAD DATA 55
TO
ADDRESS 2AAA

LOAD DATA 20
Notes: 1. Data Format: I/O7 - I/O0 (Hex); TO
Address Format: A14 - A0 (Hex). ADDRESS 5555 EXIT DATA
2. Data Protect state will be activated at end of PROTECT STATE(3)
program cycle.
3. Data Protect state will be deactivated at end of LOAD DATA
program period. TO
4. 256 bytes of data MUST BE loaded. PAGE (256 BYTES)(4)

Software Protected Program Cycle Waveform(1)(2)(3)

Notes: 1. A8 through A18 must specify the sector address during each high to low transition of WE (or CE) after the software code
has been entered.
2. OE must be high when WE and CE are both low.
3. All bytes that are not loaded within the sector being programmed will be indeterminate.

10 AT29C040A
0333I–FLASH–05/02
 AT29C040A

Data Polling Characteristics(1)

Symbol Parameter Min Typ Max Units
tDH Data Hold Time 10 ns
tOEH OE Hold Time 10 ns
(2)
tOE OE to Output Delay ns
tWR Write Recovery Time 0 ns
Notes: 1. These parameters are characterized and not 100% tested.
2. See tOE spec in AC Read Characteristics.

Data Polling Waveforms

Toggle Bit Characteristics(1)

Symbol Parameter Min Typ Max Units
tDH Data Hold Time 10 ns
tOEH OE Hold Time 10 ns
(2)
tOE OE to Output Delay ns
tOEHP OE High Pulse 150 ns
tWR Write Recovery Time 0 ns
Notes: 1. These parameters are characterized and not 100% tested.
2. See tOE spec in AC Read Characteristics.

Toggle Bit Waveforms(1)(2)(3)

Notes: 1. Toggling either OE or CE or both OE and CE will operate toggle bit. The tOEHP specification must be met by the toggling
input(s).
2. Beginning and ending state of I/O6 will vary.
3. Any address location may be used but the address should not vary.

11
0333I–FLASH–05/02
Software Product Identification Entry(1) Boot Block Lockout
LOAD DATA AA Feature Enable Algorithm(1)
TO
ADDRESS 5555 LOAD DATA AA
TO
ADDRESS 5555

LOAD DATA 55
TO
ADDRESS 2AAA LOAD DATA 55
TO
ADDRESS 2AAA

LOAD DATA 90
TO
ADDRESS 5555 LOAD DATA 80
TO
ADDRESS 5555

PAUSE 10 mS ENTER PRODUCT

IDENTIFICATION LOAD DATA AA
MODE(2)(3)(5) TO
ADDRESS 5555

Software Product Identification Exit(1)

LOAD DATA 55
LOAD DATA AA TO
TO ADDRESS 2AAA
ADDRESS 5555

LOAD DATA 40
LOAD DATA 55 TO
TO ADDRESS 5555
ADDRESS 2AAA

LOAD DATA 00 LOAD DATA FF

LOAD DATA F0 TO TO
TO ADDRESS 00000H(2) ADDRESS 7FFFFH(3)
ADDRESS 5555

PAUSE 10 mS PAUSE 10 mS
PAUSE 10 mS EXIT PRODUCT
IDENTIFICATION
MODE(4) Notes: 1. Data Format: I/O7 - I/O0 (Hex);
Address Format: A14 - A0 (Hex).
Notes: 1. Data Format: I/O7 - I/O0 (Hex);
Address Format: A14 - A0 (Hex). 2. Lockout feature set on lower address boot block.
2. A1 - A18 = VIL. 3. Lockout feature set on higher address boot block.
Manufacturer Code is read for A0 = VIL;
Device Code is read for A0 = VIH.
3. The device does not remain in identification mode if
powered down.
4. The device returns to standard operation mode.
5. Manufacturer Code is 1F. The Device Code is A4.

12 AT29C040A
0333I–FLASH–05/02
 AT29C040A

Ordering Information
tACC ICC (mA)
(ns) Active Standby Ordering Code Package Operation Range
90 40 0.1 AT29C040A-90JC 32J Commercial
AT29C040A-90PC 32P6 (0° to 70°C)
AT29C040A-90TC 32T
40 0.3 AT29C040A-90JI 32J Industrial
AT29C040A-90PI 32P6 (-40° to 85°C)
AT29C040A-90TI 32T
120 40 0.1 AT29C040A-12JC 32J Commercial
AT29C040A-12PC 32P6 (0° to 70°C)
AT29C040A-12TC 32T
40 0.3 AT29C040A-12JI 32J Industrial
AT29C040A-12PI 32P6 (-40° to 85°C)
AT29C040A-12TI 32T
150 40 0.1 AT29C040A-15JC 32J Commercial
AT29C040A-15PC 32P6 (0° to 70°C)
AT29C040A-15TC 32T
40 0.3 AT29C040A-15JI 32J Industrial
AT29C040A-15PI 32P6 (-40° to 85°C)
AT29C040A-15TI 32T
200 40 0.1 AT29C040A-20JC 32J Commercial
AT29C040A-20PC 32P6 (0° to 70°C)
AT29C040A-20TC 32T
40 0.3 AT29C040A-20JI 32J Industrial
AT29C040A-20PI 32P6 (-40° to 85°C)
AT29C040A-20TI 32T

Note: Not recommended for New Designs.

Package Type
32J 32-lead, Plastic J-leaded Chip Carrier (PLCC)
32P6 32-lead, 0.600" Wide, Plastic Dual Inline Package (PDIP)
32T 32-lead, Thin Small Outline Package (TSOP)

13
0333I–FLASH–05/02
Packaging Information

32J – PLCC

PIN NO. 1 1.14(0.045) X 45˚

1.14(0.045) X 45˚
IDENTIFIER 0.318(0.0125)
0.191(0.0075)

E1 E B1 E2
B

e
A2
D1
A1
D
A

0.51(0.020)MAX
45˚ MAX (3X) COMMON DIMENSIONS
(Unit of Measure = mm)

SYMBOL MIN NOM MAX NOTE

D2 A 3.175 – 3.556
A1 1.524 – 2.413
A2 0.381 – –
D 12.319 – 12.573
D1 11.354 – 11.506 Note 2
D2 9.906 – 10.922
Notes: 1. This package conforms to JEDEC reference MS-016, Variation AE. E 14.859 – 15.113
2. Dimensions D1 and E1 do not include mold protrusion.
Allowable protrusion is .010"(0.254 mm) per side. Dimension D1 E1 13.894 – 14.046 Note 2
and E1 include mold mismatch and are measured at the extreme E2 12.471 – 13.487
material condition at the upper or lower parting line.
3. Lead coplanarity is 0.004" (0.102 mm) maximum. B 0.660 – 0.813
B1 0.330 – 0.533
e 1.270 TYP
10/04/01

TITLE DRAWING NO. REV.

2325 Orchard Parkway
32J, 32-lead, Plastic J-leaded Chip Carrier (PLCC) 32J B
R San Jose, CA 95131

14 AT29C040A
0333I–FLASH–05/02
 AT29C040A

32P6 – PDIP

D
PIN
1

E1

SEATING PLANE

A1
L
B
B1
e

COMMON DIMENSIONS
0º ~ 15º REF (Unit of Measure = mm)
C
SYMBOL MIN NOM MAX NOTE

eB A – – 4.826
A1 0.381 – –
D 41.783 – 42.291 Note 1
E 15.240 – 15.875
E1 13.462 – 13.970 Note 1
B 0.356 – 0.559

Note: 1. Dimensions D and E1 do not include mold Flash or Protrusion. B1 1.041 – 1.651
Mold Flash or Protrusion shall not exceed 0.25 mm (0.010"). L 3.048 – 3.556
C 0.203 – 0.381
eB 15.494 – 17.526
e 2.540 TYP

09/28/01
TITLE DRAWING NO. REV.
2325 Orchard Parkway
32P6, 32-lead (0.600"/15.24 mm Wide) Plastic Dual 32P6 B
R San Jose, CA 95131 Inline Package (PDIP)

15
0333I–FLASH–05/02
32T – TSOP Type 1

PIN 1
0º ~ 8º
c

Pin 1 Identifier

D1 D

e b L1

E A2 A SEATING PLANE GAGE PLANE

COMMON DIMENSIONS
A1 (Unit of Measure = mm)

SYMBOL MIN NOM MAX NOTE

A – – 1.20
A1 0.05 – 0.15
A2 0.95 1.00 1.05
Notes: 1. This package conforms to JEDEC reference MO-142, Variation BD. D 19.80 20.00 20.20
2. Dimensions D1 and E do not include mold protrusion. Allowable
protrusion on E is 0.15 mm per side and on D1 is 0.25 mm per side. D1 18.30 18.40 18.50 Note 2
3. Lead coplanarity is 0.10 mm maximum. E 7.90 8.00 8.10 Note 2
L 0.50 0.60 0.70
L1 0.25 BASIC
b 0.17 0.22 0.27
c 0.10 – 0.21
e 0.50 BASIC

10/18/01
TITLE DRAWING NO. REV.
2325 Orchard Parkway
32T, 32-lead (8 x 20 mm Package) Plastic Thin Small Outline 32T B
R San Jose, CA 95131 Package, Type I (TSOP)

16 AT29C040A
0333I–FLASH–05/02
 Atmel Headquarters Atmel Operations
Corporate Headquarters Memory RF/Automotive
2325 Orchard Parkway 2325 Orchard Parkway Theresienstrasse 2
San Jose, CA 95131 San Jose, CA 95131 Postfach 3535
TEL 1(408) 441-0311 TEL 1(408) 441-0311 74025 Heilbronn, Germany
FAX 1(408) 487-2600 FAX 1(408) 436-4314 TEL (49) 71-31-67-0
FAX (49) 71-31-67-2340
Europe Microcontrollers
Atmel Sarl 2325 Orchard Parkway 1150 East Cheyenne Mtn. Blvd.
Route des Arsenaux 41 San Jose, CA 95131 Colorado Springs, CO 80906
Case Postale 80 TEL 1(408) 441-0311 TEL 1(719) 576-3300
CH-1705 Fribourg FAX 1(408) 436-4314 FAX 1(719) 540-1759
Switzerland
TEL (41) 26-426-5555 La Chantrerie Biometrics/Imaging/Hi-Rel MPU/
FAX (41) 26-426-5500 BP 70602 High Speed Converters/RF Datacom
44306 Nantes Cedex 3, France Avenue de Rochepleine
Asia TEL (33) 2-40-18-18-18 BP 123
Room 1219 FAX (33) 2-40-18-19-60 38521 Saint-Egreve Cedex, France
Chinachem Golden Plaza TEL (33) 4-76-58-30-00
77 Mody Road Tsimshatsui ASIC/ASSP/Smart Cards FAX (33) 4-76-58-34-80
East Kowloon Zone Industrielle
Hong Kong 13106 Rousset Cedex, France
TEL (852) 2721-9778 TEL (33) 4-42-53-60-00
FAX (852) 2722-1369 FAX (33) 4-42-53-60-01

Japan 1150 East Cheyenne Mtn. Blvd.

9F, Tonetsu Shinkawa Bldg. Colorado Springs, CO 80906
1-24-8 Shinkawa TEL 1(719) 576-3300
Chuo-ku, Tokyo 104-0033 FAX 1(719) 540-1759
Japan
TEL (81) 3-3523-3551 Scottish Enterprise Technology Park
FAX (81) 3-3523-7581 Maxwell Building
East Kilbride G75 0QR, Scotland
TEL (44) 1355-803-000
FAX (44) 1355-242-743

e-mail
[email protected]

Web Site
http://www.atmel.com

© Atmel Corporation 2002.

Atmel Corporation makes no warranty for the use of its products, other than those expressly contained in the Company’s standard warranty
which is detailed in Atmel’s Terms and Conditions located on the Company’s web site. The Company assumes no responsibility for any errors
which may appear in this document, reserves the right to change devices or specifications detailed herein at any time without notice, and does
not make any commitment to update the information contained herein. No licenses to patents or other intellectual property of Atmel are granted
by the Company in connection with the sale of Atmel products, expressly or by implication. Atmel’s products are not authorized for use as critical
components in life support devices or systems.

ATMEL ® is the registered trademark of Atmel.

Other terms and product names may be the trademarks of others.

Printed on recycled paper.

0333I–FLASH–05/02 xM