Scribd
Upload
2K views2 pages

SIPO Register VHDL Code With Testbench

The document describes a 4-bit serial-in parallel-out shift register (SIPO) and its testbench. The SIPO entity has inputs for a clock, clear signal, and serial data, and outputs a 4-bit parallel bus. The testbench instantiates the SIPO component and provides a clock signal and stimulus to the serial input. It maps the SIPO ports and monitors the parallel output for different input patterns over time.

Uploaded by

Jyo Jetti
Copyright
© © All Rights Reserved
We take content rights seriously. If you suspect this is your content, claim it here.
Available Formats
Download as DOCX, PDF, TXT or read online on Scribd
2K views2 pages

SIPO Register VHDL Code With Testbench

The document describes a 4-bit serial-in parallel-out shift register (SIPO) and its testbench. The SIPO entity has inputs for a clock, clear signal, and serial data, and outputs a 4-bit parallel bus. The testbench instantiates the SIPO component and provides a clock signal and stimulus to the serial input. It maps the SIPO ports and monitors the parallel output for different input patterns over time.

Uploaded by

Jyo Jetti
Copyright
© © All Rights Reserved
We take content rights seriously. If you suspect this is your content, claim it here.
Available Formats
Download as DOCX, PDF, TXT or read online on Scribd

SIPO Register

library IEEE;
use IEEE.std_logic_1164.all;

entity SIPO is
port(
clk, clear : in std_logic;
SI: in std_logic;
PO: out std_logic_vector(3 downto 0) );
end SIPO;

architecture arch of sipo is

begin

process (clk)
begin
if clear = '1' then
PO <= "0000";
elsif (CLK'event and CLK='1') then
PO(3 downto 1) <= PO(2 downto 0);
PO(0) <= SI;
end if;
end process;
end arch;

SIPO Register Testbench

library IEEE;
use IEEE.std_logic_1164.all;

entity SIPO_TB is
end entity;

architecture behaviour of SIPO_TB is


component SIPO
port(clk,SI,clear : in std_logic;
PO: out std_logic_vector(3 downto 0));
end component;

signal clk:std_logic:='0';
signal SI:std_logic:='0';
signal clear:std_logic:='0';
signal PO:std_logic_vector(3 downto 0);

constant clk_period:time:=10ns;
begin
uut:SIPO port map (
clear=> clear,
clk => clk,
SI => SI,
PO => PO);

Clock : process
begin
clk <= '0';
wait for clk_period/2;
clk <= '1';
wait for clk_period/2;
end process;

stim_proc:process
begin
clear <= '1';wait for 10 ns;
clear <= '0';

SI<='0'; wait for 50 ns;


SI<='1'; wait for 50 ns;
SI<='0'; wait for 50 ns;
SI<='1'; wait for 50 ns;
-- SI<='0'; wait for 50 ns;
-- SI<='1'; wait for 50 ns;
--SI<='0'; wait for 50 ns;
--SI<='1'; wait for 50 ns;

wait;
end process;
END;

You might also like