UNIT III: Basic Processing Unit 08 Hrs
CONTENTS
Some Fundamental Concepts, Register transfers, Performing
an Arithmetic or Logic operation, Fetching a word from
memory, Storing a word in memory, Execution of a complete
Instruction, Branch instructions, Multiple Bus Organization,
Hardwired Control(basic block diagram only), A complete
processor, Basic organization of Micro programmed Control
Unit.
SOME FUNDAMENTAL CONCEPTS
• To execute an instruction, processor has to perform following 3 steps:
1. Fetch contents of memory-location pointed to by PC. Content of
this location is an instruction to be executed. The instructions are
loaded into IR, Symbolically, this operation is written as: IR [[PC]]
2. Increment PC by 4.
PC [PC] +4
3. Carry out the actions specified by instruction (in the IR).
• The first 2 steps are referred to as Fetch Phase.
• Step 3 is referred to as Execution Phase.
The operation specified by an instruction can be carried out by
performing one or more of the following actions:
1.Read the contents of a given memory-location and load them
into a register.
2.Read data from one or more registers.
3.Perform an arithmetic or logic operation and place the result into
a register.
4.Store data from a register into a given memory-location.
• The hardware-components needed to perform these actions are
shown in Figure 5.1.
SINGLE BUS ORGANIZATION
• ALU and all the registers are interconnected via a Single Common Bus (Figure
7.1).
• Data & address lines of the external memory-bus is connected to the internal
processor-bus via MDR & MAR respectively. (MDR Memory Data Register,
MAR Memory Address Register).
• MDR has 2 inputs and 2 outputs. Data may be loaded into MDR either from
memory-bus (external) or from processor-bus (internal).
• MAR's input is connected to internal-bus.
• MAR's output is connected to external-bus.
• Instruction Decoder & Control Unit is responsible for
issuing the control-signals to all the units inside the processor.
implementing the actions specified by the instruction (loaded in the IR).
• Register R0 through R(n-1) are the Processor Registers.
• The programmer can access these registers for general-purpose use.
• Only processor can access 3 registers Y, Z & Temp for temporary storage
during program-execution.
The programmer cannot access these 3 registers.
In ALU,
1) “A” input gets the operand from the output of the multiplexer (MUX).
2) “B” input gets the operand directly from the processor-bus.
• There are 2 options provided for “A” input of the ALU.
MUX selects either
• MUX is used to select one of the 2 inputs.
• MUX selects either output of Y or constant-value 4( which is used
to increment PC content).
• An instruction is executed by performing one or more of the following
operations:
1) Transfer a word of data from one register to another or to the ALU.
2) Perform arithmetic or a logic operation and store the result in a register.
3) Fetch the contents of a given memory-location and load them into a
register.
4) Store a word of data from a register into a given memory-location.
• Disadvantage: Only one data-word can be transferred over the bus in a
clock cycle.
Solution: Provide multiple internal-paths. Multiple paths allow several
data-transfers to take place in parallel
REGISTER TRANSFERS
• Instruction execution involves a sequence of steps in which data are transferred from one
register to another.
• For each register, two control-signals are used: Riin & Riout. These are called Gating Signals.
Riin = 1 data on bus is loaded into Ri.
Riout=1 content of Ri is placed on bus.
Riout=0, bus can be used for transferring data from other registers.
For example, Move R1, R4; This transfers the contents of register R1 to register R4. This can be
accomplished as follows:
1. Enable the output of registers R1 by setting R1out to 1 (Figure ).
This places the contents of R1 on processor-bus.
2. Enable the input of register R4 by setting R4in to 1.
This loads data from processor-bus into register R4.
• All operations and data transfers within the processor take place within time-periods defined
by the processor-clock.
• The control-signals that govern a particular transfer are asserted at the start of the clock cycle.
Register Transfers
PERFORMING AN ARITHMETIC OR LOGIC OPERATION
• The ALU performs arithmetic operations on the 2 operands applied to its A and B inputs.
• One of the operands is output of MUX and, the other operand is obtained directly from
processor-bus.
• The result (produced by the ALU) is stored temporarily in register Z.
• The sequence of operations for [R3] [R1]+[R2] is as follows:
1. R1out, Yin
2. R2out, Select Y, Add, Zin
3. Zout, R3in
.
Instruction execution proceeds as follows:
Step 1 Contents from register R1 are loaded into register Y.
Step 2 Contents from Y and from register R2 are applied to the A and B
inputs of ALU; Addition is performed & Result is stored in the Z register.
Step 3 --> The contents of Z register is stored in the R3 register.
• The signals are activated for the duration of the clock cycle corresponding to
that step. All other signals are inactive
FETCHING A WORD FROM MEMORY
• To fetch instruction/data from memory, processor transfers required address to MAR.
At the same time, processor issues Read signal on control-lines of memory-bus.
• When requested-data are received from memory, they are stored in MDR. From MDR, they are transferred to other
registers.
• The response time of each memory access varies (based on cache miss, memory-mapped I/O). To accommodate this, MFC
is used. (MFC Memory Function Completed).
• MFC is a signal sent from addressed-device to the processor. MFC informs the processor that the requested
operation has been completed by addressed-device.
•
Consider the instruction Move (R1),R2. The sequence of steps is (Figure 7.5):
1. R1out, MARin, Read ;desired address is loaded into MAR & Read command
is issued.
2. MDRinE, WMFC ;load MDR from memory-bus & Wait for MFC response
from memory.
3. MDRout, R2in ;load R2 from MDR.
where WMFC=control-signal that causes processor's control.
circuitry to wait for arrival of MFC signal.
