MATEC Web of Conferences 28, 05002 (2015)

DOI: 10.1051/matecconf/20152805002
© Owned by the authors, published by EDP Sciences, 2015

DC Bus Control of Back-to-Back Connected Two-Level PWM Rectifier-

Five-Level NPC Voltage Source Inverter to Torque Ripple Reduction in
Induction Motor

Thameur Abdelkrim, Karima Benamrane, Badreddine Bezza

Unité de Recherche Appliquée en Energies Renouvelables, URAER,

Centre de Développement des Energies Renouvelables, CDER,

47133, Ghardaïa, Algeria

Abstract. This paper proposes a regulation method of back-to-back connected two-level PWM rectifier-five-level
Voltage Source Inverter (VSI) in order to reduce the torque ripple in induction motor. First part is dedicated to the
presentation of the feedback control of two-level PWM rectifier. In the second part, five-level Neutral Point Clamped
(NPC) voltage source inverter balancing DC bus algorithm is presented. A theoretical analysis with a complete
simulation of the system is presented to prove the excellent performance of the proposed technique.

1 Introduction
The effects of torque ripple are particularly undesirable in 2 Feedback control of two-level rectifier
some demanding motion control and machine tool
In this part, one proposes to enslave the output DC
applications. They lead to speed oscillations which cause
voltage of two-level PWM current rectifier using a PI-
deterioration in the performance. In addition, the torque
based feedback control. The synoptic diagram of two-
ripple may excite resonances in the mechanical portion of
level PWM current rectifier control is shown in Fig. 2.
the drive system, produce acoustic noise, and, in machine
The transfer functions GI(S) and GV(S) are expressed as
tool applications, leave visible patterns in high-precision
follows:
machined surfaces [1].
(1/R r )
This paper investigates the use of a back-to-back G I (S) = (1)
connection of two-level PWM rectifier-five-level Voltage 1 + (L r /R r ) S
Source Inverter (Fig. 1). This connection allow balancing 1
G V (S) = (2)
of the DC link capacitor voltages under a full range of CS
operating conditions [2] whereas, only a limited operating The modeling of this loop is based on the
range is possible if a passive rectifier (diode bridge) is instantaneous power conservation principle with no loss
employed [3]. Additional advantages brought by the hypothesis. This loop imposes the root mean square (rms)
back-to-back connection have been shown to include: the value of network current.
ability to draw almost sinusoidal currents from the supply, Input and output powers are:
the input power factor can be controlled and the back-to-
back topology automatically regenerates power back to ⎧ 3
L di 2
⎪ Pin = ∑ (Vsi i reci0 − R r i 2reci0 − r reci0 ) (3)
the supply when the operating conditions dictate [4]. ⎨ i =1 2 dt
Alternatively, a passive rectifier draws a pulsed current ⎪⎩Pout = U cm (i c + i load )
from the supply and does not allow a regenerative current Different quantities iload, ic (Fig. 2) are defined as
to return to the supply. follows:
In this paper, first part is dedicated to the presentation
of three phases two-level PWM current rectifier ⎧ 2 i d2 + i d1 - 2 i d4 - i d3
regulation loop. After that the DC bus voltages balancing ⎪ i load = 4 (4)
using the redundant vectors of five-level NPC inverter is ⎪
⎨ i c = I recm − i load
explained. At the end the simulation results demonstrate ⎪U = U + U + U + U
efficacy of this of back-to-back converters DC bus ⎪ cm c1 c2 c3 c4
⎩
control.

a
Corresponding author: [email protected]

This is an Open Access article distributed under the terms of the Creative Commons Attribution License 4.0, which permits unrestricted use, distribution,
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Figure 1. Two-Level PWM Rectifier-Five-Level NPC VSI Back-to-Back - Induction Motor

Using of the power conservation principle and

neglecting of joules loss in the resistor Rr, and To simplify into the space vector diagram of a three-
considering a sinusoidal supply network current in phase level inverter, two steps have to be taken.
with corresponding voltage Vsi, it can be written: Firstly, from the location of a given reference voltage,
3 Vsi i reci0 = U cm (i c + i load ) one hexagon has to be selected among the six hexagons.
(5) There exist some regions that are overlapped by two
adjacent hexagons. These regions will be equally divided
between the two hexagons as shown in Fig. 4. Each
hexagon is identified by a number S defined in equation
(6).
⎧1 if − π 6 < θ < π 6
⎪2 if
⎪ π 6 <θ <π 2 (6)
⎪⎪3 if π 2 < θ < 5π 6
s=⎨
⎪4 if 5π 6 < θ < 7π 6
⎪5 if 7π 6 < θ < 3π 2
⎪
⎪⎩6 if 3π 2 < θ < 11π 6

Figure 2. Synoptic diagram of two-level PWM current rectifier

control

3 Simplified SVPWM of five-level NPC

VSI
The space vector diagram of a five-level inverter can
be considered to be composed of six hexagons that are
the space vector diagrams of the three-level inverters.
Each of these six hexagons, constituting the space vector Figure 4. Division of overlapped regions
diagram of a three level inverter, centers on the six
apexes of the medium hexagon as shown in Fig. 3. Secondly, we translate the origin of the reference
voltage vector towards the center of the selected hexagon
as indicated in Fig. 5. This translation is done by
subtracting the center vector of selected hexagon from the
original reference vector. Tab. 1 gives the components d
and q of the reference voltage V3* after translation, for all
the six hexagons. The index (5) or (3) above the
components indicate five or three-level cases respectively.

Figure 3. Simplification of a five-level space vector diagram

into two-level space vector diagram
a
Corresponding author: [email protected] 05002-p.2
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are synthesized by more than one switching state. In Fig.

7 and Tab. 3, we can find 24 positions with no
redundancy (V37 to V60), 18 positions with two
redundancies (V1 to V18), 12 positions with three
redundancies (V19 to V30), 6 positions with four
redundancies (V30 to V36) and 1 position with five
redundancies (V61).
To know the impact of each vector on capacitors
voltages, four steps must be followed:
First one consists in definition of equations
Figure 5. Translation of five-level reference voltage vector representing capacitors currents (ic1, ic2, ic3 and ic4) as a
function of load currents (i1, i2 and i3) (Fig. 1) for each
Table 1. Correction of five-level reference voltage vector vector with redundant states.
s v d3* v q3* Table 3. Redundant vectors of a five-level inverter
1 v d5* − 1 / 2 vq5*
VectRedundanciesVectRedundanciesVectRedundancies
2 v d5* − 1 / 4 vq5* − 3 / 4 a P2N1N1 a P2OO a P2P1P1
V1
3 v d5* + 1 / 4 b P1N2N2 V19 b P1N1N1 b P1OO
vq5* − 3 / 4 V31
a P2ON1 c ON2N2 c ON1N1
4 V2
v d5* + 1 / 2 vq5* b P1N1N2 a P2P1O d N1N2N2
5 a P2P1N1 V20 b P1ON1 a P2P2P1
v d5* + 1 / 4 vq5* + 3 / 4 V3
b P1ON2 c ON1N2 b P1P1O
V32
6 v d5* − 1 / 4 vq5* + 3 / 4 a P2P2N1 a P2P2O c OON1
V4
b P1P1N2 V21 b P1P1N1 d N1N1N2
a P1P2N1 c OON2 a P1P2P1
To simplify into the space vector diagram of a two V5
b OP1N2 a P1P2O b OP1O
level inverter, we have to take the two steps mentioned V33
a OP2N1 V22 b OP1N1 c N1ON1
above. Fig. 6 shows the translation of three-level V6
b N1P1N2 c N1ON2 d N2N1N2
reference voltage vector. The correction of its reference a N1P2N1 a OP2O a P1P2P2
voltage vector is presented in Tab. 2. V7
b N2P1N2 V23 b N1P1N1 b OP1P1
V34
a N1P2O c N2ON2 c N1OO
Table 2. Correction of three-level reference voltage vector V8
b N2P1N1 a OP2P1 d N2N1N1
s vd2* vq2* a N1P2P1 V24 b N1P1O a P1P1P2
V9
b N2P1O c N2ON1 b OOP1
V35
1 v d3* − 1 / 4 v q3* a N1P2P2 a OP2P2 c N1N1O
V10
b N2P1P1 V25 b N1P1P1 d N2N2N1
2 v d3* − 1 / 8 v q3* − 3 / 8
a N1P1P2 c N2OO a P2P1P2
V11
3 v d3* + 1 / 8 v q3* − 3 / 8 b N2OP1 a OP1P2 b P1OP1
V36
a N1OP2 V26 b N1OP1 c ON1O
4 v d3* + 1 / 4 v q3* V12
b N2N1P1 c N2N1O d N1N2N1
5 v d3* + 1 / 8 v q3* + 3 / 8 a N1N1P2 a OOP2
V13
b N2N2P1 V27 b N1N1P1
6 v d3* − 1 / 8 v q3* + 3 / 8 a ON1P2 c N2N2O
V14
b N1N2P1 a P1OP2
a P1N1P2 V28 b ON1P1
V15
b ON2P1 c N1N2O
a P2N1P2 a P2OP2
V16
b P1N2P1 V29 b P1N1P1
a P2N1P1 c ON2O
V17
b P1N2O a P2OP1
a P2N1O V30 b P1N1O
V18
b P1N2N1 c ON2N1

⎧4 ic1 = −(3 F17 + 2 ( F11b + F10b ) + F18 ) i1 − ( 3F27 + 2 ( F21b + F20b ) + F28 ) i2
⎪ b b
⎪− ( 3 F37 + 2 ( F31 + F30 ) + F38 ) i3 (7)
⎪4 i = ( F − F − 2 ( F b + F b )) i + ( F − F − 2 ( F b + F b )) i
Figure 6. Translation of three-level reference voltage vector ⎪ c2 17 18 11 10 1 27 28 21 20 2

⎪⎪+ ( F37 − F38 − 2 ( F31b + F30b )) i3

⎨ b b b b
⎪4 ic 3 = ( F17 + 2 ( F11 + F10 ) + 3 F18 ) i1 + ( F27 + 2 ( F21 + F20 ) + 3 F28 ) i2
4 Five-level NPC VSI balancing DC bus ⎪+ ( F + 2 ( F b + F b ) + 3 F ) i
⎪ 37 31 30 38 3

In this part, one uses the redundant vectors of five-level ⎪4 ic 4 = ( F17 − F18 + 2 ( F11b + F10b )) i1 + ( F27 − F28 + 2 ( F21b + F20b )) i2
⎪
NPC VSI to balance DC bus voltages [5]. Since each leg b b
⎩⎪+ ( F37 − F38 + 2 ( F31 + F30 )) i3
has five possible switching states, five-level inverter has
53 = 125 states. Some positions of output voltage vector

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To reduce the size of control algorithm, the second step

consists in constituting vectors groups.

Group 1 : V1, V4, V7, V10, V13, V16

Group 2 : V2, V6, V8, V12, V14, V18
Group 3 : V3, V5, V9, V11, V15, V17
Group 4 : V19, V21, V23, V25, V27, V29
Group 5 : V20, V22, V24, V26, V28, V30
Group 6 : V31, V32, V33, V34, V35, V36

Third step consists in analyzing the influence of different

groups of redundant vectors on capacitors voltages, under
Figure 8. Output voltage of two-level rectifier
different conditions of load currents.
Fourth step consists to choice the redundancies. For
each case of redundancy, the vector which tends to cancel
the unbalance in capacitor voltages will be selected. In
other words, we select the vector which charge the
undercharged capacitors, and discharge the overcharged
ones.

Figure 9. DC bus capacitors voltages of five-level VSI

Figure 7. Space vector diagram of a five-level inverter

5 Simulation results
Figure 10. Induction motor torque
Simulation is divided in three times. In first time
( 0S<t<2S ), the feedback control of the two-level
rectifier is applied but the five-level VSI balancing DC 6 Conclusion
bus algorithm is not used. The present contribution intends to demonstrate that the
One remarks that the output voltage Ucm of two-level unbalance of DC bus of back-to-back connected two-
rectifier is equal to its reference Ucref=1040V (Fig. 8), but level PWM rectifier-five-level NPC VSI, causes a torque
the voltages Uc1, Uc2, Uc3 and Uc4 are unbalanced (Fig. 9). ripple in induction motor.
One observes also that torque ripple of induction motor The proposed feedback control algorithm to the two-
increase progressively (Fig. 10). level rectifier associate to the space vector PWM
In second time (2S<t<7S), the five-level VSI balancing capacitor voltages of five-level NPC inverter
balancing DC bus algorithm is applied. One remarks that algorithm shows a good following of the average output
the voltages Uc1, Uc2, Uc3 and Uc4 are balanced after few voltage of rectifier and the balancing of input voltages of
seconds (Fig. 9), One observes also that torque ripple inverter. Consequently, a torque ripple of induction motor
decrease progressively (Fig. 10). is reduced. The proposed control algorithm opens the
In third time (7S<t<10S), the nominal torque of door to different applications of NPC multilevel
induction motor is applied. One observe that voltages Uc1, converters in high power utilities such as, motor drives,
Uc2, Uc3 and Uc4 are balanced and not disturbed after doubly fed induction generators, active power filters and
application of nominal torque (Fig. 9). power supply networks interconnection.

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