Microprocessors And Microcontrollers - - Unit 11... https://onlinecourses-archive.nptel.ac.in/noc19_...
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Unit 11 - Week 9
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Certification exam Assignment 9
The due date for submitting this assignment has passed.
Course As per our records you have not submitted this Due on 2019-04-03, 23:59 IST.
outline
assignment.
How to access 1) An ARM instruction is 1 point
the portal
a) 8 bits long
Week 0
b) 16 bits long
Week 1 c) 32 bits long
d) 64 bits long
Week 2
No, the answer is incorrect.
Week 3 Score: 0
Accepted Answers:
Week 4
c) 32 bits long
Week 5 2) ALE signal in ARM is 1 point
Week 6 a) Input to the processor
b) Output from the processor
Week 7
c) Bidirectional
Week 8
d) Configurable
Week 9 No, the answer is incorrect.
Score: 0
Lecture 42 :
ARM (Contd.) Accepted Answers:
a) Input to the processor
Lecture 43 :
ARM(Contd.) 3) In ARM, FIQ processing is faster than IRQ since FIQ 1 point
Lecture 44 :
ARM (Contd.) a) Saves one jump instruction and uses duplicate set of registers
Lecture 45 : b) Saves one jump instruction and clock speed doubles
ARM (Contd.)
c) Uses duplicate set of registers and spare ALU
Lecture 46 :
d) Saves one jump instruction and uses a spare ALU
ARM (Contd.)
No, the NPTEL
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Week 9:
Lecture Score: 0
A project of In association with
Material Accepted Answers:
Quiz : a) Saves one jump instruction and uses duplicate set of registers
Assignment 9
4) Suppose the contents of registersFunded
R1, R2,
byR3 and R4 in an ARM processor are 1, 2, 3 and 1 point
Feedback for 4 respectively. Following two instructions are executed in sequence.
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Microprocessors And Microcontrollers - - Unit 11... https://onlinecourses-archive.nptel.ac.in/noc19_...
Week 9 Powered by STMFD SP!, {R1, R3, R4, R2}
LDMFD SP!, {R4, R1, R3, R2}
Week 10
The contents of the registers R1, R2, R3 and R4 will be
Week 11
a) 1, 3, 4, 2
Week 12 b) 3, 1, 2, 4
c) 1, 2, 3, 4
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VIDEOS d) 4, 3, 2, 1
No, the answer is incorrect.
Solution
Score: 0
Accepted Answers:
c) 1, 2, 3, 4
5) Which instruction set in ARM has higher code density? 1 point
a) ARM
b) THUMB
c) Same for ARM and THUMB
d) Cannot be predicted
No, the answer is incorrect.
Score: 0
Accepted Answers:
b) THUMB
6) In multiplication of a positive number by a negative number in ARM processor, which one 1 point
should be placed in source register to achieve higher speed?
a) Positive number
b) Negative number
c) Either of them
d) Not possible to predict
No, the answer is incorrect.
Score: 0
Accepted Answers:
a) Positive number
7) In ARM, conditional execution is supported in 1 point
a) Both ARM and THUMB mode
b) Only ARM mode
c) Only THUMB mode
d) A programmable manner
No, the answer is incorrect.
Score: 0
Accepted Answers:
b) Only ARM mode
8) Which register in ARM holds return address in case of procedure calls? 1 point
a) R12
b) R13
c) R14
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Microprocessors And Microcontrollers - - Unit 11... https://onlinecourses-archive.nptel.ac.in/noc19_...
d) R15
No, the answer is incorrect.
Score: 0
Accepted Answers:
c) R14
9) An ARM processor writes the 32-bit number 22292F3FH into memory and then reads a 1 point
byte from the same address. The value read in big-endian convention will be
a) 22H
b) 29H
c) 2FH
d) 3FH
No, the answer is incorrect.
Score: 0
Accepted Answers:
a) 22H
10)Number of software interrupts in ARM processor is 1 point
a) 1
b) 24
No, the answer is incorrect.
Score: 0
Accepted Answers:
11)Which Exception in ARM has the highest address in ARM vector table? 1 point
a) RESET
b) IRQ
c) FIQ
d) SWI
No, the answer is incorrect.
Score: 0
Accepted Answers:
c) FIQ
12)The instruction set used by an ARM processor on reset is 1 point
a) ARM
b) THUMB
c) Can be either ARM or THUMB
d) None of ARM or THUMB
No, the answer is incorrect.
Score: 0
Accepted Answers:
a) ARM
13)Which of the following instructions corresponds to loading a signed half word in ARM 1 point
architecture?
3 of 4 Wednesday 22 May 2019 02:14 PM
Microprocessors And Microcontrollers - - Unit 11... https://onlinecourses-archive.nptel.ac.in/noc19_...
a) LDR
b) LDRS
c) LDRSH
d) LDRH
No, the answer is incorrect.
Score: 0
Accepted Answers:
c) LDRSH
14)ARM10TDMI is a 1 point
a) 3-stage pipeline processor
b) 5-stage pipeline processor
c) 6-stage pipeline processor
d) 8-stage pipeline processor
No, the answer is incorrect.
Score: 0
Accepted Answers:
c) 6-stage pipeline processor
15)Which of the following statements is TRUE for 6-stage pipeline ARM architecture? 1 point
a) Both instruction and data buses are 32-bit wide
b) Instruction bus is 32-bit wide, but data bus is 64-bit wide
c) Instruction bus is 64-bit wide, but data bus is 32-bit wide
d) Both instruction and data buses are 64-bit wide
No, the answer is incorrect.
Score: 0
Accepted Answers:
d) Both instruction and data buses are 64-bit wide
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