Faculty of Engineering
ELECTRICAL AND ELECTRONIC ENGINEERING DEPARTMENT
EENG115/INFE115 Introduction to Logic Design
EENG211/INFE211 Digital Logic Design I
Spring 2009-10
Instructors:
M. K. Uyguroğlu
H. Demirel
Final EXAMINATION
June 08, 2010
Duration : 120 minutes
Number of Problems: 7
Good Luck
STUDENT’S
NUMBER
NAME SOLUTIONS
SURNAME
GROUP NO
Problem Achieved Maximum
1 10
2 10
3 10
4 10
5 20
6 20
7 20
TOTAL 100
Introduction to Logic Design/ Digital Logic Design I - Final Examination
Question 1 (10 points)
A. Converting (153)10 to base 8 yields which of the following results?
(a) 107
(b) 132
(c) 701
(d) 231
(e) 153
B. Converting (0111011.100)2 to base 16 yields which of the following results?
(a) 73.8
(b) 3C.4
(c) 3B.8
(d) 73.4
(e) 3B.4
C. 10100 is the two's complement representation of:
(a) -11
(b) +12
(c) -12
(d) -20
(e) +20
D. Simplification of the Boolean expression AB + ABC + ABCD + ABCDE + ABCDEF
yields which of the following results?
(a) ABCDEF
(b) AB
(c) AB + CD + EF
(d) A+B+C+D+E+F
(e) A + B(C+D(E+F))
E. Given that F = (A + B'+ C)(D + E), which of the following represents the only correct
expression for F'?
(a) F' = A'BC'+ D'+ E'
(b) F' = AB'C + DE
(c) F' = (A'+ B + C')(D'+ E')
(d) F' = A'BC' + D'E'
(e) F' = (A + B'+ C)(D'+ E')
M. K. Uyguroğlu, H. Demirel June 08, 2010
Introduction to Logic Design/ Digital Logic Design I - Final Examination
Question 2 (10 points):
A. Identify the function which generates the K-map shown
(a) F(A,B,C)= Σ(1,3,4,7)
(b) F(A,B,C)= Σ (1,3,5,6)
(c) F(A,B,C)= Σ (3,4,5,6) AB
(d) F(A,B,C)= Π(1,3,4,7) C 00 01 11 10
(e) F(A,B,C)= Π (1,3,5,6)
0 0 0 1 0
1 1 1 0 1
B. Identify the most simple expression from the K-map shown.
(a) F(A,B,C,D)=B'C + AD + CD
(b) F(A,B,C,D)=BC' + BCD' + AC'D'
(c) F(A,B,C,D)=BC' + BCD' + AB'C'D' AB
(d) F(A,B,C,D)=AD + BCD' + CD CD 00 01 11 10
(e) F(A,B,C,D)=BC' + BD' +AC'D'
00 1 1 1
01 1 1
11
10 1 1
M. K. Uyguroğlu, H. Demirel June 08, 2010
Introduction to Logic Design/ Digital Logic Design I - Final Examination
C. Identify the most simple Product of Sums (POS) expression which generates the K-map
shown.
(a) F(A,B,C)=(A+C')(A+B+C) AB
(b) F(A,B,C)=(A+B)(A+C')(B+C') C 00 01 11 10
(c) F(A,B,C)=(A'+B')(A'+C)(B'+C)
(d) F(A,B,C)=(A'+C)(A'+B'+C') 0 1 0 0 0
(e) F(A,B,C)=(A+B)(A'+C)(B'+C)
1 1 1 0 1
D. The most reduced expression which can be
obtained from the K-map illustrated is:
(a) F(A,B,C,D)=A + D AB
(b) F(A,B,C,D)=C CD 00 01 11 10
(c) F(A,B,C,D)=A + B
(d) F(A,B,C,D)=A 00 x 1 1
(e) F(A,B,C,D)=A + B + D
01 x x 1 1
11 x x 1 1
10 x 1 1
M. K. Uyguroğlu, H. Demirel June 08, 2010
Introduction to Logic Design/ Digital Logic Design I - Final Examination
Question 3 (10 points):
a) Construct a 16 X 1 multiplexer by using 5 4x 1 multiplexers. Use block diagrams.
M. K. Uyguroğlu, H. Demirel June 08, 2010
Introduction to Logic Design/ Digital Logic Design I - Final Examination
b) Construct a 2-to-4-line decoder by using a 1-to-4 Demultiplexer. Use block diagrams.
Question 4 (10 points):
Implement the following Boolean function with a 4 x 1 multiplexer:
F(A, B, C, D) = Σ (0, 1, 3, 4, 8, 9, 15)
A F
Minterm BCD
0 0 0 0 0 1
1 0 0 0 1 1 I0= C’+D
2 0 0 1 0 0
3 0 0 1 1 1
4 0 1 0 0 1
5 0 1 0 1 0 I1=C’D’
6 0 1 1 0 0
7 0 1 1 1 0
8 1 0 0 0 1
9 1 0 0 1 1 I2= C’
10 1 0 1 0 0
11 1 0 1 1 0
12 1 1 0 0 0
13 1 1 0 1 0
I3= CD
14 1 1 1 0 0
15 1 1 1 1 1
M. K. Uyguroğlu, H. Demirel June 08, 2010
Introduction to Logic Design/ Digital Logic Design I - Final Examination
Question 5 (20 points):
Design a combinational circuit that converts a 4-bit gray code to a 4-bit binary number. Implement
the circuit using exclusive-OR gates.
Gray Code BINARY
W= A
Decimal A B C D W X Y Z
0 0000 0 0 0 0 0 0 0 0
1 0001 0 0 0 1 0 0 0 1
2 0011 0 0 1 1 0 0 1 0
3 0010 0 0 1 0 0 0 1 1
4 0110 0 1 1 0 0 1 0 0
5 0111 0 1 1 1 0 1 0 1
6 0101 0 1 0 1 0 1 1 0
7 0100 0 1 0 0 0 1 1 1
8 1100 1 1 0 0 1 0 0 0
9 1101 1 1 0 1 1 0 0 1
10 1111 1 1 1 1 1 0 1 0
11 1110 1 1 1 0 1 0 1 1
12 1010 1 0 1 0 1 1 0 0
13 1011 1 0 1 1 1 1 0 1
14 1001 1 0 0 1 1 1 1 0
15 1000 1 0 0 0 1 1 1 1
M. K. Uyguroğlu, H. Demirel June 08, 2010
Introduction to Logic Design/ Digital Logic Design I - Final Examination
Question 6 (20 points):
Derive the state table and the state diagram of the sequential circuit shown in Fig. FQ-6.
Z
A
X J Q
Y
I0
2X1
A'
K Q'
MUX
I1
S0
B
J Q
K Q' B'
Figure FQ-6
JA = x
KA= B’x’+Bx
JB= A’
KB=A+x
Y=AB
Z=A’B+x’
Present Input Next Output Flip-flop
State State Input
A B x A B Y Z JA KA JB KB
0 0 0 0 1 0 1 0 1 1 0
0 0 1 1 1 0 0 1 0 1 1
0 1 0 0 1 0 1 0 0 1 0
0 1 1 1 0 0 1 1 1 1 1
1 0 0 0 0 0 1 0 1 0 1
1 0 1 1 0 0 0 1 0 0 1
1 1 0 1 0 1 1 0 0 0 1
1 1 1 0 0 1 0 1 1 0 1
M. K. Uyguroğlu, H. Demirel June 08, 2010
Introduction to Logic Design/ Digital Logic Design I - Final Examination
Question 7 (20 points):
Design the sequential circuit specified by the state diagram of Fig. FQ-7 using T flip-flops.
000
0 1
010
0
001
1 0 1
011 0 100
1 0
0
1 1
0 110
101
0
1
111
Figure FQ-7
Present Input Next Flip-flop TC = x’
State State Inputs
A B C x A B C TA TB TC
0 0 0 0 0 0 1 0 0 1
0 0 0 1 0 1 0 0 1 0
0 0 1 0 0 1 0 0 1 1
0 0 1 1 0 1 1 0 1 0
0 1 0 0 0 1 1 0 0 1
0 1 0 1 1 0 0 1 1 0
0 1 1 0 1 0 0 1 1 1
0 1 1 1 1 0 1 1 1 0
1 0 0 0 1 0 1 0 0 1
1 0 0 1 1 1 0 0 1 0
1 0 1 0 1 1 0 0 1 1
1 0 1 1 1 1 1 0 1 0
1 1 0 0 1 1 1 0 0 1
1 1 0 1 0 0 0 1 1 0
1 1 1 0 0 0 0 1 1 1
1 1 1 1 0 0 1 1 1 0
M. K. Uyguroğlu, H. Demirel June 08, 2010
Introduction to Logic Design/ Digital Logic Design I - Final Examination
M. K. Uyguroğlu, H. Demirel June 08, 2010
