Internally Trimmed

Precision IC Multiplier
Data Sheet AD632
FEATURES FUNCTIONAL BLOCK DIAGRAM
Pretrimmed to ±0.5% maximum 4-quadrant error STABLE +VS
REFERENCE
All inputs (X, Y, and Z) differential, high impedance for AND BIAS –VS
[(X1 − X2)(Y1 − Y2)/10] + Z2 transfer function
TRANSFER FUNCTION
Scale-factor adjustable to provide up to ×10 gain X1
(X1 – X2) (Y1 – Y2)
Low noise design: 90 mV rms, 10 Hz to 10 kHz V-I VO = A
10
– (Z1 – Z2)
X2
TRANSLINEAR
Low cost, monolithic construction MULTIPLIER
ELEMENT
Excellent long-term stability Y1
V-I

APPLICATIONS Y2 A OUT

HIGH GAIN
High quality analog signal processing Z1
0.75 ATTEN
OUTPUT
AMPLIFIER
Z2 V-I
Differential ratio and percentage computations 2.7kΩ

09040-007
Algebraic and trigonometric function synthesis VOS
25kΩ
Accurate voltage controlled oscillators and filters Figure 1.

GENERAL DESCRIPTION
The AD632 is an internally trimmed monolithic four-quadrant rejection. The effectiveness of the variable gain capability is
multiplier/divider. The AD632B has a maximum multiplying enhanced by the inherent low noise of the AD632 at 90 µV rms.
error of ±0.5% without external trims.
PRODUCT HIGHLIGHTS
Excellent supply rejection, low temperature coefficients, and 1. Guaranteed performance over temperature.
long-term stability of the on-chip thin film resistors and buried 2. The AD632A and AD632B are specified for maximum
zener reference preserve accuracy even under adverse conditions. multiplying errors of ±1.0% and ±0.5% of full scale,
The simplicity and flexibility of use provide an attractive alternative respectively, at +25°C and are rated for operation from
approach to the solution of complex control functions. −25°C to +85°C.
The AD632 is pin-for-pin compatible with the industry 3. Maximum multiplying errors of ±2.0% (AD632S) and
standard AD532 but with improved specifications and a fully ±1.0% (AD632T) are guaranteed over the extended
differential high impedance Z input. The AD632 is capable of temperature range of −55°C to +125°C.
providing gains of up to ×10, frequently eliminating the need 4. High reliability.
for separate instrumentation amplifiers to precondition the 5. The AD632S and AD632T series are available with MIL-
inputs. The AD632 can be effectively employed as a variable STD-883 Level B screening.
gain differential input amplifier with high common-mode 6. All devices are available in either the hermetically sealed
TO-100 metal can or ceramic DIP package.

Rev. D Document Feedback

Information furnished by Analog Devices is believed to be accurate and reliable. However, no
responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other
rights of third parties that may result from its use. Specifications subject to change without notice. No One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
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Trademarks and registered trademarks are the property of their respective owners. Technical Support www.analog.com
AD632 Data Sheet

TABLE OF CONTENTS
Features .............................................................................................. 1 Thermal Resistance .......................................................................5
Applications ....................................................................................... 1 Pin Configurations and Function Descriptions ............................6
Functional Block Diagram .............................................................. 1 Typical Performance Characteristics ..............................................7
General Description ......................................................................... 1 Operation As a Multiplier ................................................................8
Product Highlights ........................................................................... 1 Operation As a Divider .....................................................................9
Revision History ............................................................................... 2 Outline Dimensions ....................................................................... 10
Specifications..................................................................................... 3 Ordering Guide .......................................................................... 11
Absolute Maximum Ratings ............................................................ 5

REVISION HISTORY
5/13—Rev. C to Rev. D
Changes to Table 1 ............................................................................. 3
Changes to Ordering Guide ...........................................................11
12/11—Rev. B to Rev. C
Updated Format .................................................................. Universal
Added Figure 1, Renumbered Sequentially ................................... 1
Deleted Chip Dimensions and Pad Layout Section ...................... 5
Changes to Figure 3 and Figure 4 ................................................... 6
Added Table 3 and Table 4 .............................................................. 6
Changes to the Operations as a Divider Section .......................... 9
Updated Outline Dimensions ....................................................... 10
4/10—Rev. A to Rev. B
Changes to Pin Configurations and Product Highlights
Sections .............................................................................................. 1
Changes to Thermal Characteristics Section ................................ 3
Updated Outline Dimensions ......................................................... 6
Changes to Ordering Guide ............................................................ 6

Rev. D | Page 2 of 12
Data Sheet AD632

SPECIFICATIONS
@ +25°C, VS = ±15 V, R ≥ 2 kΩ, unless otherwise noted. Specifications shown in boldface are tested on all production units at final
electrical test. Results from those tests are used to calculate outgoing quality levels.

Table 1.
AD632A AD632B AD632S AD632T
Parameter Min Typ Max Min Typ Max Min Typ Max Min Typ Max Units
MULTIPLIER PERFORMANCE
Transfer Function ( X1 − X 2 ) (Y1 − Y2 ) ( X1 − X 2 ) (Y1 − Y2 ) ( X1 − X 2 ) (Y1 − Y2 ) ( X1 − X 2 ) (Y1 − Y2 )
+ Z2 + Z2 + Z2 + Z2
10 V 10 V 10 V 10 V
Total Error 1 (−10 V ≤ X, Y ≤ +10 ±1.0 ±0.5 ±1.0 ±0.5 %
V)
TA = Min to Max ±1.5 ±1.0 ±2.0 ±1.0 %
Total Error vs. Temperature ±0.022 ±0.015 ±0.02 ±0.01 %/°C
Scale Factor Error
(SF = 10,000 V Nominal) 2 ±0.25 ±0.1 ±0.25 ±0.1 %
Temperature Coefficient of ±0.02 ±0.01 ±0.2 ±0.005 %/°C
Scaling Voltage
Supply Rejection (±15 V ± 1 V) ±0.01 ±0.01 ±0.01 ±0.01 %
Nonlinearity
X (X = 20 V p-p, Y = 10 V) ±0.4 ±0.2 ±0.3 ±0.4 ±0.2 ±0.3 %
Y (Y = 20 V p-p, X = 10 V) ±0.2 ±0.1 ±0.1 ±0.2 ±0.1 ±0.1 %
Feedthrough 3
X (Y Nulled, X = 20 V p-p 50 Hz) ±0.3 ±0.15 ±0.3 ±0.3 ±0.15 ±0.3 %
Y (X Nulled, Y = 20 V p-p 50 Hz) ±0.01 ±0.01 ±0.1 ±0.01 ±0.01 ±0.1 %
Output Offset Voltage ±5 ±30 ±2 ±15 ±5 ±30 ±2 ±15 mV
Output Offset Voltage Drift 200 100 500 300 µV/°C
DYNAMICS
Small Signal BW, (VOUT = 0.1 rms) 1 1 1 1 MHz
1% Amplitude Error 50 50 50 50 kHz
(CLOAD = 1000 pF)
Slew Rate (VOUT 20 p-p) 20 20 20 20 V/µs
Settling Time (to 1%, ΔVOUT = 20 V) 2 2 2 2 µs
NOISE
Noise Spectral Density
SF = 10 V 0.8 0.8 0.8 0.8 µV/√Hz
SF = 3 V 4 0.4 0.4 0.4 0.4 µV/√Hz
Wideband Noise
A = 10 Hz to 5 MHz 1.0 1.0 1.0 1.0 mV/rms
P = 10 Hz to 10 kHz 90 90 90 90 µV/rms
OUTPUT
Output Voltage Swing ±11 ±11 ±11 ±11 V
Output Impedance (f ≤ 1 kHz) 0.1 0.1 0.1 0.1 Ω
Output Short-Circuit Current
(RL = 0, TA = Min to Max) 30 30 30 30 mA
Amplifier Open-Loop Gain 70 70 70 70 dB
(f = 50 Hz)
INPUT AMPLIFIERS (X, Y, and Z) 5
Signal Voltage Range ±10 ±12 ±10 ±12 ±10 ±12 ±10 ±12 V
(Differential or Common-
Mode Operating Diff.)
Offset Voltage X, Y ±5 ±20 ±2 ±10 ±5 ±20 ±2 ±10 mV
Offset Voltage Drift X, Y 100 50 100 150 µV/°C
Offset Voltage Z ±5 ±30 ±2 ±15 ±5 ±30 ±2 ±15 mV
Offset Voltage Drift Z 200 100 500 300 µV/°C
CMRR 60 80 70 90 60 80 70 90 dM
Bias Current 0.8 2.0 0.8 2.0 0.8 2.0 0.8 2.0 µA
Offset Current 0.1 0.1 0.1 0.1 µA
Differential Resistance 10 10 10 10 MΩ
Rev. D | Page 3 of 12
AD632 Data Sheet
AD632A AD632B AD632S AD632T
Parameter Min Typ Max Min Typ Max Min Typ Max Min Typ Max Units
DIVIDER PERFORMANCE
Transfer Function(X1 > X2) (Z 2 − Z 1 ) (Z 2 − Z 1 ) (Z 2 − Z 1 ) (Z 2 − Z 1 )
10V + Y1 10V + Y1 10V + Y1 10V + Y1
( X1 − X 2 ) ( X1 − X 2 ) ( X1 − X 2 ) ( X1 − X 2 )
Total Error1
(X = 10 V, −10 V ≤ Z ≤ +10 V) ±0.75 ±0.35 ±0.75 ±0.35 %
(X = 1 V, −1 V ≤ Z ≤ +1 V) ±2.0 ±1.0 ±2.0 ±1.0 %
(0.1 V ≤ X ≤ 10 V, −10 V ≤ Z ≤ ±2.5 ±1.0 ±2.5 ±1.0 %
10 V)
SQUARER PERFORMANCE
Transfer Function ( X 1 − X 2 )2 ( X 1 − X 2 )2 ( X 1 − X 2 )2 ( X 1 − X 2 )2
+ Z2 + Z2 + Z2 + Z2
10 V 10 V 10 V 10 V
Total Error (−10 V ≤ X ≤ 10 V) ±0.6 ±0.3 ±0.6 ±0.3 %
SQUARE-ROOTER PERFORMANCE
Transfer Function, (Z1 ≤ Z2)
10 V(Z 2 − Z 1 ) + X 2 10 V(Z 2 − Z 1 ) + X 2 10 V(Z 2 − Z 1 ) + X 2 10 V(Z 2 − Z 1 ) + X 2
1
Total Error (1 V ≤ Z ≤ 10 V) ±1.0 ±0.5 ±1.0 ±0.5 %
POWER SUPPLY SPECIFICATIONS
Supply Voltage
Rated Performance ±15 ±15 ±15 ±15 V
Operating ±8 ±18 ±8 ±18 ±8 ±22 ±8 ±22 V
Supply Current
Quiescent 4 6 4 6 4 6 4 6 mA

1
Figures given are percent of full-scale, ±10 V (that is, 0.01% = 1 mV).
2
Can be reduced to 3 V using an external resistor between –VS and SF.
3
Irreducible component due to nonlinearity: excludes effect of offsets.
4
Using an external resistor adjusted to give a value of SF = 3 V.
5
See the functional block diagram (Figure 1) for definition of sections.

Rev. D | Page 4 of 12
Data Sheet AD632

ABSOLUTE MAXIMUM RATINGS

THERMAL RESISTANCE
θJA is specified for the worst-case conditions, that is, a device
soldered in a circuit board for surface-mount packages.

Table 2. Thermal Resistance

Package Type θJA θJC Unit
10-Lead TO-100 150 25 °C/W
14-Lead SBDIP 95 25 °C/W

Rev. D | Page 5 of 12
AD632 Data Sheet

PIN CONFIGURATIONS AND FUNCTION DESCRIPTIONS

VOS
Y2 Z2 (GND) Z1 1 14 +VS
9 8 OUT 2 13 Y1
10
X2
Y1
7 –VS 3 AD632 12 Y2
1
AD632 6
NC 4 TOP VIEW 11 VOS
X1 (Not to Scale)
2
NC 5 10 Z2
+VS 5 NC 6 9 X2
3 4
–VS X1 7 NC

09040-001
8

09040-002
Z1
OUT
(Not to Scale) NC = NO CONNECT

Figure 2. Pin Configuration, H-Package, TO-100 Figure 3. Pin Configuration, D-Package, SBDIP

Table 3. Pin Function Descriptions, 10-Pin TO-100 Table 4. Pin Function Descriptions, 14-Lead SBDIP
Pin No. Mnemonic Description Pin No. Mnemonic Description
1 Y1 Y Multiplicand Noninverting Input. 1 Z1 Summing Node Noninverting Input.
2 +VS Positive Supply Voltage. 2 OUT Product.
3 Z1 Summing Node Noninverting Input. 3 −VS Negative Supply Voltage.
4 OUT Product. 4, 5, 6, 8 NC No Connection. Do not connect to
5 −VS Negative Supply Voltage. this pin.
6 X1 X Multiplicand Noninverting Input. 7 X1 X Multiplicand Noninverting Input.
7 X2 X Multiplicand Inverting Input. 9 X2 X Multiplicand Noninverting Input.
8 Z2 Summing Node Inverting Input. 10 Z2 Summing Node Inverting Input.
9 VOS Offset Voltage Adjustment. 11 VOS Offset Voltage Adjustment.
10 Y2 Y Multiplicand Inverting Input. 12 Y2 Y Multiplicand Inverting Input.
13 Y1 Y Multiplicand Noninverting Input.
14 +VS Positive Supply Voltage.

Rev. D | Page 6 of 12
Data Sheet AD632

TYPICAL PERFORMANCE CHARACTERISTICS

Typical @ 25°C with ±VS = 15 V.
1000

40
Y FEEDTHROUGH
100 VX = 100mV DC
FEEDTHROUGH (mV p-p)

VZ = 10mV rms

)
VO
Vz
X FEEDTHROUGH 20

OUTPUT (dB
VX = 1V DC
10 VZ = 100mV rms

0dB = 1V rms, RL = 2kΩ

0
1
VX = 10V DC
VZ = 1V rms

09040-006
09040-004
0.1 –20
10 100 1k 10k 100k 1M 10M 1k 10k 100k 1M 10M
FREQUENCY (Hz) FREQUENCY (Hz)

Figure 4. AC Feedthrough vs. Frequency Figure 6. Frequency Response vs. Divider Denominator Input Voltage

0dB = 0.1V rms, RL = 2kΩ

0
CL = 1000pF
OUTPUT RESPONSE (dB)

CL = 0pF

–10 CL ≤ 1000pF
CF ≤ 200pF
CL ≤ 1000pF
CF = 0pF

–20
WITH ×10 NORMAL
FEEDBACK CONNECTION
ATTENUATOR
09040-005

–30
10k 100k 1M 10M
FREQUENCY (Hz)

Figure 5. Frequency Response as a Multiplier

Rev. D | Page 7 of 12
AD632 Data Sheet

OPERATION AS A MULTIPLIER
Figure 7 shows the basic connection for multiplication. Note A much lower scaling voltage can be achieved without any reduc-
that the circuit meets all specifications without trimming. tion of input signal range using a feedback attenuator, as shown
in Figure 8. In this example, the scale is such that VOUT = XY, so
X INPUT X1 +VS +15V that the circuit can exhibit a maximum gain of 10. This connection
±10V FS results in a reduction of bandwidth to about 80 kHz without the
±12V PK X2
OUTPUT, ±12V PK
peaking capacitor, CF. In addition, the output offset voltage is
OUT (X – X2) (Y1 – Y2) increased by a factor of 10 making external adjustments necessary
= 1 + Z2
10
VOS Z1 in some applications.
OPTIONAL SUMMING
Z2 INPUT, Z, ±10V PK;
Feedback attenuation also retains the capability for adding a
VOS TERMINAL signal to the output. Signals can be applied to the Z terminal,
Y1 NOT USED
Y INPUT where they are amplified by −10, or to the common ground
±10V FS
±12V PK Y2 –VS –15V connection where they are amplified by −1. Input signals can

09040-008
also be applied to the lower end of the 2.7 kΩ resistor, giving a
Figure 7. Basic Multiplier Connection gain of +9.
When needed, the user can reduce ac feedthrough to a minimum
X1 +VS +15V
(as in a suppressed carrier modulator) by applying an external X INPUT
±10V FS
trim voltage (±30 mV range required) to the X or Y input. Figure 4 ±12V PK X2
shows the typical ac feedthrough with this adjustment mode. OUTPUT, ±12V PK
OUT = (X1 – X2) (Y1 – Y2)
Note that the feedthrough of the Y input is a factor of 10 lower (SCALE = 1)
than that of the X input and is to be used for applications where Z1

null suppression is critical. Z2

The Z2 terminal of the AD632 can be used to sum an additional Y INPUT Y1 VOS
signal into the output. In this mode, the output amplifier behaves ±10V FS
±12V PK Y2 –VS –15V

09040-009
as a voltage follower with a 1 MHz small signal bandwidth and
a 20 V/μs slew rate. Always reference this terminal to the ground
Figure 8. Connections for Scale Factor of Unity
point of the driven system, particularly if this is remote. Like-
wise, reference the differential inputs to their respective signal
common potentials to realize the full accuracy of the AD632.

Rev. D | Page 8 of 12
Data Sheet AD632

OPERATION AS A DIVIDER
Figure 9 shows the connection required for division. Unlike
+
earlier products, the AD632 provides differential operation on X INPUT X1 +VS +15V
(DENOMINATOR)
+10V FS OUTPUT, ±12V PK
both the numerator and the denominator, allowing the ratio of +12V PK X2 10 (Z2 – Z1)
– = + Y1
two floating variables to be generated. Further flexibility results (X1 – X2)
+15V +VS OUT
from access to a high impedance summing input to Y1. As with
2kΩ
all dividers based on the use of a multiplier in a feedback loop, TO VOS Z1 Z INPUT
200kΩ (NUMERATOR)
the bandwidth is proportional to the denominator magnitude, OPTIONAL –15V –VS Z2 ±10V FS, ±12V PK
as shown in Figure 6. SUMMING INPUT
±10V PK
Y1
The accuracy of the AD632 B-model is sufficient to maintain a
1% error over a 10 V to 1 V denominator range. Y2 –VS –15V

09040-010
Figure 9. Basic Divider Connection

Rev. D | Page 9 of 12
AD632 Data Sheet

OUTLINE DIMENSIONS
0.005 (0.13) MIN 0.080 (2.03) MAX

14 8
0.310 (7.87)
1 0.220 (5.59)
7
PIN 1
0.100 (2.54)
BSC 0.320 (8.13)
0.765 (19.43) MAX 0.290 (7.37)
0.200 (5.08) 0.060 (1.52)
MAX 0.015 (0.38)
0.150
(3.81)
0.200 (5.08) MIN
0.125 (3.18) SEATING 0.015 (0.38)
0.070 (1.78) 0.008 (0.20)
PLANE
0.023 (0.58) 0.030 (0.76)
0.014 (0.36)

CONTROLLING DIMENSIONS ARE IN INCHES; MILLIMETER DIMENSIONS

(IN PARENTHESES) ARE ROUNDED-OFF INCH EQUIVALENTS FOR
REFERENCE ONLY AND ARE NOT APPROPRIATE FOR USE IN DESIGN.

Figure 10. 14-Lead Side-Brazed Ceramic Dual In-Line Package [SBDIP]

(D-14)
Dimensions shown in inches and (millimeters)
REFERENCE PLANE

0.500 (12.70)
0.185 (4.70) MIN 0.160 (4.06)
0.165 (4.19) 0.110 (2.79)

6 7
5
0.370 (9.40)
0.335 (8.51)
0.335 (8.51)
0.305 (7.75)

0.021 (0.53) 0.115 8

0.016 (0.40) (2.92) 4 0.045 (1.14)
BSC 9 0.025 (0.65)
3
10 0.034 (0.86)
2 1 0.025 (0.64)
0.230 (5.84)
BASE & SEATING PLANE BSC
0.040 (1.02) MAX 36° BSC

0.050 (1.27) MAX

DIMENSIONS PER JEDEC STANDARDS MO-006-AF

CONTROLLING DIMENSIONS ARE IN INCHES; MILLIMETER DIMENSIONS
022306-A

(IN PARENTHESES) ARE ROUNDED-OFF INCH EQUIVALENTS FOR

REFERENCE ONLY AND ARE NOT APPROPRIATE FOR USE IN DESIGN.

Figure 11. 10-Pin Metal Header Package [TO-100]

(H-10)
Dimensions shown in inches and (millimeters)

Rev. D | Page 10 of 12
Data Sheet AD632
ORDERING GUIDE
Model 1 Temperature Range Package Description Package Option
AD632AD −25°C to +85°C 14-Lead Side-Brazed Ceramic Dual In-Line Package [SBDIP] D-14
AD632ADZ −25°C to +85°C 14-Lead Side-Brazed Ceramic Dual In-Line Package [SBDIP] D-14
AD632AHZ −25°C to +85°C 10-Pin Metal Header Package [TO-100] H-10
AD632BD −25°C to +85°C 14-Lead Side-Brazed Ceramic Dual In-Line Package [SBDIP] D-14
AD632BDZ −25°C to +85°C 14-Lead Side-Brazed Ceramic Dual In-Line Package [SBDIP] D-14
AD632BHZ −25°C to +85°C 10-Pin Metal Header Package [TO-100] H-10
AD632SD −55°C to +125°C 14-Lead Side-Brazed Ceramic Dual In-Line Package [SBDIP] D-14
AD632SH −55°C to +125°C 10-Pin Metal Header Package [TO-100] H-10
AD632SH/883B −55°C to +125°C 10-Pin Metal Header Package [TO-100] H-10
AD632TD −55°C to +125°C 14-Lead Side-Brazed Ceramic Dual In-Line Package [SBDIP] D-14
AD632TD/883B −55°C to +125°C 14-Lead Side-Brazed Ceramic Dual In-Line Package [SBDIP] D-14
AD632TH −55°C to +125°C 10-Pin Metal Header Package [TO-100] H-10
AD632TH/883B −55°C to +125°C 10-Pin Metal Header Package [TO-100] H-10
1
Z = RoHS Compliant Part.

Rev. D | Page 11 of 12
AD632 Data Sheet

NOTES

©1979–2013 Analog Devices, Inc. All rights reserved. Trademarks and

registered trademarks are the property of their respective owners.
D09040-0-5/13(D)

Rev. D | Page 12 of 12