Chapter 7 ■ Number Theory for FPGAs
There are some VHDL-00 reserved words in the Table 7-1. Most of them are not recommended for use
as they are not supported by all tools.
■■Note The following web site descripts each reserved word in detail: [Link]
xilinx10/isehelp/ite_r_vhdl_reserved_words.htm.
7.1.3 Signal, Variable, and Constant
Each VHDL module is combined from multiple data objects that store or display information. For example,
CONSTANT is used to store fixed information and is a data object. There are three types of data object:
signals, variables, and constants. So far, we have seen signals that were used as internal nets (full adder
signals D).
When we create a data object, we need to assign a data value and data type to that object. The data
value will be different when the object type is different. For example, if the data type is a bit object then
the stored value must be either a 0 or a 1. If the data type is a real object then the stored value will be a real
number.
[Link] Signal
Signals in VHDL are like a physical wire. They are used to connect different modules. Signals are declared as
shown in Listings 7-2 and 7-3.
Listing 7-2. Signal Declaration
signal signal_name : type [ := initial value ] ;
Listing 7-3. Signal Declaration Examples
signal Q1 : std_logic ; -- declare Q1 as std_logic data type without initial value
signal counter : natural := 0 ; -- declare counter as natural data type with
initial value = 0
signal Data : std_logic_vector( 7 downto 0 ) ; -- declare Data as std_logic_vector
with 8 bit width
Signals can be updated using a signal assignment statement. Figure 7-3 shows an example for the signal
data type.
128
Chapter 7 ■ Number Theory for FPGAs
Figure 7-3. signal_example VHDL module
In the signal_example, signals s_1, s_2, s_3, and s_4 are declared std_logic. All four of them get
assigned a value which is a logic operation result from lines 20 to 23. In line 24, the output S_out is assigned
the value of s_4.
There is always some delay in the signal assignments. This is different from the variable data type.
[Link] Variable
Variable data objects, like in C, are used to store local process/function information. They are used to hold
temporary data. Variables are declared with the statement shown in Listings 7-4 and 7-5.
Listing 7-4. Signal Declaration
variable variable_name : type [ := initial value ] ;
129
Chapter 7 ■ Number Theory for FPGAs
Listing 7-5. Signal Declaration Examples
variable Q1 : std_logic ; -- declare Q1 as std_logic data type without initial value
variable counter : natural := 0 ; -- declare counter as natural data type with initial
value = 0
variable Data : std_logic_vector( 7 downto 0 ) ; -- declare Data as std_logic_vector
with 8 bit width
In Figure 7-4, variables v_1, v_2, v_3, and v_4 are declared std_logic inside the v_p process. All four of
the variables are only allowed to be used within the process. All four of them get assigned a value which is
the logic operation result from lines 24 to 27. In line 29, the output S_out is assigned the value of v_4.
Figure 7-4. variable_example VHDL module
130
Chapter 7 ■ Number Theory for FPGAs
There are two differences between variables and signals. The first one is that variables are only able to
assign/update values within a process, procedure, or function. Signals can also be assigned a value by direct
assignment (as in Figure 7-3 lines 20-24).
The second example is where the value changes. We will use Listings 7-6 and 7-7 to show the difference.
Listing 7-6. Process Using Signal
architecture SIG of delay_example is
signal activate, result : natural := 0 ;
signal signal_1 : natural := 1 ;
signal signal_2 : natural := 2 ;
signal signal_3 : natural := 3 ;
begin
process( activate )
begin
signal_1 <= signal_2 ;
signal_2 <= signal_1 + signal_3 ;
signal_3 <= signal_2 ;
result <= signal_1 + signal_2 + signal 3;
end process;
end SIG
Listing 7-7. Process Using Variable
architecture VAR of delay_example is
signal activate, result : natural := 0 ;
begin
process( activate )
variable variable_1 : natural := 1 ;
variable variable_2 : natural := 2 ;
variable variable_3 : natural := 3 ;
begin
variable_1 := variable_2 ;
variable_2 := variable_1 + variable_3 ;
variable_3 := variable_2 ;
result <= signal_1 + signal_2 + signal 3;
end process;
end VAR
In Listing 7-8, the signals (signal_1, signal_2, signal_3) are computed at the same time that activate is
triggered. The signals will get updated as the following: signal_1 = 2, signal_2 = 1 + 3 = 4, signal_3 = 2, and
result = 1 + 2 + 3 = 6.
In Listing 7-9, the variables are computed at the time when activate is triggered in sequential order
(from top to bottom). The signals will get updated as the following: variable_1 = 2, variable_2 = 2 + 3 = 5,
variable_3 = 5, and result = 2 + 5 + 5 = 12.
■■Tip For the vast majority of the time use signals in your designs and don't mix signals and variables in the
same process
131
Chapter 7 ■ Number Theory for FPGAs
[Link] Constant
A constant is like variable data object, but the value of it cannot be changed. It can improve readability of the
VHDL code. A constant is declared as in Listing 7-8.
Listing 7-8. Signal Declaration
constant constant_name : type [ := initial value ] ;
Listing 7-9. Signal Declaration Examples
constant PEROID : time := 10 ns ; -- declare PERIOD as time data type with value = 10 nano seconds
constant BUS_WIDTH : natural := 16 ; -- declare BUS_WIDTH as natural data type with value = 16
Constants can be declared at the beginning of architecture and can be used anywhere within the
architecture. If constants are declared within a process, then they can only be used inside the process.
7.1.4 Literal: Word for Word
There are two main types of literal: characters and numbers. The meaning of the literal though depends on
the type of the object. For example, “1” could be the only integer bigger than 0 and smaller than 2, or it could
be the character in ASCII code 31 (HEX). Therefore, words in VHDL need to be paired with a data type.
[Link] Characters
A character is only ONE “character”; it is stored as its ASCII code. To use a character, you need to use single
quotation marks, as shown in Listing 7-10.
Listing 7-10. Characters Examples
'1', 'Z', 'a', 'f', '$'
[Link] String
A string is a group of characters. You need to use double quotation marks when you want to use a string
(Listing 7-11).
Listing 7-11. String Examples
"This is a string",
"This is a ""string"" too."
[Link] Bit String
A bit string can treated as a mutation of a string. A string is used to represent characters and a bit string is
used to represent binary numbers or a sequence of bit values (Listings 7-12 through 7-14). Examples are
show as the following. All of them are showing value 90 and 240 but not the same number of bits for each
type: 90 in the binary bit string only uses 7 bit; Octal use 9 bit; and Hexagonal use 8 bit.
132
