ELECTRONICS AND COMMUNICATION

DEPARTMENT
October 3, 2017
The LNMIIT, JAIPUR
Digital Circuits and Systems (Code: DCS)
Time: 90 Minites Mid Sem Examination Solution Maximum Marks: 30

Section I:

Q1. (a) If the numbers (+992) and (+78) are in signed magnitude format, convert the numbers to signed-10’s complement
form and show that SU M 1 = −SU M 2, where SU M 1 = (+992) − (+78) and SU M 2 = (−992) + (+78).

[1+1+1]

Solution: Number of required digits, in this case, is five since the sum of these two numbers are four digit number
and one digit required for the sign digit. Hence, these numbers can be written as:
+992 → 00992 and +78 → 00078 and then the 10’s complement form as: 99999 − 00992 + 1 = 99008 and
99999 − 00078 + 1 = 99922, respectively. [1]
SU M 1 = (+992) − (+78)
SU M 1 = 00992+10’s complement of (00078)
SU M 1 = 00992 + 99922
SU M 1 = 100914, after discarding end carry SU M 1 = 00914 = +914 [1]

similarly for SU M 2
SU M 2 = (−992) + (+78)
SU M 2 =10’s complement of (00992) + 00078
SU M 2 = 99008 + 00078
SU M 2 = 99086, no carry so we need to take 10’s complement back −ve sign, that is:
SU M 2 = −(10’s complement of 99086) = −(99999 − 99086 + 1) = −(00914) = −(+914) = −SU M 1 [1]

(b) Make a table listing two different self complimenting codes, if inputs are (A, B, C, D).

[2+2]

Solution: A necessary condition for a self-complimenting code is that the sum of its weights should be 9, e.g. in
Excess-3 code 8 + 4 + 2 + 1 + 3 = 18 = 1 + 8 = 9, in 631-1 code 6 + 3 + 1 − 1 = 9 and in 2421 code 2 + 4 + 2 + 1 = 9.
Examples are: [2] marks for each code.

You were required to make a table listing all 16 combinations for (A, B, C, D) inputs. To verify your solution take
a number such as 1011 = 5 in 2421 code. Complement of 1011 is 0100 = 4 in 2421 code, which is complement of 5,
thus 2421 code is self-complementing.

Q2. (a) If F = x + y, find its dual Fd and prove that Fd is an identity element with respect to (+) operator and F is
another identity element with respect to (.) operator. Hint: a + 0 = a and a.1 = a where 0 is an identity element
with respect to (+) operator and 1 is an identity element with respect to (.) operator, respectively.

[1+1+1]
Elex. & Comm. ECE — Digital Circuits and Systems Page 2 of 4

Solution: Dual Fd of F is: Fd = x.y [1]

Based on the hint a + 0 = a and a.1 = a lets calculate F + Fd and F.Fd .
F + Fd = x + y + x.y
F + Fd = x + x.y + y + x.y = x.(1 + y) + y.(1 + x) = x.1 + y.1 = x + y
F + Fd = F comparing with a + 0 = a, Fd is an identity element with respect to (+) operator. [1]
Similarly for F.Fd
F.Fd = (x + y).(x.y) = x.x.y + x.y.y = x.y + x.y = x.y
Fd .F = Fd comparing with a.1 = a, F is an identity element with respect to (.) operator. [1]

(b) Prove also from part (a) that F + F 0 = 1 and F.F 0 = 0.

[1+1]

Solution: Complement of F , that is F 0 = (x + y)0 = x0 y 0

Then,
F +F 0 = x+y +x0 y 0 = x+x0 y 0 +y +x0 y 0 = (x+x0 )(x+y 0 )+(x0 +y)(y +y 0 ) = x+y 0 +x0 +y = (x+x0 )+(y +y 0 ) = 1 [1]

similarly,
F.F 0 = (x + y)(x0 y 0 ) = xx0 y 0 + x0 yy 0 = 0 [1]
Bonus marks, if you have written correctly theorem’s and/ or postulate’s names used.

Q3. X and Y are the input of a circuit which produces Difference D (of X − Y ) and Borrow B as outputs. Implement
the circuit using minimum 2 : 1 multiplexers.

[1+2]

Solution: One mark for the table and two marks for the circuit. Digital circuit can be design in two ways.

I0 I0
X Y D B 2:1 2:1
I1 D=X XOR Y I1 D=X XOR Y
0 0 0 0 1 1
I0 I0
0 1 1 1 2:1 2:1
0 I1 0 I1
1 0 1 0 I0 0 I0
1 1 0 0 2:1 2:1
0 I1 B=X'Y I1 B=X'Y
Y X

X Y

Figure 1:
.

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MSB in LSB in

C
x S Q

A B (XOR) Clk
R
MSB o/p LSB o/p
(a) (b) (c)

E
A O/P
J Q

Clk B

‘1’ K Q’ C
D

(d) (e)

Figure 2: Refer for section II

Section II: .
1. An 8 bit ripple carry adder is to be realized using some full adders FA (all identical) and half adderes HA (all
identical). The worst case carry and sum propogation of full adder is 12ns and 15ns, respectively. The worst case
carry and sum propogation of half adder is 10ns and 15ns, respectively. Calculate the worst case delay (in ns) of
best design of 8 bit adder using these FAs and HAs only. [03]
Solution: Best solution with 7 FAs and 1 HA
Available at t = 0 ns
b7 a7 b6 a6 b5 a5 b4 a4 b3 a3 b2 a2 b1 a1 b0 a0

FA FA FA FA FA FA FA HA
CY_8 CY_7 CY_6 CY_5 CY_4 CY_3 CY_2 CY_1
94ns 82ns 70ns 58ns 46ns 34ns 22ns 10ns

Sum_7 Sum_6 Sum_5 Sum_4 Sum_3 Sum_2 Sum_1 Sum_0

97ns 85ns 73ns 61ns 49ns 37ns 25ns 10ns
Ans: Total Delay

Figure 3:
.
2. X and Y are the input of a circuit which produces Differene D (of X−Y) and Borrow B as outputs. Implement the
circuit using minimum 2:1 multiplexers. [02]
Solution: Best solution with 3 - 2:1 Mux

I0 I0
X Y D B 2:1 2:1
I1 D=X XOR Y I1 D=X XOR Y
0 0 0 0 1 1
I0 I0
0 1 1 1 2:1 2:1
0 I1 0 I1
1 0 1 0 I0 0 I0
1 1 0 0 2:1 2:1
0 I1 B=X'Y I1 B=X'Y
Y X

X Y

Figure 4:
.
3. Consider the circuit shown in the Fig. 1(c) and find the expression for next state Q+ as a function of x and Q. [02]
Solution: Ans: Qn+1 = Qn XNOR X

D
Qn S Q
X in here Q(n+1) = D’
D = Qn XOR X Clk
= Qn XNOR X
R

Figure 5:
.

4. Design a JK flip-flop using D flip-flop and some other gates. [02]

Solution:
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Elex. & Comm. ECE — Digital Circuits and Systems Page 4 of 4

K D Q

J Q’
Clk

Figure 6:
.

5. Whether the circuit shown i Fig. 1(e) is sequential or not (consider all gates as ideal with zero propogation delay) ?
Prove your answer with reasoning. [02]
Solution: Although circuit has a feedback element in its architecture but as explain in the Fig. 6 the output is
always stuck at ’1’ means does not follow any input sequence. Hence, this circuit can not be classify as sequential
circuit.

Figure 7:
.
6. In the circuit (shown in Fig. 1(d)) JK flip-flop has J and K as inputs and Q and Q’ as outputs. It is configured as
J = Q’ (means Q’ is connected to the input J) and K = ’1’. Initially flip-flop is cleared and then FF is clocked with
6 clock pulses. Calculate the sequence at the output Q for these 6 clock pulses (in the answer MSB should belongs
to the value of Q corrrosponds to 6th clock pluse and LSB should belongs to the value of Q corrosponds to 1st clock
pulse). [03]
Solution: From 6 to 1 = sequence is 010101 as explained in Fig. 7

1 2 3 4 5 6
CLK

Q 1 0 1 0 1 0

Q’

J
K
Initial State

Figure 8:
Section III - SET B - Objective Questions - with. 25% negative marking:
1. Correct hamming code for a binary code D4 D3 D2 D1 = 1101 (Hint - even parity check and p0 bit is at the extreme
left in the hamming code ):
(a) 0 1 1 0 0 1 1 (b) 0 1 0 1 1 0 1 (c) 0 0 1 0 0 1 1 (d) 0 1 0 0 1 0 0 (e) 0 0 1 1 0 0 1. [01]
2. In SR latch racing condition occurs for input conditions which are (latch is enabled in all cases) (a) S = R =’1’
followed by S = R = ’0’ (b) S = R =’0’ followed by S = R = ’1’ (c) when S = R =’1’ (d) S = R =’1’ followed by
any other input combination (e) S = R = ’0’ followed by any other input combination. [0.5]
3. For output Qn of J-K flip flop to have a transition from ’0’ to ’1’ (with the edge of the clock pulse), the value of the
inputs J and K are , respectively (a) ’1’ and X (don’t care) (b) ’0’ and X (c) X and ’1’ (d) X and ’0’ (e) ’1’ and ’0’. [0.5]
4. Booloean expression for the shaded area shown in Fig. 1(a) is: (a) AB + B’C’ (b) AB + B’C’ + A’B’ (c) ABC’
+ A’B’C + A’B’C (d) A’B’C + ABC’ (e) ABC + AB’C’. [0.5]
5. The circuit shown in Fig. 1(b) converts . (a) BCD to Binary (b) Binary to Excess-3 (c) Binary to Grey (d) Grey to
Binary (e) Grey to Excess-3. [0.5]
Answer Sheet:
1. (a) 2. (a) 3. (a) 4. (c) ABC’ + A’B’C + A’B’C and (d) A’B’C + ABC’ (as in SET B) 5. (d)

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