Advancing Low-Power Innovation

Analog / Mixed-signal Power, Noise, and Reliability Solution

Columbus

Totem-MMX is a transistor-level power/ Dynamic Power Integrity

ground noise analysis and verification
solution addressing static and dynamic
power integrity needs from early stage Substrate Noise Coupling
in the design to sign-off validation. It
addresses the verification of IPs de-
signed using full-custom or semi-cus- Power & Signal EM
tom techniques for both analog and
mixed-signal designs. Totem enables
designers to verify power grid connec- Interactive Layout-based Debug
tion problems, identify high voltage
drop causing mechanisms, and isolate
electro-migration bottlenecks. Macro Model Creation

Key Capabilities

• Delivers
full-chip capacity with • Provides
built-in extraction and • Layout-driven
analysis integrated with
SPICE-level accuracy for transient simulation engine with fast incremental existing analog design environment
power/ground noise analysis and “what-if” analysis • Ability
to generate models for hierarchical
• Concurrently
analyzes noise propagation • Enablesgrid weakness check, “hot spot” full-chip and system-level simulation
through power delivery network, substrate root cause identification, and design fix • Performspower and signal electro-migration
network, and package/PCB parasitics exploration, delivering significant time
signoff supporting industry standard and
savings and productivity enhancements
advanced process technology EM limit

Overview Accuracy and Capacity

Totem-MMX is a comprehensive solution that Totem-MMX incorporates transistor-level board RLC through the support of broadband
incorporates transistor-level noise injection, modeling with voltage de-rated switching S-parameter package and PCB models.
parasitic extraction, package modeling, current techniques and SPICE-accurate
dynamic analysis, and design debug in a decoupling capacitance (decap) extraction
single-flow environment to enable analog/ for highly accurate power noise analysis. It
mixed-signal designers to mitigate design pre-characterizes the circuit using the SPICE
failure risks and reduce the product cost. netlist, device models and input vector set, and
is simulated using industry standard SPICE
simulators. The characterization process Circuit modeling for PG noise simulation
captures switching current waveforms for all
switching transistors as a function of voltage Totem-MMX delivers the capacity required
for various operating conditions, as well as for standalone DRAM, Flash, and CMOS
their intentional and intrinsic capacitance. It image sensors, as well as embedded
also considers the impact of package and memory macros.

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Totem-MMX™ Analog / Mixed-signal Power, Noise, and Reliability Solution

Layout-based Unified Analysis top-level connectivity and noise coupling Signal EM checks on flattened transistor-level
and Debugging Environment scenario for block/IP-level analysis. Once designs as well as on block-level inter-cells
validated, the designer can generate a for embedded digital blocks. Its layout-based
Totem-MMX provides advanced viewing, detailed model capturing layout and circuit GUI with cross probing capabilities provides
debugging and fixing capabilities to effectively behavior of the IP. easy to use and robust debugging including
analyze and optimize full-custom designs.
detailed violation reports with current values
Its layout-driven interface is integrated with IP model generated by Totem-MMX, Custom
and their direction.
existing analog design environment and Macro Model (CMM™), captures different
supports cross-probing of power noise operating states such as “read” and
violations with the industry standard layout “write” with its associated current and other
schematic tools, as well as interactively parameters. It also enables designers to
analyze the fixes made in the design. embed constraints such as maximum voltage
drop allowance on transistors or a metal layer
for top-level verification.

For multi-company IP integration, Totem-MMX

provides various levels of IP encryption to
protect the intellectual property of the circuitry.
It delivers an optimized model for quick
top-level analysis, while preserving the
overall integrity and without compromising
its accuracy. Signal EM debugging – Searches shortest
path of resistance
Power and Signal
Reliability Analysis Connectivity Weakness Exploration
Totem-MMX provides a single platform for Totem-MMX verifies grid connectivity issues,
Multi-frame GUI – Cross check layout, netlist and power rail and signal interconnect electro- such as missing vias and weakly connected
analysis report on single page migration (EM) analyses. Power EM is devices. These connectivity issues can be
performed as part of static or dynamic debugged using the GUI and textual reports.
The powerful ‘what-if’ capability allows de- analysis. It supports EM limit for 65/45/28nm Totem-MMX’s network topology analysis
signers to quickly verify a fix before committing processes and provides checks for average, provides insights into routing issues that
to the layout. Fixes such as decap insertion RMS and peak current densities. The EM can cause voltage drop hot-spots or current
and addition or removal of metal or via can be results are easily checked and analyzed in the congestions in the design. The shortest
verified using incremental extraction and re- layout-based environment. electrical path from the voltage supply pads
analysis to ensure that the proposed change to every transistor is provided as an overlay on
does indeed fix the violation. the design layout allowing one to identify the
bottleneck segments.

Integrated views of EM result table and violation

Signal EM analysis is performed for average,

“What-if” analysis for upsizing wire width to fix IR drop RMS, and peak current densities in all signal Integrated views of transistor pin resistance
wires and vias. It supports unified run with and its minimum resistance path
IP Creation and SoC-level Analysis
separate uni-directional and bi-directional
Totem-MMX can analyze and validate power current analysis. Totem-MMX either estimates
noise issues at the IP level and generate a the current based on design parameter and
model of that IP that can be used for SoC or user input or imports the current based on
top-level power noise analysis. It incorporates actual SPICE simulation. Totem-MMX analyzes

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