4

Instructions Set of 8086

4.1 INTRODUCTION

Program is a set of instructions written to solve a problem. Instructions are the directions
which a microprocessor follows to execute a task or part of a task.
Broadly computer language can be divided into two parts as high-level language and low-
level language. Low-level languages are machine specific. Low-level language is further divided
into machine language and assembly language.
Machine language is the only language which a machine can understand. Instructions in
this language are written in binary bits as a specific bit pattern. The computer interprets this
bit pattern as an instruction to perform a particular task. The entire program is a sequence of
the binary numbers. This is a machine-friendly language but not user friendly. Debugging is
another problem associated with machine language.
To overcome these problems, programmers develop another way in which instructions are
written in English alphabets. This new language is known as Assembly language. The instructions
in this language are termed mnemonics. As microprocessor can only understand the machine
language so mnemonics are translated into machine language either manually or by a program
known as assembler.
Efficient software development for the microprocessor requires a complete familiarity with
the instruction set, their format and addressing modes. This chapter is devoted to develop an
understanding regarding the addressing modes and instruction formats of all the instructions
of microprocessor 8086.
This chapter can be divided into three parts. The first part deals with the addressing modes
of 8086. The second part discusses the instruction formats and instruction templates of 8086.
Finally the third part covers the instructions of 8086 microprocessor.

4.2 ADDRESSING MODES OF 8086

The addressing modes are the ways of specifying an operand in an instruction. In 8086 the
addressing modes are broadly categorized into two groups, i.e. data addressing modes and
74
 Instructions Set of 8086 75
address addressing modes. Data addressing modes are for defining a data operand in the
instruction whereas address addressing modes are the ways of specifying a branch address in
control transfer instructions.

4.2.1 Data Addressing Modes

The 8086 microprocessor introduces many new techniques to access the memory by introduction
of many more types of addressing modes. With these new memory related addressing modes,
it can access memory in many different ways. These addressing modes provide flexibility to
the processor to access memory, which in turn allows the user to access variables, arrays,
records, pointers, and other complex data types in a more flexible manner. Mastery of the 8086
addressing modes is the first step towards the understanding of 8086 assembly language.
The microprocessor 8086 has all the five data addressing modes available in 8085, i.e.
implied, register, immediate, direct and register indirect. The register indirect addressing mode
in 8086 works with SI, DI, BX and BP registers. Apart from these data addressing modes,
8086 has five more addressing modes. These are:
1. Base addressing mode
2. Index addressing mode
3. Based indexed addressing mode
4. Based indexed with displacement addressing mode
5. String addressing mode
Different addressing modes may take differing amounts of time to compute the effective
address. Complex addressing modes take more time to compute the effective address than the
simpler addressing modes. Complexity of an addressing mode will go on increasing with the
number of terms in the addressing mode. For example, [BX] [DI] is more complex than [DI].
Similarly disp [BX] [DI] is more complex than [BX] [DI].
The displacement in all the memory-related addressing modes can be a signed 8-bit constant
or a signed 16-bit constant. For 8-bit displacement the offset is in the range of –128 ... +127
and the instruction will be shorter and faster as compared to the instructions which uses the
16-bit signed displacement. It is always preferable to use a small displacement (8-bit) and a
large number in the register(s) instead of using large displacement (16-bit) and small value in
the register(s) because the size of the value in the register does not affect the execution time
or size.
When the BIU of microprocessor calculates the effective address, and finds that the
address sum is more than 16-bit, i.e. address value is greater than FFFFH, then the microprocessor
discards the overflow and the result wraps around back to zero. For example, if DI contains
1000H, then the instruction MOV CL, 0FFFFH [DI] will load the CL register from location
DS: 1000H.
Immediate addressing mode
In immediate addressing mode the operands are specified within the instruction itself. The
immediate operand can only be the source operand. For example,
MOV AX, 2500H
Here the immediate data is 2500H.
76 Microprocessor 8086—Architecture, Programming and Interfacing

Register addressing mode

Most 8086 instructions can operate on the 8086’s general purpose register set. The content of
a register can be accessed by specifying the name of the register as an operand to the instruction.
For example, the following MOV instruction of 8086 copies the data from the source operand
to the destination operand.
MOV AX, BX
MOV DL, AL
MOV SI, DX
The 8- and 16-bit registers are the valid operands for this instruction. The only restriction
is that both operands must be of the same size.
The registers are the best place to keep often used variables. Instructions using the registers
are shorter and faster than those that access memory.
Segment registers can never be used as data registers to hold arbitrary values. They should
only contain segment addresses.
Direct addressing mode or the displacement only addressing mode
Direct addressing mode displacement only addressing mode may be defined as the addressing
mode in which the address of the memory is specified in the instruction itself. In this addressing
mode the instruction consists of a 16-bit memory address or an 8-bit IO address. The 16-bit
memory address is always written inside the square brackets. For example, the instruction
MOV BL, [2000H], transfers the content of the memory location 2000H in the BL register.
Similarly, the instruction MOV [1234H], DL transfers the content of the DL register in the
memory location specified by 1234H. Figure 4.1 shows the direct addressing mode.

Figure 4.1 Direct addressing mode.

By default, all the direct addressing mode point in the data segment. The segment override
prefix is to be used before address if we have to point any other memory segment.
For example, to access location 4321H in the extra segment ES the instruction will be of the
form MOV AX, ES: [4321H]. Similarly, to access this location in the code segment, the
instruction will be MOV AX, CS: [4321H].
Register indirect addressing modes
This addressing mode is also used in concern with memory and IO. In this addressing mode,
the memory address is specified by some pointer, index or base registers. These registers are
 Instructions Set of 8086 77
written inside the square brackets. There are four forms of this addressing mode on the 8086,
best demonstrated by the following instructions:
MOV DX, [BX]
MOV DX, [BP]
MOV DX, [SI]
MOV DX, [DI]
These four addressing modes refer the word at the offset found in the BX, BP, SI or DI
registers, respectively. The [BX], [SI], and [DI] modes use the DS segment by default. The
[BP] addressing mode uses the stack segment (SS) by default.
To access data from other than the default segment, the segment override prefix symbols
are to be used. The following instructions demonstrate the use of these overrides:
MOV AX, CS:[BX]
MOV AX, DS:[BP]
MOV AX, SS:[SI]
MOV AX, ES:[DI]
Base addressing mode
In this mode 8-bit or 16-bit displacement is added to the contents of a base register (BX or
BP); the resulting value is a pointer to location where data resides. In this addressing mode,
the memory location is calculated by adding the signed 8-bit or 16-bit displacement to either
BX or BP register.
È BX 8-bit displacement Ø
Memory location = É ± Ù
É
Ê BP 16-bit displacement ÙÚ
For example if BX = 2000H, the instruction is
MOV AL, [BX + 15]
In this example, the contents of the memory location 200FH (2000H + 0FH (equivalent
to decimal 15)) is transferred to AL register. The maximum 8-bit displacement can be ± 127
and the maximum 16-bit displacement can be ± 32767.
There are four possible combinations of the base addressing modes, i.e.
BX ± 8-bit displacement
Memory location = BX ± 16-bit displacement
BP ± 8-bit displacement
BP ± 16-bit displacement
The displacement can also be written as
MOV AL, DISP [BX]
The addressing modes involving BX, use the data segment, the addressing mode involving
[BP] uses the stack segment by default. As with the register indirect addressing modes, the
segment override prefixes can be used to specify a different segment:
78 Microprocessor 8086—Architecture, Programming and Interfacing

MOV AL, SS: DISP [BX]

MOV AL, ES: DISP [BP]
Figure 4.2 shows how the offset address will be calculated for the instruction MOV AX,
[BX + 15].

Figure 4.2 Calculation of offset address in base addressing mode.

Index addressing mode

This addressing mode is similar to base addressing mode with the difference that in this mode
the 8-bit or 16-bit displacement is added to the contents of an index register (SI or DI). In this
addressing mode, the memory location is calculated by adding the signed 8-bit or 16-bit
displacement to either SI or DI register.

È SI 8-bit displacement Ø
Memory location = É ± Ù
É
Ê DI 16-bit displacement ÙÚ
There are four possible combinations of the base addressing modes, i.e.
SI ± 8-bit displacement
Memory location = SI ± 16-bit displacement
DI ± 8-bit displacement
DI ± 16-bit displacement
Data segment is the default segment for this addressing mode. As with the register indirect
and base addressing modes, the segment override prefixes can be used to specify a different
segment:
MOV AL, CS: DISP [SI]
MOV AL, SS: DISP [DI]
The offset address in this addressing mode will be calculated as shown in Figure 4.2 by
replacing the BX contents by SI or DI contents.
Note that Intel still refers to these addressing modes as based addressing and indexed
addressing. Intel’s literature does not differentiate between these modes with or without the
constant.
 Instructions Set of 8086 79
Based indexed addressing mode
The based indexed addressing modes are simply the combinations of the register indirect
addressing modes. In based indexed addressing mode, the contents of a base register (BX or
BP) are added to the contents of an index register (SI or DI), the resulting value is a pointer
to location where data resides.

È SI BX Ø
Memory location = É + Ù
É
Ê DI BP ÙÚ
The allowable forms for these addressing modes are:
MOV AL, [BX][SI]
MOV AL, [BX][DI]
MOV AL, [BP][SI]
MOV AL, [BP][DI]
For example, if BX = 2000H and SI = 5400H, the instruction is
MOV AL, [BX + SI]
In this example the contents of the memory location 7400H (2000H + 5400H) is transferred
to AL register.
The addressing modes that do not involve bp use the data segment by default. Those that
have bp as an operand use the stack segment by default.
There are four possible combinations of the base addressing modes, i.e.
SI + BP
Memory location = SI + BX
DI + BP
DI + BX
Figure 4.3 shows how the offset address will be calculated for the instruction MOV AX,
[BX + DI].

Figure 4.3 Calculation of offset address in base index addressing mode.

Based indexed with displacement addressing mode

In this addressing mode, the offset address is generated by the sum of Base register and Index
registers along with 8-bit or 16-bit displacement. In this addressing mode, 8-bit or 16-bit
80 Microprocessor 8086—Architecture, Programming and Interfacing

displacement is added to the contents of a base register (BX or BP) and index register (SI or
DI); the resulting value is a pointer to location where data resides.
È SI BX 8-bit displacement Ø
Memory location = É + ± Ù
É
Ê DI BP 16-bit displacement ÙÚ
In this addressing mode the memory location is calculated by adding the signed 8-bit or
16-bit displacement to the sum of the content of SI + BP or SI + BX or DI + BP or DI +
BX.
Considering the same example, i.e. if BX = 2000H and SI = 5400H, the instruction is
MOV AL, [BX + SI + 15]
In this example, the contents of the memory location 740FH (2000H + 5400H + 0FH
(equivalent to decimal 15)) is transferred to AL register. Again the maximum 8-bit displacement
can be ± 127 and the maximum 16-bit displacement can be ± 32767.
There are eight possible combinations of the base index with displacement addressing
mode, i.e.
SI + BP ± 8-bit displacement
SI + BX ± 8-bit displacement
DI + BP ± 8-bit displacement
Memory location = DI + BX ± 8-bit displacement
SI + BP ± 16-bit displacement
SI + BX ± 16-bit displacement
DI + BP ± 16-bit displacement
DI + BX ± 16-bit displacement
The following are some of the examples of these addressing modes:
MOV AL, DISP [BX][SI]
MOV AL, DISP [BX + DI]
MOV AL, [BP + SI + DISP]
MOV AL, [BP][DI][DISP]
Figure 4.4 shows how the offset address will be calculated for the instruction MOV AX,
[BX + DI + 15].

Figure 4.4 Calculation of offset address in relative base index addressing mode.
 Instructions Set of 8086 81
String addressing modes
This mode uses index registers. The string instructions automatically assume SI to point to the
first byte or word of the source operand and DI to point to the first byte or word of the
destination operand.
The segment register for the source is DS and may be overridden. The segment register
for the destination must be ES and cannot be overridden.
The contents of SI and DI are automatically incremented by clearing DF (Direction Flag)
to 0 by CLD instruction or automatically decremented by setting DF to 1 by STD instruction.
Table 4.1 summarizes all the 32 possible data addressing modes of 8086.

Table 4.1 Summary of data addressing modes

(BX) + (SI) (BX) + (SI) + d8 (BX) + (SI) + d16 AL AX
(BX) + (DI) (BX) + (DI) + d8 (BX) + (DI) + d16 CL CX
(BP) + (SI) (BP) + (SI) + d8 (BP) + (SI) + d16 DL DX
(BP) + (DI) (BP) + (DI) + d8 (BP) + (DI) + d16 BL BX
(SI) (SI) + d8 (SI) + d16 AH SP
(DI) (DI) + d8 (DI) + d16 CH BP
d16 (BP) + d8 (BP) + d16 AH SP
(BX) (BX) + d8 (BX) + d16 BH DI

4.2.2 Address Addressing Modes

These addressing modes indicate the branch addresses in the call and jump instructions.
In 8086 there are four types of address addressing modes, i.e. intrasegment direct, intrasegment
indirect, intersegment direct and intersegment indirect. In intrasegment the branching is within
the segment and in intersegment the branching is outside the segment. Intersegment is a
synonym for far, intrasegment is a synonym for near.
Intrasegment direct
In this addressing mode the effective branch address will be the sum of the signed 8- or
16-bit displacement and the content of the IP. When the displacement is of 8-bit, then this is
referred to as short jump or short call, otherwise long jump or long call. For example, consider
the following two jump instructions
JMP 8-bit displacement; direct intrasegment, 8-bit displacement
JMP 16-bit displacement; direct intrasegment, 16-bit displacement
These two forms of the direct intrasegment jump are the same except their length. In the
case of JMP 8-bit displacement instruction, the microprocessor sign extends this 8-bit displacement
into 16-bits and then add it to the IP register to point the jump location. With the help of this
instruction, microprocessor can transfer the control either to a branch location to 128 locations
before the JMP instruction location or to 127 locations ahead of the JMP instruction. Or, we
can say that with 8-bit displacement the control can be transferred within a memory location
space of –128 to +127. The JMP 8-bit displacement is a two-byte long instruction.
The second form of the intrasegment jump is three bytes long with the first byte as the
opcode and the next two bytes as displacement. This instruction allows a memory range of
82 Microprocessor 8086—Architecture, Programming and Interfacing

–32,768 to +32,767 locations. This instruction can transfer control to anywhere in the current
code segment. The microprocessor adds the two byte displacement to the IP register contents
to point to the jump location.
The 8-bit displacement can be used with conditional as well as unconditional call and
jump instructions but the 16-bit displacement can be used only in unconditional instructions.
Figure 4.5 shows a graphical means to compute the effective address of the branched address.

Figure 4.5 Calculation of the EA of the branched address in intrasegment direct addressing mode.

Intrasegment indirect
In this addressing mode the effective address is specified by any of the register or memory
contents. The memory location can be specified by any of the memory related data addressing modes.
In this addressing mode the content of the IP is replaced by the effective branch address. This
addressing mode is used only for unconditional branch instructions. Consider the example
JMP Disp [BX]; Disp is an array of words
This addressing mode fetches the word from location disp + BX and copies this value to
the IP register. Figure 4.6 shows a graphical means to compute the effective address of the
branched address.

Figure 4.6 Calculation of the EA of the branched address in intrasegment indirect addressing mode.

Intersegment direct
In this addressing mode the contents of IP are replaced by a part of the instruction and the
contents of the CS is replaced by another part of the instruction. The 32-bit operand is loaded
into the IP and CS register. The direct intersegment jump or call is five bytes long, the last
four bytes containing a segmented address (the offset in the second and third bytes,
the segment in the fourth and fifth bytes). This instruction copies the offset into the IP register
and the segment into the CS register. Execution of the next instruction continues at the new
address in CS:IP. The address following the opcode is the absolute memory address of the
target instruction. This instruction loads CS:IP with a 32-bit immediate value. Intersegment
 Instructions Set of 8086 83
Direct does not use relative addressing. Figure 4.7 shows a graphical means to compute the
effective address of the branched address.

Figure 4.7 Calculation of the EA of the branched address in intersegment direct addressing mode.

Intersegment indirect
In this addressing mode the contents of IP and CS are replaced by the contents of the four
consecutive memory locations pointed by any of the memory-related data addressing modes
except the immediate and register addressing mode. Figure 4.8 shows a graphical means to
compute the effective address of the branched address.

Figure 4.8 Calculation of the EA of the branched address in intersegment indirect addressing mode.

EXAMPLE 4.1 Given that

BX = 2500H SI = 5000H Displacement = 1000H IP = 2000H
Determine the effective address for the following addressing modes:
(i) Immediate (ii) Register using SI (iii) Direct
(iv) Register indirect using BX (v) Base (vi) Index
(vii) Base index (viii) Base index relative.
Solution
(i) For immediate addressing mode effective address is the content of the IP, so EA = 2000H.
(ii) For register addressing using SI, the EA = 5000H
(iii) For direct addressing using the displacement, the EA = 1000H
(iv) For register indirect addressing using BX, the EA = 2500H
(v) For base addressing using displacement, the EA = 2500H + 1000H = 3500H
(vi) For index addressing using displacement, the EA = 5000H + 1000H = 6000H
(vii) For base index addressing the EA = BX + SI = 2500H + 5000H = 7500H
(viii) For base index relative addressing the EA = BX + SI + Disp = 2500H + 5000H +
1000H = 8500H.
84 Microprocessor 8086—Architecture, Programming and Interfacing

EXAMPLE 4.2 Find the branch address for the following address addressing modes:
(i) Intrasegment direct
(ii) Intrasegment indirect using BX register
(iii) Intrasegment indirect using base addressing
(iv) Intrasegment direct
(v) Intrasegment indirect using BX register using relative addressing
Assume the following:
IP = 2500H CS = 2000H BX = 3000H DS = 4000H Immediate value (16-bit) = 1500H.
Immediate value (32-bit) = 1500:3500H [43000H] = 40FD3598H [44500H] = 05F6H.
Solution
(i) For intrasegment direct addressing mode, the branch address will be the sum of the
16-bit immediate value present in the instruction and the content of IP.
So branch address = 1500H + 2500H = 4000H.
(ii) For intrasegment indirect addressing mode, using BX register and register addressing,
the branch address will be the value present in the BX register.
So branch address = 3000H.
(iii) For intrasegment indirect addressing mode, using base addressing, the branch address
will be the value present in the memory location pointed by [DS:BX] plus the displacement.
So branch address = [DS * 10H + BX + Disp] = [44500H] = 05F6H.
(iv) For intersegment direct addressing mode the branch address will be the immediate
value present in the instruction. The first word of the immediate value will go to the
IP and the remaining will go to the CS register.
So branch address will be IP = 1500H and CS = 3500H.
(v) For intersegment indirect addressing mode using BX register and register addressing
the branch address will be the content of the memory location pointed by the [DS:BX]
register. The first word will go to the IP and the second will go to the CS register.
So branch address = [DS * 10H + BX] = [43000H] = 40FD3598H
So IP = 40FDH and CS = 3598H.

4.3 INSTRUCTION FORMAT

The instructions of 8086 may be one to six byte long. These instructions have different
formats. Figure 4.9 shows some of the instruction formats.

Figure 4.9 Examples of Instruction format.

 Instructions Set of 8086 85
The first byte always consists of the opcode. The opcode may be of 8-bit or may occupy
MSB six bits of the first bytes and it defines the operation to be carried out by the instruction.
The remaining two bits are any of the following bits.
1. Direction bit (D) defines whether the register operand in byte 2 is the source or destination
operand.
D = 1 specifies that the register operand is the destination operand.
D = 0 indicates that the register is a source operand.
2. Data size bit (W) defines whether the operation to be performed is an 8 bit or 16 bit data.
W = 0 indicates 8-bit operation
W = 1 indicates 16-bit operation
3. Sign bit (S) is used for sign extension of an 8-bit 2’s compliment number to a 16-bit
2’s compliment number. This is done by making all the bits in high-order byte same as
that of MSB in the lower-order byte. This bit appears with the W bit in add, subtract
and compare instructions. For 8-bit operation S:W bits are 00 and these bits are 01 for
16-bits operation with 16-bit immediate operand.
S:W bits are 11 for 16-bit operation with a sign-extended 8-bit immediate operand.
4. V-bit is used in shift and rotate instruction to determine the number of shifts.
V = 0 indicates that the shift count is 1
V = 1 indicates that CL register contains the shift count
5. The Z-bit is used in REP instruction. The Z-bit is matched with the zero flag bit.
The REP instruction goes on executing till the Z-bit does not match with the zero flag.
A summary of these bits encoding is shown in Table 4.2.
Table 4.2 Single-bit field encoding
Field Value Function
S 0 No sign extension
1 Sign extend 8-bit immediate data to 16-bits if W = 1
W 0 Instruction operates on byte data
1 Instruction operates on word data
D 0 Instruction source is specified in REG field
1 Instruction destination is specified in REG field
V 0 Shift/rotate count is one
1 Shift/rotate count is specified in CL register
Z 0 Repeat/loop while zero flag is clear
1 Repeat/loop while zero flag is set

As shown in Figure 4.9, depending on the instruction, the opcode byte may be the only
byte in the instruction or may be followed by
• One or two byte long immediate data
• One or two byte long displacement
• One or two byte long displacement and then one or two byte long immediate data
• Two byte long direct address
• Two byte long displacement and then two byte long segment address
86 Microprocessor 8086—Architecture, Programming and Interfacing

The presence of these additional bytes depends on the opcode byte of the instruction.
Figure 4.10 shows an instruction format of MOV instruction.

Figure 4.10 Instruction template for the MOV instruction.

4.4 INSTRUCTION TEMPLATES

8085 has total 246 opcodes. These opcodes can be printed on a single paper sheet but such
is not the case with 8086 microprocessor.
For example, consider the case of the MOV AX, Source instruction. As there are altogether
32 different addressing modes so the source can be specified by any of those 32 ways.
Similarly, if AX becomes the source, then again there will be 32 different ways to specify the
destination. Hence there are 64 opcodes for MOV instruction involving AX register at source
and destination location. Still there will be another 64 opcodes if AL is used and 64 more
opcodes can be generated by using AH register. In a nutshell there will be 192 opcodes only
for MOV instruction involving AX, AL, and AH registers.
Microprocessor 8086 has about 13000 opcodes which require 60 pages to tabulate these
opcodes.
It becomes very tedious to find out the opcodes of the 8086 instructions from a book of
60 pages. So instruction templates are used for each basic instruction to generate the opcodes
by filling the bits in the templates corresponding to those instructions. In other words, the
opcodes are generated on a bit by bit basis. Figure 4.10 shows the instruction template for the
MOV instruction to transfer data between registers or between register and memory location
specified by any of the addressing mode.
In the MOV instruction template the MSB six bits of the first byte is of the op code and the
LSB two bits are D and W bits. The second byte of the instruction usually identifies whether one
of the operands is in memory or whether both are registers. This byte contains 3 fields. These
are the mode (MOD) field, the register (REG) field and the Register/Memory (R/M) field.
These three fields are encoded as per Table 4.3.
 Instructions Set of 8086 87
Table 4.3 Encoding of MOD and R/M field
MOD/R/M MOD 11
MOD 00 MOD 01 MOD 10 W=0 W=1
000 (BX) + (SI) (BX) + (SI) + d8 (BX) + (SI) + d16 AL AX
001 (BX) + (DI) (BX) + (DI) + d8 (BX) + (DI) + d16 CL CX
010 (BP) + (SI) (BP) + (SI) + d8 (BP) + (SI) + d16 DL DX
011 (BP) + (DI) (BP) + (DI) + d8 (BP) + (DI) + d16 BL BX
100 (SI) (SI) + d8 (SI) + d16 AH SP
101 (DI) (DI) + d8 (DI) + d16 CH BP
110 d16 (BP) + d8 (BP) + d16 DH SI
111 (BX) (BX) + d8 (BX) + d16 BH DI
¬ Memery Mode (EA Calculation) ® ¬ Register Mode ®

In the second byte the MSB two bits D 7 and D6 are defined as MOD field. The MOD field
defines whether the R/M field is for register or memory and if it is for memory then is there
no displacement, or an 8-bit displacement or a 16-bit displacement. These two bits are encoded as:
MOD = 00: R/M for memory with no displacement
MOD = 01: R/M for memory with 8-bit displacement
MOD = 10: R/M for memory with 16-bit displacement
MOD = 11: R/M for a register.
Register field occupies 3 bits D3, D4, and D5. This field defines the register for the first
operand which is specified as source or destination by the D bit. D3, D4, and D5 are encoded
as per Table 4.4.

Table 4.4 Encoding of REG field

REG W=0 W=1
000 AL AX
001 CL CX
010 DL DX
011 BL BX
100 AH SP
101 CH BP
110 DH SI
111 BH DI

The R/M field occupies LSB 3 bits: D0, D1 and D2. The R/M field along with the MOD
field defines the second operand as shown in Table 4.5 for MOD = 11. In this table, for
example, suppose the second operand is AX, then R/M field will be 000.
If the second operand is memory then the MOD field will be either 00 or 01 or 10
depending on how the memory is addressed. Table 4.6 shows the encoding of the R/M field
along with the MOD field for MOD = 00, 01 and 10.
88 Microprocessor 8086—Architecture, Programming and Interfacing

Table 4.5 Encoding of R/M field for MOD = 11

R/M W=0 W=1
000 AL AX
001 CL CX
010 DL DX
011 BL BX
100 AH SP
101 CH BP
110 DH SI
111 BH DI

Table 4.6 Encoding of R/M field for MOD = 00, 01, 10

R/M MOD 00 MOD 01 MOD 10
000 (BX) + (SI) (BX) + (SI) + D8 (BX) + (SI) + D16
001 (BX) + (DI) (BX) + (DI) + D8 (BX) + (DI) + D16
010 (BP) + (SI) (BP) + (SI) + D8 (BP) + (SI) + D16
011 (BP) + (DI) (BP) + (DI) + D8 (BP) + (DI) + D16
100 (SI) (SI) + D8 (SI) + D16
101 (DI) (DI) + D8 (DI) + D16
110 Direct address (BP) + D8 (BP) + D16
111 (BX) (BX) + D8 (BX) + D16

In the above, encoding of the R/M field depends on how the mode field is set. If MOD = 11
(register to register mode), this R/M identifies the second register operand. MOD selects
memory mode, then R/M indicates how the effective address of the memory operand is to be
calculated. Bytes 3 through 6 of an instruction are optional fields that normally contain the
displacement value of a memory operand and/or the actual value of an immediate constant
operand.
Segment override prefix
Segment override prefix (SOP) is used when a default offset register is not used with its
default base segment register, but with a different base register. In instruction format one byte
is appended as suffix, for segment override before the opcode byte. The format of this byte
is shown in Figure 4.11.

Figure 4.11 Format of the segment override instruction.

 Instructions Set of 8086 89
In this format the SR indicates the segment register. The four segment register is encoded
as shown in Figure 4.11. For example, to use DS as the new register in place of default register
we have to use 3EH as a prefix byte. Table 4.6 shows the offset registers and their respective
default segment registers and segment override prefix.
In Table 4.7 it is shown that IP and SP can never be associated with any other segment
registers apart from their respective default segments. Similarly when DI is used as an implied
memory pointer for string instructions, then it can only be used with its default segment
register, i.e. ES. The other offset registers can be used with any of the segment registers using
segment override prefix.
Examples MOV AX, DS: [BP],
LODS ES: DATA 1

Table 4.7 Probable override prefixes

Operand register Default With override prefix
IP (Code address) CS Never
SP (Stack address) SS Never
BP (Stack address) SS BP + DS or ES or CS
SI or DI (not including strings) DS ES, SS or CS
SI (Implicit source address for strings) DS ES, SS or CS
DI (Implicit destination address for strings) ES Never

EXAMPLE 4.3 Construct the machine code for the instruction MOV BL, CH.
Solution This instruction copies the 8-bit content of CH to BL.
The instruction template of this instruction will be of two bytes only and shown in Figure 4.12.

Figure 4.12 Template for MOV BL, CH.

The 6-bit opcode for this instruction is 100010.

Since this instruction transfer only 8-bit, hence W = 0 shows a byte operation.
D-bit indicates whether the register specified by the REG field of byte 2 is a source or
destination operand.
90 Microprocessor 8086—Architecture, Programming and Interfacing

D = 0 indicates CH is a source operand.

In byte 2, since the second operand is a register, MOD field will be 11.
The R/M field = 011 (BL)
Register (REG) field = 101 (CH)
Hence the machine code for MOV BL, CH will be 88EBH.
The same instruction can be coded by another way by considering BL register in REG
field. In this case the D bit is defined in concern with the BL register and now it will be
D = 1 because the BL register is destination.
The R/M field = 101 (CH)
Register (REG) field = 011 (BL)
Hence the machine code for MOV BL, CH will be 8ADDH

Figure 4.13 Machine code for MOV BL, CH.

The machine code for the instruction MOV BL, CH is shown in Figure 4.13. These two
machine codes will perform the same function, i.e. MOV BL, CH.
EXAMPLE 4.4 Construct the machine code for the instruction MOV 1234 [SI], AX.
Solution Here REG field will specify the AX register, the D bit must be 0, indicating the
AX is the source register. The REG field must be 000 to indicate AX register. The W bit must
be 1 to indicate it is a word operation. 1234 [SI] is specified using MOD value of 10 and
R/M value of 100 and a displacement of 1234H. The 4-byte code for this instruction would
be 89 8434 12H and is shown in Figure 4.14.

Figure 4.14 Machine code for the instruction MOV 1234 [SI], AX.

EXAMPLE 4.5 Construct the machine code for MOV DS: 43 [BP], CX.
Solution Here we have to specify CX using REG field. The D bit must be 0, indicating that
CX is the source register. The REG field must be 001 to indicate CX register. The W bit must
be 1 to indicate it is a 16-bit operation. 43 [BP] is specified with MOD = 01 and R/M = 110
and displacement = 43H.
Whenever BP is used to generate the Effective Address (EA), the default segment would
be SS. But here in this instruction segment override is used, i.e. the segment register DS is
used. In such cases segment override prefix byte (SOP byte) is to be used. The SOP byte is
001 SR 110, where SR value is provided as per Table 4.8 shown below.
 Instructions Set of 8086 91
Table 4.8 Segment override prefix byte (SOP byte) table.
SR Segement register
00 ES
01 CS
10 SS
11 DS

To specify DS register, the SOP byte would be 001 11 110 = 3EH.

The complete template and the machine code are shown in Figure 4.15. The machine code
for this instruction would be 3E 89 4E 43H.

Figure 4.15 Complete template (a) and the machine code of MOV DS: 43 [BP], CX instruction (b).

EXAMPLE 4.6 Construct the machine code for IN AX, 35H.

Solution The instruction template of the IN instruction is shown in Figure 4.16.

Figure 4.16 Instruction template for IN instruction.

So the machine code for IN AX, 35H is 1110010100110101, i.e. E535H.

EXAMPLE 4.7 Construct the machine code for SUB BX, [DI].
Solution The instruction template of the SUB BX, [DI] instruction is the same as that of a
two byte MOV instruction
The 6-bit opcode for SUB is 001010.
D = 1 so that REG field of byte 2 is the destination operand. W = 1 indicates 16-bit
operation.
92 Microprocessor 8086—Architecture, Programming and Interfacing

MOD = 00
REG = 011
R/M = 101
The machine code is 0010 1011 0001 1101 = 2B1DH.

4.5 INSTRUCTION SET OF 8086

The instruction set of 8086 microprocessor can be broadly classified into eight groups depending
on the functions these instructions perform. The Data Transfer Instructions are used for transferring
data from source location to destination location. The Arithmetic Instructions are used to
perform arithmetic operations like addition, subtraction, multiplication and division. Logical
Instructions perform the logical operations like AND, OR, EXOR operations. Shift and Rotate
Instructions are used to perform the logical and arithmetic shift operations and left and right
shifting. String Instructions performs the string related operations. The Data Adjustment
Instructions are used to convert the binary data in ASCII or in BCD format. As the name
suggests the Flag Related Instructions are used to modify the flag bits. The Control Transfer
Instructions are used to transfer the control within the program or from main program to
subroutine program or from subroutine to main program. The Machine Control Instructions
are used to perform the machine control operations like halt.

4.5.1 Data Transfer Instructions

The data transfer instructions copy values from one location to another. These instructions
include MOV, XCHG, XLAT, LDS, LEA, LES, PUSH, PUSHF, POP, POPF, LAHF, SAHF,
IN, and OUT.
MOV destination, source Move source to destination
The MOV Instruction copies the second operand (source) to the first operand (destination)
without modifying the contents of the source. In true sense these are not the data transfer
instructions but data copy instruction because the source is not modified.
The source operand can be an immediate value, general-purpose register or memory location.
The destination register can be a general-purpose register, or memory location. Both operands
must be the same size, which can be a byte or a word.
The following types of operands are supported:
MOV REG, memory
MOV memory, REG
MOV REG, REG
MOV memory, immediate
MOV REG, immediate
Here the register may be any of the general purposes registers, i.e. AX, BX, CX, DX, AH,
AL, BL, BH, CH, CL, DH, DL, DI, SI, BP, and SP. The memory may be specified by any
of the memory-related addressing modes. Immediate data can only be specified at the source
location.
 Instructions Set of 8086 93
For segment registers only these types of MOV are supported:
MOV SREG, memory
MOV memory, SREG
MOV REG, SREG
MOV SREG, REG
A data cannot be transferred from a memory to another memory, from memory to an IO,
from an IO to another IO and from IO to memory. IO can communicate with Accumulator
only. The immediate data cannot be transferred into a segment register. The only instructions
that move data into or out of a segment register have mod-reg-r/m bytes associated with them;
there is no format that moves an immediate value into a segment register. Move to and from
segment registers are always 16-bits. Since we cannot load an immediate data directly into a
segment register so to initialize a segment register first we load the immediate data into a
general purpose data register and then transfer that data from the data register to the segment
register with the help of MOV instruction.
The MOV instruction cannot set the value of the CS and IP registers. Also it cannot copy
value of one segment register to another segment register. For example, if we want to initialize
the Data Segment by a memory location 02500H, then first we have to load the value 2500H
into AX register and then transferring the contents of AX to DS register with the help of the
following instructions.
Example MOV AX, 2500H,
MOV DS, AX
In MOV instruction the flag remain unchanged.
IN Input data from input port
Operands
AL, 8-bit port address
AL, DX
AX, 8-bit port address
AX, DX
This instruction transfers a byte or word from a port to the accumulator register. The port
address is specified by the source operand, which can be DX or an 8-bit constant. If the port
address is of 8-bit then direct addressing will be used.
Example
IN AX, 04H; Move the content of the port number 04H and 05H to AL and AH
IN AL, 70H; Move the content of the port number 70H to AL.
If the port number is of 16-bit, then indirect addressing will be used and DX will be the
default register to specify the port number. To note that the DX register is not enclosed in
square brackets like memory addressing.
Example
IN AX, DX; Move the content of the port number specified in DX and DX + 1 to AL and AH
IN AL, DX; Move the content of the port number specified in DX to AL.
94 Microprocessor 8086—Architecture, Programming and Interfacing

OUT Output data to output port

Operands
AL, 8-bit port address
AL, DX
AX, 8-bit port address
AX, DX
This instruction transfers a byte or word to an output port from the accumulator register.
The port address is specified by the destination operand. Port number may be of 8-bit or 16-
bit. For 16-bit port address DX register will be used and for 8-bit port address an 8-bit
constant will be used.
Example
OUT 04H, AX; Transfer the content of the AX register to the port 04H and 05H.
OUT 70H, AL; Transfer the content of the AL register to the port 70H.
OUT DX, AX; Transfer the content of the AX register to the port specified by DX and
DX + 1.
OUT DX, AL; Transfer the content of the AL register to the port specified by DX.
The flag register remain unchanged.
LDS Rd, M: Load pointer using DS Load pointer and DS register
This instruction is used to load the double word stored in memory into specified register and
DS register. The general purpose register is loaded from the lower-order word of the memory
operand and the segment register DS from the higher-order word. The memory may be specified
by any of the memory-related addressing mode. This instruction is very useful in string
instructions where the source is always DS:SI. For example, the following instruction may be
used to initialize both the SI and DS registers.
LDS SI, [BX]; SI is set to [BX:BX + 1] and DS is set to [BX + 2:BX + 3].
Figure 4.17 shows the action taken by the processor in response to this instruction.

Figure 4.17 LDS SI, [BX].

The flag register remain unchanged.

 Instructions Set of 8086 95
LEA Rd, M: Load effective address Load effective address
This instruction is used to load the effective address (offset) of the source memory operand
into the specified destination register.
It loads the specified 16-bit register with the effective (offset) address of the specified
memory location. For example, LEA SI, DS:[4F00H] loads the destination register SI with the
value 4F00H. Here, in this example, the same operation can also be performed by the MOV
instruction, i.e. MOV AX, 4F00H.
But the LEA instruction also computes the effective address of the memory for a particular
addressing mode which a MOV instruction does not perform. For example, consider the
following LEA instruction:
LEA DI, 3[SI]
This instruction copies the address of the memory location 3[SI] into the DI register, i.e.
it adds three with the value in the SI register and moves the sum into DI. Now the MOV
instruction cannot add 3 to the content of SI before loading it to DI. So the LEA instruction
can be used to do a MOV operation and an addition with a single instruction.
In this instruction the flag remain unchanged.
LES Rd, M: Load pointer using ES Load effective address and ES register
This instruction is used to load the double word stored in memory into specified register and
ES register. The general purpose register is loaded from the lower-order word of the memory
operand and the segment register ES from the higher-order word. The source M can be
specified by any of the memory-related addressing modes. This single instruction can be used
to initialize the string destination ES: DI. For example:
LES DI, [BX + 15]; DI is set to [BX + 15:BX + 16] and ES is set to [BX + 17:BX + 18].
Figure 4.18 shows the action taken by the processor in response to this instruction.

Figure 4.18 LES DI, [BX + 15].

The flag remain unchanged.

96 Microprocessor 8086—Architecture, Programming and Interfacing

XCHG Exchange
Operands Rd, M
M, Rs
Rd, Rs
Exchange values of two operands. The order of the XCHG’s operands does not matter but both
operands should be of the same size. The flag register remain unchanged after this instruction.
For example, if BL = 15 and AH = 20, then after the instruction XCHG BL, AH the
content of BL will be 20 and AH will be 15.
PUSH Push content on to stack top
Operands REG
SREG
memory
Push instruction pushes the source operand onto the stack. After the PUSH instruction, the
content of SP is decreased by 2 and the source value is copied to SS:SP. The PUSH instruction
always operates on words. The operands in the PUSH instruction can be a memory location,
a general purpose 16-bit register, or a segment register. PUSH SP copies the value of SP after
the push.
For example, if the content of the AX register is 1234H, then after the PUSH AX instruction
the 12h is loaded on [SP] and 34H is loaded on [SP – 1] and SP is further decremented by
1 and becomes SP = SP – 2. The flag register remain unchanged after this instruction.
POP Pop-off contents from top of stack
Operands REG
SREG
memory
This instruction pops the top of the stack into the destination operand. This means that the
value at SS:SP is copied to the destination operand and SP is increased by 2. The destination
operand can be a memory location, a general purpose 16-bit register, or any segment register
except CS. For example, if the top of the stack contains 12H and 34H, then after the instruction

Figure 4.19 PUSH and POP instructions.

 Instructions Set of 8086 97
POP BX, the SP is increased by 1 and the content of that location is loaded into BL and SP
again is incremented by 1 and the content of that location is loaded into BH. The flag register
remain unchanged after this instruction.
PUSHF no operands Push flag on top of stack
The flag register is pushed onto the stack. The higher byte of the flag register is pushed at
[SP]. SP is then decremented by 1 and then lower byte of flag is pushed on the [SP]. The SP
is again decremented by 1. The flag register remain unchanged after this instruction.
POPF no operands Pop off flag from top of stack
This instruction pops the value on the top of the stack into the flags register. First the SP is
incremented by 1 then the byte of the top of the stack will be popped into the lower byte of
the flag register. Again the SP will increase by 1 and the next byte from the stack will be
loaded into the higher byte of the flag register. The flag register remain unchanged after this
instruction.
LAHF no operands Load flag
Load the AH register by the lower byte of the flag register which contains the status flag, i.e.
carry, parity, auxiliary carry, zero, and sign flags. By this instruction we can see the contents
of the status flag.
SAHF no operands Store flag
Store the AH register in the lower byte of the flag register which contains the status flag, i.e.
carry, parity, auxiliary carry, zero, and sign flags. By this instruction we can modify the
contents of the status flag.
XLAT Translate
This is the translate instruction which is used to translate a value from one coding system to
another with the help of a lookup table. In this instruction BX is by default one of the registers
which points to the starting location of the lookup table. This BX register must be initialized
before the XLAT instruction. AL is the second register used in this instruction and contains
the unsigned value which is to be translated from the table. The pointed table value will be
transferred in the AL register after the execution of the instruction. This instruction do not
required any operand. DS is the by default segment which can be override by segment override
prefix. The XLAT instruction will perform the operation AL = DS:[BX + unsigned AL].
For example, consider the program
LEA BX, 2000H
MOV AL, 20
XLAT
In this program AL will be loaded with the content of the memory location pointed by
[2000 + 20]. The flag register remain unchanged after this instruction.
98 Microprocessor 8086—Architecture, Programming and Interfacing

4.5.2 Arithmetic Instructions

Microprocessor 8086/8088 may perform the arithmetic operations on four types of data, i.e.
signed binary, unsigned binary, unsigned unpacked BCD and unsigned packed BCD. The
binary numbers may be of 8-bit or of 16-bits, they may be signed or unsigned. The BCD
numbers are always unsigned and may be in packed BCD or unpacked BCD form.
The 8086 provides many arithmetic operations: addition, subtraction, negation, multiplication,
division/modulo (remainder), and comparing two values. The instructions that handle these
operations are ADD, ADC, SUB, SBB, MUL, IMUL, DIV, IDIV, NEG, INC, DEC, CBW and
CWD.
In the arithmetic instructions the flag register is modified.
ADD Add
Operands REG, memory
memory, REG
REG, REG
memory, immediate
REG, immediate
These instructions add a data from source operand to a data from destination and save the
result in the destination operand. The source and destination must be of the same type, means
they must be a byte type or a word type. If a byte is to be added to a word, then the byte must
be converted to a word by extended the D7 bit of the byte in the upper byte of the word.
Segment registers cannot be used as an operand in ADD instruction. Memory to memory and
IO to memory addition is also not permitted.
The following example demonstrates how the ADD instruction can be used to perform the
operation F = X + Y + Z:
MOV AX, X
ADD AX, Y
ADD AX, Z
MOV F, AX
Flag bits are modified as per the result of the operation.
ADC Add with carry
Operands REG, memory
memory, REG
REG, REG
memory, immediate
REG, immediate
This instruction adds the source operand to the destination operand along with the carry flag.
The result is stored in the destination operand. This instruction is used to add the data which
are of large in size, i.e. double word type. Both ADD and ADC instructions affect the flags
identically.
 Instructions Set of 8086 99
For example, the following example shows the addition of the two numbers 12345678H
and FEDB4321H with the help of ADC instruction.
MOV AX, 5678H
ADD AX, 4321H
MOV BX, 1234H
ADC BX, FEDBH
SUB Subtract
Operands REG, memory
memory, REG
REG, REG
memory, immediate
REG, immediate
This instruction subtracts the source operand from the destination operand and stores the result
in the destination operand. Segment registers cannot be used as an operand in ADD instruction.
Memory to memory and IO to memory addition is also not permitted. Flag bits are modified
as per the result of the operation.
Example MOV AL, 05H SUB AL, 02H
After the execution of the SUB instruction AL will contain 03H.
SBB Subtract with borrow
Operands REG, memory
memory, REG
REG, REG
memory, immediate
REG, immediate
Subtract with borrow. This instruction subtracts the source from the destination along with the
value of the carry flag. The result is stored in the destination. This instruction is used to
subtract the data which are of large in size, i.e. double word type.
The SBB instruction computes the value
DEST operand = DEST operand – SRC operand – Carry flag.
The carry flag will set if an unsigned overflow occurs during the SUB and SBB instructions.
For example, the following example shows the subtraction of FEDB4321H from 12345678H.
MOV AX, 5678H
SUB AX, 4321H
MOV BX, 1234H
SBB BX, FEDBH
INC Increment
Operands REG
memory
100 Microprocessor 8086—Architecture, Programming and Interfacing

Increment the operand by 1. This instruction increment the destination operand by 1. This
instruction differs with the ADD by 1 instruction in the way that the INC instruction does not
affect the carry flag whereas the ADD instruction modifies the carry flag. The INC instruction
is more compact and often faster than the comparable ADD instruction because it is a one-
byte instruction.
In INC all flags, except the carry flag, changes as that of in ADD and ADC instructions.
DEC Decrement
Operands REG
memory
Decrement the operand by 1. This instruction decrement the destination operand by 1.
This instruction differs with the SUB by 1 instruction in the way that the DEC instruction does
not affect the carry flag whereas the SUB instruction modifies the carry flag. The DEC
instruction is more compact and often faster than the comparable ADD instruction because it
is a one-byte instruction. In DEC except the carry flag all other flag changes as that of in SUB
and SBB instructions.
DIV Unsigned division
Operands REG
memory
This instruction divides the contents of the AX or the DX:AX by a specified source operand.
The AX and the DX:AX is the implied destination operands for 16-bit and 32-bit division.
This is an unsigned operation and hence both operands are treated as unsigned operands. If
the divisor is 16-bits wide, then the dividend is the DX:AX register pair. After the division
the quotient will be stored into AX and the remainder into DX. When the divisor is of 8 bits,
the dividend is AX. And in this case the quotient will be stored in AL and the remainder in
AH. Figure 4.20 shows the pictorial representation of DIV. All the flag bits are undefined, i.e.
the value of all the flag bits may be either 0 or 1.

Figure 4.20 Pictorial representation of DIV and IDIV.

Example MOV AX, 00C8H

MOV CL, 06H
DIV CL
After this program the result is available in AL (= 21H) and the remainder is present in AH
(= 02H).
 Instructions Set of 8086 101
IDIV Signed division
Operands REG
memory
This instruction is exactly the same as that of DIV except that here both operands are signed
numbers. Figure 4.20 shows the pictorial representation of IDIV. In both DIV and IDIV
instructions, the source operand cannot be an immediate data or a segment register. All the
flag bits are undefined, i.e. the value of all the flag bits may be either 0 or 1.
Example MOV AX, – 200; AX = 0FF38H
MOV CL, 6
IDIV CL
After this program the result is available in AL (= DFH = – 33) and the remainder is
present in AH (= FEH = 02).
MUL Multiplication
Operands REG
memory
This instruction multiplies the contents of the AL or the AX by a specified source operand.
The AL and the AX are the implied destination operands for 8-bit and 16-bit multiplication.
This is an unsigned operation and hence both operands are treated as unsigned operands.
In this instruction both the implied operand and the source operand must be of the same size.
For a 16-bit multiplication, the implied operand will be the AX register. After the multiplication
the product, which is of 32-bits, will be stored into the DX:AX register pair. For an 8-bit
multiplication, the implied operand will be the AL register. After the multiplication the product,
which is of 16-bits, will be stored into the AX register. If after the multiplication DX is not
0 for 16-bit operands or AH is not zero for 8-bit operands, then the carry and overflow flags
will set. The A, P, S, and Z flags are undefined, i.e. the value of these flag bits may be either
0 or 1. Figure 4.21 shows the pictorial representation of MUL.

Figure 4.21 Pictorial representation of MUL and IMUL.

Example MOV AL, 0FDH

MOV CL, 05H
MUL CL; AX = 04F1H
CF = OF = 0 when high section of the result is zero.
102 Microprocessor 8086—Architecture, Programming and Interfacing

IMUL Signed multiplication

Operands REG
memory
This instruction is exactly the same as that of MUL except that here both operands are signed
numbers. In both MUL and IMUL instructions, the source operand cannot be an immediate
data or a segment register. If the product is sign extended into DX for 16-bit operands, into
AH for 8-bit operands then the carry and overflow flags are set and the remaining flag bits,
i.e. the A, P, S, and Z flags are undefined, i.e. the value of these flag bits may be either 0 or
1. Figure 4.21 shows the pictorial representation of IMUL.
Example MOV AL, –03H
MOV CL, –05H
IMUL CL; AX = 000FH
CF = OF = 0 when result fits into operand of IMUL.
NEG Negate
Operands REG
memory
This instruction produces the two’s complement of the specified operand and stored the result
in the same operand. Microprocessor performs the negate (NEG) operation by subtracting the
operand from 0. This is done to represent a negative number. All the flag bits are modified
as per the result. The carry flag will be set for a non-zero operand and for a zero operand it
will be reseted. If the operand contains the maximum possible negative value (–128 for 8-bit
operands or –32768 for 16-bit operands), the value does not change, but the overflow and
carry flags are set.
Example MOV AL, 15H
NEG AL; AL = 0EBH (2’s Complement of 15H)
CBW no operands Convert byte to word
CBW converts the signed value in the AL register into an equivalent 16-bit signed value in
the AX register by extending the sign bit to the left.
This instruction copies the sign of a byte in AL to all the bits in AH. AH is then said to
be the sign extension of AL. The flags are not modified and remain unchanged.
MOV AX, 0; AH = 0, AL = 0
MOV AL, F5H
CBW; AX = 0FFF5H
In this example, F5H is equivalent to 11110101B, this means the sign bit is 1. After the CBW,
the sign bit (1 in this case) will be extended into AX register.
Similarly,
MOV AX, 0; AH = 0, AL = 0
MOV AL, 55H
CBW; AX = 0055H
 Instructions Set of 8086 103
In this example, 55H is equivalent to 01010101B, this means the sign bit is 0 hence after
the CBW the sign bit (0 in this case) will be extended into AX register (i.e. 0055H).
CWD no operands Convert word to double word
Convert word into double word. CWD converts the 16 bit signed value in the AX register into
an equivalent 32-bit signed value in DX:AX register pair by duplicating the sign bit to the left.
The CWD instruction sets all the bits in the DX register to the same sign bit of the AX
register. The effect is to create a 32-bit signed result that has the same integer value as the
original 16-bit operand. The flags are not modified and remain unchanged.
Example MOV DX, 0
MOV AX, 0
MOV AX, –14H; DX:AX = 0000H:0FFECH
CWD; DX:AX = 0FFFFH:0FFECH

4.5.3 Logical Instructions

The 8086 provides six logical instructions. The logical instructions are AND, OR, XOR,
TEST, NOT and CMP. These instructions can manipulate bits, convert values, do logical
operations, pack and unpack data operations.
AND Logically AND
Operands REG, memory
memory, REG
REG, REG
memory, immediate
REG, immediate
This instruction performs a bitwise Logical AND of destination operand and the source
operand. The result of the operation is stored in the destination operand. The AND operation
is performed as per Table 4.9. The Z, S, and P flag bits are modified as per the result. The
carry and overflow flag bits are 0 and auxiliary carry is undefined (i.e. may be 0 or 1).

Table 4.9 Truth table of the different logical operations

AND OR EXCLUSIVE OR NOT
A B A·B A B A–B A B A(–)B A /A
0 0 0 0 0 0 0 0 0 0 1
0 1 0 0 1 1 0 1 1 1 0
1 0 0 1 0 1 1 0 1 – –
1 1 1 1 1 1 1 1 0 – –

Example MOV AL, 61H; AL = 01100001

AND AL, CFH; AL = 01000001
104 Microprocessor 8086—Architecture, Programming and Interfacing

CMP Compare
Operands REG, memory
memory, REG
REG, REG
memory, immediate
REG, immediate
This instruction compares the source operand with the destination operand. Microprocessor
executes this CMP instruction by subtracting the source operand from the destination operand
but none of the operands are modified. The result is reflected by the flag bits. Generally the
result (i.e. flag conditions) of this instruction is used for conditional control transfer instructions.
The comparison may be a signed comparison or an unsigned comparison. For unsigned
comparison, the result is reflected by the Carry and Zero flag bits whereas for signed comparison
the result is reflected by the Zero, Sign and the Overflow flag.
For unsigned comparison operation, consider instruction CMP AX, BX, the microprocessor
performs the AX – BX operation.
Now if AX = BX, then the result will be zero and hence the zero flag will set. If AX is
greater than BX, the result will be non-zero and positive and hence both the Zero and Carry
are reset. Similarly, when BX is greater than AX, then to perform AX – BX we require to take
borrow and hence the Zero flag is reset and the carry is set.
For signed comparison if the EX-OR operation of the Sign and Overflow flag is 1, then
the result is negative. It is to be noted that for signed comparisons, the sign flag doesn’t show
the proper status. For example, CMP AX, BX.

Flag condition Result

Sign flag Overflow flag
0 1 AX < BX
1 0 AX < BX
0 0 AX > BX
1 1 AX > BX

The CMP instruction also affects the parity and auxiliary carry flags, but these two flags
are rarely tested after a compare operation.
NOT Logically NOT
Operands REG
memory
This instruction complements the individual bits of the operand and save the result in the same
operand. In other words, we can say that it generates the 1’s complement or the NOT operation
of the operand. After this instruction the flag register remain unmodified. Table 4.8 shows the
logical NOT operation.
Example MOV AL, 39H
NOT AL; AL = C6H
 Instructions Set of 8086 105
OR Logically OR
Operands REG, memory
memory, REG
REG, REG
memory, immediate
REG, immediate
This instruction performs a bitwise logical OR operation between the source and destination
operands. The result is stored in the destination operand. Table 4.8 shows the logical OR
operation. After the operation, the Z, S, and P flag bits are modified whereas the carry and
overflow flag bits are 0 and auxiliary carry is undefined (i.e. may be 0 or 1).
TEST Test
Operands REG, memory
memory, REG
REG, REG
memory, immediate
REG, immediate
This instruction performs logical AND between all bits of the source and destination operands.
In this instruction perform the logical AND operation but none of the operands is modified,
it is only the ZF, SF, PF flags are modified. The carry and the overflow flags are cleared.
This instruction is used to tests specified bits of an operand and sets the flags for a
subsequent conditional jump or set instruction. One of the operands contains the value to be
tested. The other contains a bit mask indicating the bits to be tested. TEST works by doing
a logical bitwise AND on the source and destination operands. The flags are modified according
to the result, but the destination operand is not changed. This instruction is the same as the
AND instruction, except that the result is not stored.
Example MOV AL, 25H
TEST AL, 05H; ZF = 0
TEST AL, 20H; ZF = 0
XOR Logically EX-OR
Operands REG, memory
memory, REG
REG, REG
memory, immediate
REG, immediate
This instruction performs a bitwise exclusive OR operation between the source and destination
operands. After the operation, the result is stored in the destination. Table 4.8 shows the
logical EX-OR operation. The Z, S, and P bits of the flag register are modified as per the
result whereas the carry and overflow flag bits are set to 0 and auxiliary carry is undefined
(i.e. may be 0 or 1).
106 Microprocessor 8086—Architecture, Programming and Interfacing

4.5.4 Shift and Rotate Instructions

The 8086 provides four rotate instructions, and three shift instructions. This is the second set
of instructions which are used for bit manipulation. The 8086 supports three different shift
instructions (SHL and SAL are the same instruction), SHL (shift left), SAL (shift arithmetic
left), SHR (shift right), and SAR (shift arithmetic right). The shift instructions move bits
around in a register or memory location.
Rotate instructions are the third set (apart from Shift and Logical instructions) of instructions
which are used for bit manipulation. The rotate instructions shift the bits around, just like the
shift instructions, except the bits shifted out of the operand by the rotate instructions recirculate
through the operand. They include RCL (rotate through carry left), RCR (rotate through carry
right), ROL (rotate left), and ROR (rotate right).
These instructions can manipulate bits, convert values, do logical operations, pack and
unpack data, and do arithmetic operations.
RCL Rotate left through carry
Operands memory, immediate
REG, immediate
memory, CL
REG, CL
The RCL instruction is used to rotate the operand1 left through the Carry Flag. In this
instruction the second operand may be an immediate value or the counter register CL.
This second operand decides the number of times the rotation will take place.
The RCL instruction moves the D 15 or D7 bit to the Carry Flag and the Carry Bit goes to
the D0 bit position and all other bits shift towards left, i.e. to the higher bit position in the
operand register. RCL sets the overflow flag if the sign changes as a result of the rotate when
the rotate count is one. If the count is not one, the overflow flag is undefined. Only carry and
overflow flags are modified, whereas, rest of the flag bits, i.e. zero, sign, parity or auxiliary
carry flags remain undefined, i.e. may be 0 or 1. Figure 4.22 shows the pictorial representation
of RCL.

Figure 4.22 Pictorial representation of RCL.

Example STC; set carry (CF = 1)

MOV AL, 5AH; AL = 01011010
MOV CL, 03H
RCL AL, CL; AL = 11010101, CF = 0
 Instructions Set of 8086 107
ROL Rotate left
Operands memory, immediate
REG, immediate
memory, CL
REG, CL
The ROL instruction is used to rotate the operand 1 left. In this instruction the second operand
may be an immediate value or the counter register CL. This second operand decides the
number of times the rotation will take place.
The ROL instruction moves the D15 or D7 bit to the D0 bit position of the operand as well
as to the carry flag and all other bits shifts towards left, i.e. to the higher bit position in the
operand register. The ROL instruction is similar to the RCL instruction with a difference that
the carry flag bit is not part of the rotation. ROL sets the overflow flag if the sign changes
as a result of the rotate when the rotate count is one. If the count is not one, the overflow flag
is undefined. Only carry and overflow flags are modified whereas rest of the flag bits, i.e.
zero, sign, parity, or auxiliary carry flags remain undefined, i.e. may be 0 or 1. Figure 4.23
shows the pictorial representation of ROL.

Figure 4.23 Pictorial representation of ROL.

Example STC; set carry (CF = 1)

MOV AL, 5AH; AL = 01011010
MOV CL, 03H
ROL AL, CL; AL = 11010010, CF = 0
RCR Rotate right through carry
Operands memory, immediate
REG, immediate
memory, CL
REG, CL
This instruction performs the rotation of the contents of operand1 right through the Carry Flag.
In this instruction the second operand may be an immediate value or the counter register CL.
This second operand decides the number of times the rotation will take place. This instruction
RCR is the complement to the RCL instruction. In this instruction the D 0 bit of the operand1
is shifted to the carry flag, the carry flag is shifted to the D15 or the D7 bit and all the other
bits are shifted towards the right, i.e. one bit down to itself. It shifts its bits right through the
carry flag and back into the MSB position.
After the execution only the carry and overflow flag bits are modified whereas rest of the
flag bits, i.e. zero, sign, parity, or auxiliary carry flags are undefined, i.e. they may be 0 or
108 Microprocessor 8086—Architecture, Programming and Interfacing

1. However, if the count is not one, the value of the overflow flag is undefined. Figure 4.24
shows the pictorial representation of RCR.

Figure 4.24 Pictorial representation of RCR.

Example STC; set carry (CF = 1)

MOV AL, 5AH; AL = 01011010
MOV CL, 03H
RCR AL, CL; AL = 10111010, CF = 0
ROR Rotate right
Operands memory, immediate
REG, immediate
memory, CL
REG, CL
Rotate operand1 right. This instruction is the same as that of RCR with a difference that the
LSB will go to the MSB position as well as to the carry. Only carry and overflow flags will
be modified rest will be undefined, i.e. may be 0 or 1. Figure 4.25 shows the pictorial
representation of ROR.

Figure 4.25 Pictorial representation of ROR.

Example STC; set carry (CF = 1)

MOV AL, 5AH; AL = 01011010
MOV CL, 03H
ROR AL, CL; AL = 01011010, CF = 0
SAL/SHL Airthmatic/logical shift left
Operands memory, immediate
REG, immediate
memory, CL
REG, CL
 Instructions Set of 8086 109
The SHL (Shift Logically Left) and SAL (Shift Arithmetically Left) are used to shift the
content of the first operand towards left. The encoding of these two mnemonics is the same.
The second operand may be an immediate data or the counter register CL and represent the
number of times the shifting takes place. While each bit of the operand shifts to left, the zeros
fill vacated positions at the lower order bit.
As we know that the shifting towards left is equivalent to multiply by 2 hence the
SHL/SAL instruction multiplies both signed and unsigned values by two for each bit shift.
The carry and the overflow flags will set for the unsigned and signed numbers if the result
does not fit in the destination operand, i.e. MSB is one. The AC flag is undefined after the
SHL/SAL instruction. Figure 4.26 shows the pictorial representation of SAL/SHL.

Figure 4.26 Pictorial representation of SHL/SAL.

SAR Airthmatically shift right

Operands memory, immediate
REG, immediate
memory, CL
REG, CL
Shift arithmetically the content of the first operand right by the number of times specified by
the second operand. The second operand may be an immediate data or the counter register CL.
In SAR while each bit is shifted right and goes to the carry flag, the sign bit is inserted from
the MSB side as shown in Figure 4.27.
As we know that shifting a binary number towards right is equivalent to dividing that
number by two, hence the SAR instruction is used to perform a signed division. Each shift
to the right divides the value of the destination by two. In some way, the SAR is similar to
the IDIV instruction except a difference that the IDIV instruction always truncates towards
zero while SAR truncates results toward the smaller result. For positive results, an arithmetic
shift right by one position produces the same result as an integer division by two. However,
if the quotient is negative, IDIV truncates towards zero while SAR truncates towards negative
infinity.
After the execution of the SAR instruction, the carry, parity and zero flag modified as per
the result. The sign remain unchanged, overflow flag is always zero and the AC flag is
undefined.

Figure 4.27 Pictorial representation of SAR.

110 Microprocessor 8086—Architecture, Programming and Interfacing

Example MOV AL, 8EH; AL = 10001110

MOV CL, 02H
SAR AL, CL; AL = 11100011; CF = 1.
SHR Logically shift right
Operands memory, immediate
REG, immediate
memory, CL
REG, CL
Shift, logically, the content of the first operand right by the number of times specified by the
second operand. The second operand may be an immediate data or the counter register CL.
In SHR while each bit is shifted right and goes to the carry flag, a zero bit is inserted from
the MSB side as shown in Figure 4.28. As the SHR performs division by two operations on
signed operand, similarly the SHR instruction performs division by two operations for unsigned
operands.
This instruction sets the overflow flag if the sign changes, i.e. if the shift count is one,
the overflow flag will contain the value of the higher order bit of the operand prior to the shift.
However, if the count is not one, the value of the overflow flag is undefined. The condition
of all other flag bits will be the same as in the case of SAR.

Figure 4.28 Pictorial representation of SHR.

Example MOV AL, 07H; AL = 00000111

MOV CL, 02H
SHR AL, CL; AL = 00000001; CF = 1

4.5.5 String Instructions

String instructions are the instructions used for manipulation of sequence of bytes or words
that contain the alphanumeric code for characters. These instructions are used for processing
the text. There are five types of string instructions in 8086. These instructions are for byte as
well as for words. The operands in string instructions may be an implied source or an implied
destination or both the source and destination may also be implied. The source string is always
in the data segment and the destination string is always in the extra segment. The source
location, i.e. data segment can be override but not the destination, i.e. extra segment.
The source index SI and the destination index DI will hold the offset of the source string and
the destination string respectively or in other words in string instructions DS:SI and ES:DI is
the default source and destination memory pointers. The SI and DI is auto updated after the
string instruction. The string instructions of 8086 are MOVS (move string), CMPS (compare
string), SCANS (scan string), LODS (load string) and STOS (store string).
 Instructions Set of 8086 111
CMPSB no operands Compare bytes string

CMPSW no operands Compare words string

These instructions are used to compare the two string bytes or string words stored in memory.
The source string is always pointed by SI in the data segment and the destination string is
pointed by the ES in the extra segment. To compare these two strings, the microprocessor
performs the subtraction operation. It subtracts the destination string from the source string.
After the operation, none of the operands is modified, only the flags are modified to reflect
the result. The SI and the DI registers are either incremented or decremented by one or two
depending on the status of the direction flag and according to the size of the operands.
They are increased if the direction flag is zero or decreased if the direction flag is one.
Though the source string is always present in the data segment but a segment override can
be used to other segment. The segment override cannot be used with the destination segment,
i.e. with extra segment. The compare instruction performs the comparison once for each CMP
instruction. If we wish to compare a series of string data stored in the source and destination
locations, then we use the REP instruction (to be discussed later in this section) as a prefix
to the CMP instruction.
LODSB no operands Load string byte

LODSW no operands Load string word

Load AL or AX by the string byte or string word pointed by SI in the Data Segment.
After the execution of the instruction, the SI is incremented by one (in case of string byte)
or two (in case of string word) if the direction flag is zero, otherwise the SI will be decremented
by the same value for byte and word string. The flag register will remain unmodified. A
segment override can be given to change the source segment DS.
MOVSB no operands Move string byte

MOVSW no operands Move string word

These instructions are used to transfer the string byte (MOVSB) or a word byte (MOVSW)
source pointed by DS:SI to the destination location pointed by ES:DI. After the execution of
the instruction, the SI and DI is incremented by one (in case of string byte) or two (in case
of string word) if the direction flag is zero, otherwise the SI and DI will be decremented by
the same value for byte and word string. The MOVS instruction is an excellent instruction
with the help of which we can transfer data directly from one memory location to another
memory location. If the source string is stored in a segment other than DS, then we can use
a segment override but it is not permissible for the destination segment, i.e. ES. For transferring
multiple string data the REP instruction is used as a suffix to MOVS. Before using the repeat
prefix the counter register CX must be initialize. The Flag register is not modified by the
MOVS instruction.
Example of MOVSB
LEA SI, 2000H
112 Microprocessor 8086—Architecture, Programming and Interfacing

LEA DI, 3000H

MOV CL, 15H
REP MOVSB
This program transfers 15H string bytes from DS:2000H to ES:3000H.
SCASB no operands Scan string byte

SCASW no operands Scan string word

These instructions are used to scan a string stored in memory to find a value specified in the
accumulator register. These instructions actually compare the string present in AL or AX with
the string stored in memory pointed by ES:DI. The SCAS instruction is performed by subtracting
each element of the destination from the accumulator contents. After the operation the flags
are updated to show the comparison result. After the operation none of the operands is
modified. The DI register is either incremented or decremented by one or two depending on
the status of the direction flag and according to the size of the operands. The DI is increased
if the direction flag is zero or decreased if the direction flag is one. In case of SCAS instruction
segment override is not allowed.
Generally a repeat prefix is used with the SCAS instruction. REPNE (or REPNZ) is used
to find the first match of the accumulator value. REPE (or REPZ) is used to find the first non-
match. Before using the SCAS instruction, CX or CL must be initialized with the maximum
number of elements to be compared. After the comparison, CX will be 0 if no match or non-
match was found. Otherwise SI and DI will point to the element after the first match or non-
match. Flag will be modified as per the result.
STOSB no operands Store string byte

STOSW no operands Store string word

These two instructions are used to store the string data available in the AL or AX in the
memory specified location by ES:DI. After the operation the DI register is either incremented
or decremented by one or two depending on the status of the direction flag and according to
the size of the operands. DI is increased if the direction flag is zero or decreased if the
direction flag is one.
STOSB and STOSW are generally used with the REP prefix. The counter register CX or
CL must be initialized before the repeated instruction is executed. Flag register remain unchanged.
The following program shows how the STOSW instruction is used:
LEA DI, 2000H
MOV AX, 25FEH
MOV CX, 5
REP STOSW
In this program first DI is initialized to point to the memory location 2000H in the Data
segment, then AX is loaded with the string value and counter CX is initialized with 5.
The REP STOSW instruction will store the AX contents (25FEH) in the memory location
ES:2000H onwards till CX is zero.
 Instructions Set of 8086 113
REP (unconditionally) Repeat unconditionally
This is a prefix instruction to a string instruction. This instruction repeats the string instruction
by the number of times indicated by CX. The execution of the string instruction stops when
CX is decremented to 0. The REP instruction is generally used with MOVS and STOS string
instructions. Except zero all the other flag bits are undefined.
REP (conditionally) Repeat conditionally
The repeat conditionally instruction which is used as prefix to a string instruction is used to
repeat a string instruction as long as condition is true and the CX is not zero. There are two
conditional repeat instructions and four mnemonics. These are REPE/REPZ and REPNE/
REPNZ. Before executing any of these instructions, CX must be initialized with the maximum
allowable number of repetitions. For each string element, the string instruction is performed,
CX is decremented, and the zero flag is tested. Except zero, all the other flag bits are undefined.
(i) REPE/REPZ Repeat till equal/Repeat till zero
REPE (Repeat till equal) and REPZ (repeat till zero) instructions are used to repeat a
string instruction till the zero flag is set. As in these two instructions the zero flag is
tested so these instructions are used with the SCAS and CMPS instructions as these are
the only string instructions that modify the zero flag. For example,
Repeat CMPSB, CMPSW, SCASB, SCASW instructions while ZF = 1 (result is Equal)
or till CX reaches to.
(ii) REPNE/REPNZ Repeat till not equal/Repeat if no zero
REPNE (Repeat till not equal) or REPNZ (repeat if no zero) instructions are used to
repeat a string instruction till zero flag is not zero or till CX becomes zero. For
example,
Repeat CMPSB, CMPSW, SCASB, SCASW instructions while ZF = 0 (result is Not
Equal) or till CX reaches zero.

4.5.6 Adjustment Instructions

AAA no operands ASCII adjustment after addition

AAA converts the result of the addition of two valid unpacked BCD digits to a valid packed
BCD number. AL register is the implied operand.
The decimal numbers in ASCII have a code from 30H (“0”) to 39H (“9”). When we add
two ASCII numbers, the result will not be in ASCII. The AAA instruction will adjust the result
of addition to a BCD digit. The instruction assumes that the add operands are proper ASCII
values.
If the addition produces carry (AF = 1), the AH register is incremented and the carry CF and
auxiliary carry AF flags are set to 1. If the addition did not produce a decimal carry, CF and AF
are cleared to 0 and AH is not altered. In both cases the higher 4-bits of AL are cleared to 0.
AAD no operands ASCII adjustment before division
AAD converts unpacked BCD digits in the AH and AL register into a single binary number
in the AX register in preparation for a division operation.
114 Microprocessor 8086—Architecture, Programming and Interfacing

The most significant BCD digit is stored in the AH register and the last significant BCD
digit is stored in AL register before the execution of AAD. The two unpacked BCD digits are
combined into a single binary number by the AAD instruction by setting AL = (AH*10) + AL
and clearing AH to 0. The carry, auxiliary carry and overflow flag bits are modified as per the
result and all other flag bits are undefined.
AAM no operands ASCII adjustment after multiplication
AAM converts the result of the multiplication of two valid unpacked BCD digits into a valid
unpacked BCD number. AX is the implicit operand in AAM.
AAM unpacks the result by dividing AX by 10, placing the quotient (Most Significant
Digit) in AH and the remainder (Least Significant Digit) in AL. In AAM, except carry and
auxiliary carry flag bits, all the other flag bits are undefined.
AAS no operands ASCII adjustment after Subtraction
AAS converts the result of the subtraction of two valid unpacked BCD digits to a single valid
BCD number. AL register is an implicit operand.
The two operands of the subtraction must have its lower 4-bit contain number in the range
of 0 to 9. The AAS instruction then adjust AL so that it contains a correct BCD digit.
The AAS instruction operates on strings of ASCII numbers with one-decimal digit (in the
range of 0 to 9) per byte. This instruction can be used after a SUB or SBB instruction on the
ASCII value. Except carry and auxiliary flag bits, all other flag bits are undefined.
DAA no operands Decimal adjust after addition
The DAA instruction adjusts the result of an addition to a packed BCD number. DAA converts
this binary sum to packed BCD format. If the sum is greater than 99h after adjustment, then
the carry and auxiliary carry flags are set. Otherwise, the carry and auxiliary carry flags are
cleared.
For example, two BCD values are added as if they were binary numbers and the result will
be in binary and then to convert this binary sum the DAA instruction is executed to correct
the result in BCD. The DAA instruction functions like AAA except it handles packed BCD
(binary code decimal) values rather than unpacked. All flag bits are modified as per the result.
DAS no operands Decimal adjust after subtraction
The DAS instruction adjusts the result of a subtraction to a packed BCD number (less than
100 decimal). DAS converts the binary result of subtraction into packed BCD. If the sum is
greater than 99H after adjustment, then the carry and auxiliary carry flags are set. Otherwise,
carry and auxiliary carry flags are cleared. All flag bits are modified as per the result.

4.5.7 Flag Related Instructions

These instructions are used to set or reset the individual control flag bits and also the carry
flag. No operands are associated with these instructions.
 Instructions Set of 8086 115
CLC no operands Clear carry
CLC clear the carry flag (CF) to 0. This instruction has no effect on the processor, registers,
or other flags. It is often used to clear the CF before returning from a procedure to indicate
a successful termination. It is also use to clear the CF during rotate operation involving the
CF such as ADC, RCL, and RCR.
CLD no operands Clear direction flag
This instruction reset the designation flag to zero. This instruction has no effect on the
registers or other flags. When the direction flag is cleared/reset SI and DI will automatically
be incremented when one of the string instructions such as MOVS, CMPS, SCAS, MOVSB
and STOSB executes.
CLI no operands Clear interrupt enable flag
This instruction resets the interrupt flag to zero. No other flags are affected. If the interrupt
flag is reset, the 8086 will not respond to an interrupt signal on its INTR input. This CLI
instruction has no effect on the nonmaskable interrupt input, NMI.
CMC no operands Complement carry
If the carry flag CF is zero before this instruction, it will be set to one after the instruction.
If the carry flag is one before this instruction, it will be reset to zero after the instruction
executes. CMC has no effect on other flags.
STC no operands Set carry
This instruction sets the Carry flag.
STD no operands Set direction flag
This instruction sets the Direction flag. SI and DI will be decremented by chain instructions:
CMPSB, CMPSW, LODSB, LODSW, MOVSB, MOVSW, STOSB, and STOSW.
STI no operands Set interrupt enable flag
This instruction sets the Interrupt enable flag. When the interrupt flag is set, maskable interrupts
are enabled. If interrupts were disabled by a previous CLI instruction, pending interrupts will
not be executed immediately; they will be executed after the instruction following STI.

4.5.8 Control Transfer Instructions

The control transfer instructions are used to transfer the control from one memory location to
another location. In 8086 there are four types of control transfer instruction, i.e. jump, call,
return and interrupt. All these type of control transfer instructions may be conditional or
unconditional. In case of conditional control transfer instructions, the control will be transferred
only if the condition is true.
CALL Call subroutine/procedure
Operands procedure name
label
4-byte address
116 Microprocessor 8086—Architecture, Programming and Interfacing

This instruction is used to transfer the control of execution to a subroutine or procedure.

There are two basic types of CALL instructions, the Near CALL and the Far CALL.
A CALL instruction is called Near CALL if the procedure is in the same code segment
as the main program.
When microprocessor executes the CALL instruction, the control is transferred to the
procedure but before it goes to the subroutine it saves the returning address on the top of
stack. The stack pointer is decremented by two and copies the offset of the next instruction
after the CALL on the stack.
The control is again transfer to the main program when microprocessor comes across RET
instruction at the end of the procedure. This is done by popping up the offset saved on the
stack back to IP.
When the procedure is stored in a code segment different from where the main program
is stored, the CALL instruction is called Far CALL. In this case also the returning address
which consists of CS:IP is stored at the top of stack. First the stack pointer is decremented
by two and stored the content of CS register to the stack top. Again stack pointer is decremented
by two and stored the IP contents on stack top.
When the procedure is completed, the control is again transferred to the main program by
executing the RET instruction at the end of procedure and by restoring saved CS and IP from
the stack.
RET no operands Return
This is the last instruction of a procedure. When microprocessor executes this instruction,
transfer the control from the subroutine to the main program, in doing so it popped the
returning address from the top of the stack. A near return is specified by the RETN and far
return is specified by RETF. A near return works by popping a word into IP. A far return works
by popping a word into IP and then popping a word into CS.
IRET no operands Interrupt return
The IRET (Return from Interrupt Service Routine) transferred the control from an interrupt
procedure to the main program. The IRET instruction pops IP, CS, and the flags (in that order)
and resumes execution.
INTn Interrupt
The INTn generates the software interrupts. Here in this instruction the subscript n may be
from 0 to 255 and is called type of interrupt. When microprocessor executes the software
interrupt INTn, the control is transferred to a predefined memory location called the vectored
location. From this vectored location, the address of the ISR is fetched by the microprocessor
and then the control is transferred to that ISR. When an interrupt is called, the flags CS and
IP are pushed onto the stack (in that order) and the trap and interrupt flags are cleared.
To return from an interrupt, use the IRET instruction.
INTO no operands Interrupt on overflow
Interrupt of overflow flag is 1. The control is transferred to the ISR if the overflow flag is set
after an arithmetic instruction. If overflow is not set, then the ISR will not be called.
 Instructions Set of 8086 117
JMP Jump unconditionally
Operands label
4-byte address
This is an unconditional jump instruction. By this instruction, the control is transferred
from one memory location to another location within the program. The 4-byte address specified
as 234h:5678H. Here the first value denotes the segment and the second value shows the
offset.
The jump instruction may be conditional also. There are 30 conditional jump instructions.
In these instructions the control will be transferred to the label or 4-byte address only when
the condition is true. The condition may be logical condition or may be arithmetical condition.
The arithmetical condition may further be either signed or unsigned. Table 4.10 shows the
interpretation of these conditional jumps.

Table 4.10 Interpretation of conditional jumps

Mnemonic Condition tested “Jump it...”
JA/JNBE (CF or ZF) = 0 above/not below nor equal
JAE/JNB CF = 0 above or equal/not below
JB/JNAE CF = 1 below/not above nor equal
JBE/JNA (CF or ZF) = 1 below or equal/not above
JC CF = 1 carry
JE/JZ ZF = 1 equal/zero
JG/JNLE ((SF XOR OF) or ZF) = 0 greater/not less nor equal
JGE/JNL (SF XOR OF) = 0 greater or equal/not less
JL/JNGE (SF XOR OF) = 1 less/not greater nor equal
JLE/JNG ((SF XOR OF) or ZF) = 1 less or equal/not greater
JNC CF = 0 not carry
JNE/JNZ ZF = 0 not equal/not zero
JNO OF = 0 not overflow
JNP/JPO PF = 0 not parity/parity odd
JNS SF = 0 not sign
JO OF = 1 overflow
JP/JPE PF = 1 parity/parity equal
JS SF = 1 sign
Note: “above” and “below” refer to the relationship of two unsigned values; “greater” and
“less” refer to the relationship of two signed values.

The different conditional jump instructions are:

(i) JAE label: Short jump if first operand is above or equal to second operand (as set by
CMP instruction). It is unsigned jump operation.
Algorithm:
if CF = 0, then jump
(ii) JB label: Short jump if first operand is below second operand (as set by CMP instruction).
It is unsigned jump operation.
118 Microprocessor 8086—Architecture, Programming and Interfacing

Algorithm:
if CF = 1, then jump
(iii) JBE label: Short jump if first operand is below or equal to second operand (as set by
CMP instruction). It is unsigned jump operation.
Algorithm:
if CF = 1 or ZF = 1, then jump
(iv) JC label: Short jump if carry flag is set to 1.
Algorithm:
if CF = 1, then jump
(v) JCXZ label: Short jump if CX register is 0.
Algorithm:
if CX = 0, then jump
(vi) JE label: Short jump if first operand is equal to second operand (as set by CMP
instruction). It may be a signed or an unsigned jump operation.
Algorithm:
if ZF = 1, then jump
(vii) JG label: Short jump if first operand is greater than second operand (as set by CMP
instruction). It is a signed operation.
Algorithm:
if (ZF = 0) and (SF = OF), then jump
(viii) JGE label: Short jump if first operand is greater than or equal to second operand
(as set by CMP instruction). It is signed jump operation.
Algorithm:
if SF = OF, then jump
(ix) JL label: Short jump if first operand is less than second operand (as set by CMP
instruction). It is signed jump operation.
Algorithm:
if SF Å OF = 1, then jump
(x) JLE label: Short jump if first operand is less than or equal to second operand (as set
by CMP instruction). It is signed jump operation.
Algorithm:
if ((SF Å OF) + ZF) = 1, then jump
(xi) JNA label: Short jump if first operand is not above second operand (as set by CMP
instruction). It is unsigned jump operation.
Algorithm:
if CF = 1 or ZF = 1, then jump
(xii) JNAE label: Short jump if first operand is not above and not equal to second operand
(as set by CMP instruction). It is an unsigned operation.
Algorithm:
if CF = 1, then jump
(xiii) JNB label: Short jump if first operand is not below second operand (as set by CMP
instruction). It is unsigned jump operation.
Algorithm:
if CF = 0, then jump
 Instructions Set of 8086 119
(xiv) JNBE label: Short jump if first operand is not below and not equal to second operand
(as set by CMP instruction). It is unsigned jump operation.
Algorithm:
if (CF = 0) and (ZF = 0), then jump
(xv) JNC label: Short jump if carry flag is set to 0.
Algorithm:
if CF = 0, then jump
(xvi) JNE label: Short jump if first operand is not equal to second operand (as set by CMP
instruction). It may be a signed or an unsigned jump operation.
Algorithm:
if ZF = 0, then jump
(xvii) JNG label: Short jump if first operand is not greater than second operand (as set by
CMP instruction). It is a signed jump operation.
Algorithm:
if ((SF Å OF) + ZF) = 1, then jump
(xviii) JNGE label: Short jump if first operand is not greater than and not equal to second
operand (as set by CMP instruction). It is a signed jump operation.
Algorithm:
if SF Å OF = 1, then jump
(xix) JNL label: Short jump if first operand is not less than second operand (as set by CMP
instruction). It is a signed jump operation.
Algorithm:
if SF = OF, then jump
(xx) JNLE label: Short jump if first operand is not less than and not equal to second
operand (as set by CMP instruction). It is a signed jump operation.
Algorithm:
if (SF = OF) and (ZF = 0), then jump
(xxi) JNO label: Short jump if not overflow.
Algorithm:
if OF = 0, then jump
(xxii) JNP label: Short jump if no parity (odd). only 8 low bits of result are checked. Set
by CMP, SUB, ADD, TEST, AND, OR, XOR instructions.
Algorithm:
if PF = 0, then jump
(xxiii) JNS label: Short jump if not signed (if positive). Set by CMP, SUB, ADD, TEST,
AND, OR, XOR instructions.
Algorithm:
if SF = 0, then jump
(xxiv) JNZ label: Short jump if not zero (not equal). Set by CMP, SUB, ADD, TEST,
AND, OR, XOR instructions.
Algorithm:
if ZF = 0, then jump
120 Microprocessor 8086—Architecture, Programming and Interfacing

(xxv) JO label: Short jump if overflow.

Algorithm:
if OF = 1, then jump
(xxvi) JP label: Short jump if parity (even). Only 8 low bits of result are checked. Set by
CMP, SUB, ADD, TEST, AND, OR, XOR instructions.
Algorithm:
if PF = 1, then jump
(xxvii) JPE label: Short jump if parity even. Only 8 low bits of result are checked. Set by
CMP, SUB, ADD, TEST, AND, OR, XOR instructions.
Algorithm:
if PF = 1, then jump
(xxviii) JPO label: Short jump if parity odd. Only 8 low bits of result are checked. Set by
CMP, SUB, ADD, TEST, AND, OR, XOR instructions.
Algorithm:
if PF = 0, then jump
(xxix) JS label: Short jump if signed (if negative). Set by CMP, SUB, ADD, TEST, AND,
OR, XOR instructions.
Algorithm:
if SF = 1, then jump
(xxx) JZ label: Short jump if zero (equal). Set by CMP, SUB, ADD, TEST, AND, OR,
XOR instructions.
Algorithm:
if ZF = 1, then jump
LOOP label LOOP unconditionally
Loop instruction is used to create a loop from the Loop instruction to a specified label. Loop
decrements CX without changing any flags and if the result is not 0, transfers execution to
the address specified by the operand. If CX is 0 after being decremented, execution continues
at the next instruction. The operand must specify a short label (between –128 and 127 bytes
from the instruction following the LOOP instruction).
LOOP conditional
Conditional Loop instruction is used to create a loop from the Loop instruction to a specified
label if condition is met and if CX is not 0. The instruction decrements CX without changing
any flags and tests to see if the zero flag was set by a previous instruction (such as CMP).
With LOOPE and LOOPZ, execution is transferred to the label if the zero flag is set and CX
is not 0. With LOOPNE and LOOPNZ, execution is transferred to the label if the zero flag
is cleared and CX is not 0. Execution continues at the next instruction if the condition is not
met. Before entering the loop, CX should be set to the maximum number of repetitions desired.
(i) LOOPE label: LOOP if equal decrease CX, jump to label if CX not zero and equal
(ZF = 1).
(ii) LOOPNE label: LOOP if not equal decrease CX, jump to label if CX not zero and
not equal (ZF = 0).
 Instructions Set of 8086 121
(iii) LOOPNZ label: LOOP if not zero decrease CX, jump to label if CX not zero and
ZF = 0.
(iv) LOOPZ label: LOOP if zero decrease CX, jump to label if CX not zero and ZF = 1.

4.5.9 Processor-control Instructions

This group of instructions (except for NOP) generally deals with interactions in multiprocessor
situations.
NOP No operation
No operation
This instruction performs no operation. NOP can be used for timing delays or alignment.
ESC Escape
There are certain instructions in the 8086 assembly language which are designed only for
coprocessor. These instructions are called ESCAPE instructions. In these ESCAPE instructions
the MSB 5-bits of the opcode is always 110011. This instruction allows a memory or register
operand to be used by a coprocessor instruction. This instruction is explained in detail in
Chapter 8.
WAIT Wait
The WAIT instruction suspends the microprocessor execution and the processor enters into the
wait state. The processor will remain in wait state until a signal (TEST –) is received which
indicates that the coprocessor has finished a simultaneous operation. This instruction is used
when the microprocessor is used in maximum mode configuration and specifically when a
math coprocessor is present in the multiprocessing environment system. This instruction prevents
the math coprocessor instruction from modifying a memory location that is being modified at
the same time by a processor instruction. FWAIT is an equivalent instruction in the math
coprocessor’s instruction set.
LOCK Lock
This instruction prevents the other processor from acquiring the buses during the execution of
an instruction. This instruction is used as a prefix. For example, suppose the microprocessor
is executing the instruction MOV AX, 1000H, and in the mean time the DMA controller sends
a request for the buses, then the microprocessor is forced to suspend the execution of the
MOV instruction and releases the buses for the DMA controller. But if the MOV instruction
is prefixed with the LOCK instruction like LOCK MOV AX, 1000H, then the processor will
not release the buses till the MOV instruction is complete. The processor will release the buses
after the execution of this instruction and before the execution of the next instruction.
The LOCK prefix will activate the LOCK – pin of the microprocessor.
HLT Halt
This instruction stops the execution of the microprocessor and force the processor to enter into
the wait state. The processor comes out of this wait state only when an interrupt restarts
execution at the instruction following HLT or by the external RESET signal.
122 Microprocessor 8086—Architecture, Programming and Interfacing

Instruction Set Summary

Mnemonic and Description Instruction Code

DATA TRANSFER
MOV = Move:
Register/Memory to/from Register

Immediate to Register/Memory

Immediate to Register

Memory to Accumulator

Accumulator to Memory

Register/Memory to Segment Register

Segment register to register/memory

PUSH = Push:
Register/Memory

Register

Segment Register
POP = Pop:
Register/Memory

Register

Segment Register
XCHG = Exchange:
Register/Memory with Register

Register with Accumulator

IN = Input from:
Fixed Port

Variable Port
OUT = Output to:
Fixed Port

Variable Port

XLAT = Translate Byte to AL

 Instructions Set of 8086 123

Mnemonic and Description Instruction Code

LEA = Load EA to Register

LDS = Load Pointer to DS

LES = Load Pointer to ES

LAHF = Load AH with Flags

SAHF = Store AH into Flags

PUSHF = Push Flags

POPF = Pop Flags

ARITHMETIC
ADD = Add:
Reg./Memory with Register to Either

Immediate to Register/Memory

Immediate to Accumulator
ADC = Add with Carry:
Reg./Memory with Register to Either

Immediate to Register/Memory

Immediate to Accumulator
INC = Increment:
Register/Memory

Register
SUB = Subtract:
Reg./Memory and Register to Either

Immediate from Register/Memory

Immediate from Accumulator

SSB = Subtract with Borrow:
Reg./Memory and Register to Either

Immediate from Register/Memory

Immediate from Accumulator

124 Microprocessor 8086—Architecture, Programming and Interfacing

Mnemonic and Description Instruction Code

DEC = Decrement:
Register/Memory

Register

NEG = Change Sign

CMP = Compare:
Register/Memory and Register

Immediate with Register/Memory

Immediate with Accumulator

MUL = Multiply (Unsigned)

IMUL = Integer Multiply (Signed)

DlV = Divide (Unsigned)

IDlV = Integer Divide (Signed)

CBW = Convert Byte to Word

CWD = Convert Word to Double Word

DATA ADJUSTMENT
AAA = ASCII Adjust for Add

DAA = Decimal Adjust for Add

AAS = ASCII Adjust for Subtract

DAS = Decimal Adjust for Subtract

AAM = ASCII Adjust for Multiply

AAD = ASCII Adjust for Divide

ROTATE AND SHIFT
SHL/SAL = Shift Logical/Arithmetic Left

SHR = Shift Logical Right

SAR = Shift Arithmetic Right

ROL = Rotate left

ROR = Rotate right

 Instructions Set of 8086 125

Mnemonic and Description Instruction Code

RCL = Rotate Through Carry Flag Left

RCR = Rotate Through Carry Right

LOGIC

NOT = Invert
AND = And:
Reg./Memory and Register to Either

Immediate to Register/Memory

Immediate to Accumulator
OR = Or:
Reg./Memory and Register to Either

Immediate to Register/Memory

Immediate to Accumulator
XOR = Exclusive or
Reg./Memory and Register to Either

Immediate to Register/Memory

Immediate to Accumulator
TEST = And Function to Flags,
No Result:
Register/Memory and Register

Immediate Data and Register/Memory

Immediate Data and Accumulator

STRING MANIPULATION
REP = Repeat

MOVS = Move Byte/Word

CMPS = Compare Byte/Word

SCAS = Scan Byte/Word

LODS = Load Byte/Wd to AL/AX

STOS = Stor Byte/Wd from AL/A

126 Microprocessor 8086—Architecture, Programming and Interfacing

Mnemonic and Description Instruction Code

CONTROL TRANSFER
CALL = Call:
Direct within Segment

Indirect within Segment

Direct Intersegment

Indirect intersegment
JMP = Unconditional jump:
Direct within Segment

Direct within Segment-short

Indirect within Segment

Direct Intersegment

Indirect Intersegment
RET = Return from CALL:
Within Segment

Within Segment Adding Immediate to SP

Intersegment

Intersegment Adding Immediate to SP

JE/JZ = Jump on Equal/Zero

JL/JNGE = Jump on Less/Not Greater or Equal

JLE/JNG = Jump on Less or Equal/Not Greater

JB/JNAE = Jump on Below/Not Above or Equal

JBE/JNA = Jump on Below or Equal/Not Above

JP/JPE = Jump on Parity/Parity Even

JO = Jump on Overflow

JS = Jump on Sign

JNE/JNZ = Jump on Not Equal/Not Zero

 Instructions Set of 8086 127

Mnemonic and Description Instruction Code

JNL/JGE = Jump on Not Less/Greater or Equal

JNLE/JG = Jump on Not Less or Equal/Greater

JNB/JAE = Jump on Not Below/Above or Equal

JNBE/JA = Jump on Not Below or Equal/Above

JNP/JPO = Jump on Not Par/Par Odd

JNO = Jump on Not Overflow

JNS = Jump on Not Sign

LOOP = Loop CX Times

LOOPZ/LOOPE = Loop While Zero/Equal

LOOPNZ/LOOPNE = Loop While Not Zero/Equal

JCXZ = Jump on CX Zero

INT = Interrupt

Type Specified

Type 3

INTO = Interrupt on Overflow

IRET = Interrupt Return

FLAG RELATED INSTRUCTION
CLC = Clear Carry

CMC = Complement Carry

STC = Set Carry

CLD = Clear Direction

STD = Set Direction

CLl = Clear Interrupt

STI = Set interrupt

PROCESSOR CONTROL
HLT = Halt

WAIT = Wait
128 Microprocessor 8086—Architecture, Programming and Interfacing

Mnemonic and Description Instruction Code

ESC = Escape (to External Device)

LOCK = Bus Lock Prefix

EXERCISES

Multiple Choice Questions

1. The effect of the following instructions
MOV AH, 2H
INT 21H
is to
(a) Read a character into AL (b) Read a character into DL
(c) Display the character in AL (d) Display the character in DL.
2. The effect of the following instructions
MOV AH, 1H
INT 21H
is to
(a) Read a character into AL (b) Read a character into DL
(c) Display the character in AL (d) Display the character in DL.
3. Given that AL contains the ASCII code of an uppercase letter, it can be converted to
lowercase by
(a) ADD AL, 32 (b) SUB AL, 32
(c) OR AL, 1101 1111 (d) AND AL, 0010 0000.
4. Given that AL contains the ASCII code of a lowercase letter, it can be converted to
uppercase by
(a) ADD AL, 32 (b) SUB AL, 32
(c) OR AL, 1101 1111 (d) AND AL, 0010 0000.
5. The instruction JG operates with
(a) Unsigned numbers (b) 2’s complement numbers
(c) Floating point numbers (d) ASCII codes.
6. The instruction JA operates with
(a) Unsigned numbers (b) Signed numbers
(c) Floating point numbers (d) ASCII codes.
7. The instruction MOV STR[SI], ‘a’ is an example of
(a) Indirect addressing (b) Indexed addressing
(c) Direct addressing (d) Register addressing.
8. The instruction MOV AX, [BX] is an example of
(a) Indirect addressing (b) Indexed addressing
(c) Direct addressing (d) Based addressing.
 Instructions Set of 8086 129
9. The instruction JE label is an example of
(a) Indirect addressing (b) Indexed addressing
(c) Relative addressing (d) Immediate addressing.
10. Which of the following is an illegal 8086 instruction?
(a) IRET (b) PUSH AX
(c) ADD BX, 25000H (d) MOV X, AY.
11. The call instruction stores the return address for a subprogram
(a) On the stack (b) In the memory address register
(c) In the program counter (d) Does not involve using the return address.
12. The instruction JE label is an example of
(a) Indirect addressing (b) Indexed addressing
(c) Relative addressing (d) Immediate addressing.
13. The CMP instruction modifies the
(a) Program counter (b) Instruction register
(c) Flags register (d) Segment register.
14. Conditional instructions typically inspect the
(a) Program counter (b) Instruction register
(c) Flags register (d) Accumulator.
15. The BP register is typically used for accessing
(a) Strings (b) Memory
(c) Stack (d) Data segment.
16. The RET instruction modifies the
(a) Instruction register (b) Program counter
(c) Address register (d) Flags register.
17. The CALL instruction modifies
(a) The flags register (b) Program counter
(c) BP register (d) None of the above.
18. The IRET instruction modifies
(a) The flags register (b) Stack pointer
(c) BP register (d) None of the above.
19. The instruction INC I where I is a memory variable involves
(a) A memory read operation
(b) A memory write operation
(c) A memory read and a memory write operation
(d) Only an arithmetic operation.
20. The result of MOV AL, 65 is to store
(a) 0100 0010 in AL (b) ASCII code of ‘A’ in AL
(c) Store 42H in AL (d) Store 1000 0001 in AL.
21. The call instruction is used to
(a) Access subprograms (b) Access memory
(c) Perform I/O (d) Access the stack.
130 Microprocessor 8086—Architecture, Programming and Interfacing

22. To copy the hexadecimal number from A to BH register, you write

(a) MOV 0BH, AH (b) MOV BH, 0AH
(c) MOV BH, AH (d) MOV BH, [AH].
23. Which of the following is an illegal instruction?
(a) MOV AX, 30000 (b) INC AL
(c) AND BX, BX (d) ADD AX 30.
24. Given that the BL register contains 1111 0000, the effect of the following instruction or
BL, 0000 1111 is to
(a) Clear BL (b) Store 1111 1111 in BL
(c) Store 0000 1111 in BL (d) Leave BL unchanged.
25. Which of the following is an illegal 8086 instruction?
(a) MOV 20, BX (b) INC AL
(c) AND BX, BX (d) ADD AX, 30.
26. Which of the following is an illegal 8086 instruction?
(a) MOV AX, [BX] (b) INC [BX]
(c) ADD BX, [BX] (d) ADD AX, [CX].
27. Which of the following is an illegal 8086 instruction?
(a) MOV AX, [BX] (b) INC [BX]
(c) ADD BX, [DX] (d) ADD [BX], 1.
28. Which of the following is an illegal 8086 instruction?
(a) RET 2 (b) PUSH AL
(c) ADD BX, 2500 (d) AND AX, DX.
29. An assembly language instruction
(a) Always has a label (b) Always takes at least 1 operand
(c) Always has an operation field (d) Always modifies the status register.
30. An arithmetic instruction always modifies the
(a) Stack pointer (b) Status register
(c) Program counter (d) An index register.
31. A conditional jump instruction
(a) Always causes a transfer of control
(b) Always involves the use of the status register
(c) Always modifies the program counter
(d) Always involves testing the Zero flag.
32. An interrupt instruction
(a) Causes an unconditional transfer of control
(b) Causes a conditional transfer of control
(c) Modifies the status register
(d) Is an I/O instruction.
33. A data movement instruction will
(a) Modify the status register (b) Modify the stack pointer
(c) Modify the program counter (d) Transfer data from one location to another.
 Instructions Set of 8086 131
34. Programs are written in assembly language because they
(a) Run faster than High-level language
(b) Are portable
(c) Easier to write than machine code programs
(d) They allow the programmer access to register or instructions that are not usually
provided by a High-level language.
35. The result of MOV AL, 65 is to store
(a) 0100 0010 in AL (b) 42H in AL
(c) 40H in AL (d) 0100 0001 in AL.
36. Which group of instructions do not affect the flags?
(a) Arithmetic operations (b) Logic operations
(c) Data transfer operations (d) Branch operations.
37. The conditional branch instruction JNS performs the operations when
(a) ZF = 0 (b) SF = 0
(c) PF = 0 (d) CF = 0.
38. IDIV and DIV instructions perform the same operations for
(a) Unsigned number (b) Signed number
(c) Signed number and unsigned number (d) None of above.
39. What is the output of the following code?
AL = –28 decimal, BL = 59 decimal
IMUL BL
AX = ?, MSB = ?
(a) AX = F98CH, MSB = 1 (b) AX = 1652, MSB = 1
(c) BX F9C8H, MSB = 1 (d) BX = 1652, MSB = 1.
40. What is the output of the following code?
CF = 0, BH = 179
RCL BH, 1
(a) CF = 0, OF = 1, BH = 01100101 (b) CF = 1, OF = 1, BH = 01100110
(c) CF = 1, OF = 0, BH = 01001101 (d) CF = 0, OF = 0, BH = 00101100.
41. What is the output of the following code?
SI = 10010011 10101101, CF = 0
SHR SI, 1
(a) 37805, CF = 1, OF = 1 (b) 18902, CF = 1, OF = 1
(c) 19820, CF = 1, OF = 1 (d) 53708, CF = 1, OF = 1.
42. What is the output of the following code?
BX = 23763 CL = 8
ROL BX, CL
(a) 0101110011010011, CF = 0 (b) 1101001101011100, CF = 0
(c) 0110100010011101, CF = 1 (d) 1011100110001100, CF = 1.
132 Microprocessor 8086—Architecture, Programming and Interfacing

43. What is the output of the following code?

PUSH AL
(a) Decrement SP by 2 and push a word to stack
(b) Increment SP by 2 and push a word to stack
(c) Decrement SP by 2 and push AL to stack
(d) Illegal.
44. What is the output of the following code?
AX = 37D7H, BH = 151 decimal
DIV BH
(a) AL = 65H, AH = 94 decimal
(b) AL = 5EH, AH = 101 decimal
(c) AH = E5H, AL = 5EH
(d) AL = 56H, AH = 5EH.
45. In 8086 microprocessor; which one of the following instructions is executed before an
arithmetic operation?
(a) AAM (b) AAD
(c) DAS. (d) DAA.
46. The number of address mode provided in 8086 is
(a) 4 (b) 5
(c) 6 (d) 7.
47. Indexed address mode should not belong to which of the register?
(a) Base pointer (b) Sources index
(c) Destination register (d) Stack register.
48. The following instruction given below is related to which of address mode
MOV AL, DIS(BX) (SI)?
(a) Base indexed displacement address mode
(b) Based indexed address address mode
(c) Indexed address mode
(d) Register indirect address mode.
49. 8086 provides how many ways to access memory?
(a) 10 (b) 15
(c) 16 (d) 17.
50. Which of the following is string related opcode in 8086?
(a) MOV (b) MOV B
(c) CALL RET (d) JC.
51. Which of the following instruction is register indirect address mode?
(a) MOV AX, BX (b) MOV CH, 3AH
(c) MOV (1234), AX (d) MOV (BX), CL.
52. Which of the following is the register related address mode?
(a) MOV (BX + SI), BP (b) MOVCL, (B X + 4)
(c) MOV ARRAY (BX + SI), DX (d) MOV CH, 3AH.
 Instructions Set of 8086 133
53. Which of the following is the direct address mode?
(a) MOV AX, CX (b) MOV CH, 3AH
(c) MOV (1234), AX (d) MOV (BX), CL.
54. Which of the following is an immediate address mode?
(a) MOV AX, CX (b) MOV CH, 3AH
(c) MOV (1234) (d) MOV (BX), CL.
55. Which of the following is the register address mode?
(a) MOV AX, CX (b) MOV CH, 3AH
(c) MOV (1234) (d) MOV (BX), CL.
56. A segment register can be explicitly specified in the
(a) MOV (b) PUSH
(c) POP (d) All of the above.
57. Which one of the following registers can’t be specified as an operand?
(a) SI (b) DI
(c) IP (d) None of the above.
58. Immediate data can’t be used as an operand in which one of the following instructions?
(a) MOV DST, SRC (b) ADD DST, SRC
(c) CMP OPR1, OPR2 (d) XCHG OPR1, OPR2.
59. Which one of the flag bits is modified after executing the XCHG OPR1,OPR2?
(a) Overflow flag (OF) (b) Trap flag (TF)
(c) Direction flag (DF) (d) None of the above.
60. Which one of the following operations cannot be performed on packed BCD numbers?
(a) Subtraction (b) Addition
(c) Multiplication (d) None of the above.
61. Which of the following instructions are used for packed BCD adjust instructions?
(a) DAA (b) DAS
(c) Both (a) and (b) (d) None of the above.
62. Which one of the following instructions is present in 8086?
(a) LAHF (b) LALF
(c) LAXF (d) None of the above.
63. Which one of the following logical instructions don’t effect any flag bit?
(a) OR DST, SRC (b) AND DST, SRC
(c) NOT OPR (d) XOR DST, SRC.
64. If DIV BX instruction is executed, then where will be the quotient and remainder will be
stored?
(a) AX and BX (b) BX and AX
(c) AX and DX (d) DX and AX.
65. Which one of the following flag bit is modified after executing XLAT OPR instruction.
(a) Trap flag (TF) (b) Sign flag (SF)
(c) Parity flag (PF) (d) None of the above.
134 Microprocessor 8086—Architecture, Programming and Interfacing

66. Shift instructions are

(a) Data manipulation instructions (b) Data transfer instructions
(c) Program control instructions (d) All of the above.
67. What is the status of the Auxiliary carry (AC) flag bit after executing the SHR mem/reg,
count instruction?
(a) set(=1) (b) reset(=0)
(c) Tristated (d) Undefined.
68. What is the status of the Overflow Flag (OF) and Carry Flag (CF) bit after executing the
OR mem/reg, data instruction?
(a) set(=1) (b) reset(=0)
(c) Tristated (d) Undefined.
69. What is the status of the flag register after executing the IRET instruction?
(a) set(= 1) (b) reset(=0)
(c) Tristated (d) Undefined.

Descriptive Questions
1. What is an instruction? Explain various instruction formats with examples.
2. Explain different addressing modes of 8086 with examples.
3. Explain the following instruction formats with examples.
(a) One-byte instruction, register mode.
(b) Register to/from memory with no displacement.
4. Explain the various addressing modes used in 8086.
5. Explain the different types of Instruction Formats used in 8086.
6. Explain in detail the coding template for MOV instruction of 8086.
7. Construct the binary code for the MOV BX, 59H [DI] instruction.
8. Given that: BX = 637D, SI = 2A9B, Displacement = C237.
Determine the effective address (if applicable) resulting from these registers and the
addressing mode:
(a) Immediate
(b) Direct
(c) Register using BX
(d) Based indexed
9. Given that BX = 637D, SI = 2A9B, Displacement = 237. Determine the effective resulting
from these registers and the addressing mode.
(a) Immediate (b) Direct
(c) Register indirect using BX (d) Relative base indexed
(e) Base indexed (f) Register relative using BX.
10. For the following instructions, indicate the addressing modes type and the physical address
of the source operand, if CS = 2000H, DS = 543AH, SS = 9AC5H, SI = 3200H,
DI = 2ABCH, BX = 3F00H, BP = 329AH
 Instructions Set of 8086 135
(a) ADD BL, [SI+10H] (b) MOV AX, [BX][DI–01H]
(c) MOV AX, [BP–100H].
11. What do you mean by segment override prefix?
12. At a particular instant, the data in certain registers of the 8086 are given below:
AX = 1234H; BX = 3456H; CX = 10 H; SI = 5678H; DI = ABEFH;
BP = CDEFH; CS = 9087H; DS = 9035H; ES = 6798H; SS = 9097H.
13. If now the instruction MOVSB is executed by the processor, state clearly what happens
in the memory? Also indicate what data are left in the above registers? Assume that D flag
is set.
14. Write different groups of 8086 instruction giving two examples.
15. What is the advantage of LOOP instruction? Where is it used? Explain different LOOP
instructions in 8086 microprocessor.
16. With the help of examples, illustrate the use and the meaning of the following instructions:
AAA, XLAT, WAIT.
17. Write instructions to:
(a) Load 26 (decimal) into register cx (b) Copy contents of ax to bx and dx
18. What errors are present in the following:
(a) MOV AX 3D (b) MOV 23, AX
(c) MOV CX, CH (d) MOVE AX, 1H
(e) ADD 2, CX (f) ADD 3, 6
(g) INC AX, 2.
19. Find the syntax errors in the following instructions:
(a) MOV BH, AX (b) MOV 7632H, CX
(c) MOV DX,CL (d) IN BL, 04H
(e) ADD AL, 2073H.
20. Explain string instructions supported by 8086 processor.
21. Explain the fixed part and variable part formats of IN and OUT instructions with examples.
22. Explain the following 8086 instructions
(a) XLAT (b) IMUL
(c) SHR (d) LOOP.
23. What is a stack? Explain 8086 instructions for pushing and popping data on stack.
24. How are the procedures CALL and RET take place in 8086 programming?
25. Describe the difference between the instructions MOV AX, 2347H and MOV AX, [2347H].
26. What is the difference between
(a) Near and far procedure (b) RET and IRET
(c) MUL and IMUL (d) DIV and IDIV
(e) Shifts and rotate instructions (f) RCL and RCR instructions.
27. Write 8086 assembly instruction which will perform the following operations:
(a) Multiply AL times BL
(b) Load the number F3H into AL register
136 Microprocessor 8086—Architecture, Programming and Interfacing

(c) Copies BP register contents to SP register

(d) Divide the AL register contents by 2 using a shift instruction
(e) Multiply the AL register contents by 4 using a shift instruction
28. Write and explain instruction template for MOV instruction. The opcode for MOV is
100010, generate opcode for the following instructions:
(a) MOV CL, [BX] (b) MOV CS: [BX], DL
(c) MOV 43H [SI], DH (d) MOV CX, [437A]H.
29. How could you use the TEST instruction (or a sequence of TEST instructions) to see if
bits zero and four in the AL register are both set to one? How would the TEST instruction
be used to see if either bit is set? How could the TEST instruction be used to see if neither
bit is set?
30. State any four addressing modes used in 8086 microprocessor. Identify addressing modes
used in each of the following 8086 instructions.
(a) MOV BX, 0354H (b) ADD AL, [BX + 04]
(c) MOV AX, [BX + SI] (d) MOV AX, [BX + SI + 04].
31. What is wrong with the instruction IN AX, 2500H?
32. Find and explain error if there are array in the following instructions:
(a) MOV AL, CX (b) MOV BL, CX
(c) MOV Arr1 [S1], Arr2 [d1] (d) IN 82H, AL.
(e) XCHG AL, BL.
33. Explain the difference between NEAR and FAR procedure of 8086 processor.
34. Explain REP MOVSB instruction with an example.
35. Explain the following instructions with an example:
(a) DAA (b) AAM
(c) LOOP (d) SUB
(e) XLAT.
36. Briefly explain about the following instructions.
(a) ADD (b) NEG
(c) AAM (d) DIV.
37. Explain the use of the following instructions:
(a) XLAT (b) DAA
(c) CMPSB.
38. Differentiate between CALL and JMP instructions of 8086 microprocessor.
39. What is the difference between RET and IRET? Discuss the result, if RET instruction is
placed at the end of the interrupt service routine.
40. Write notes on the following:
(a) RCL (b) SHR
(c) JAE (d) LOOP.
41. What single 8086 instruction is equivalent to the following four instructions?
(a) PUSH BX (b) PUSH AX
(c) POP BX (d) POP AX.