Innovative  Entrepreneurial  Global

CHAPTER 3: 
MULTISTAGE AMPLIFIERS

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Multistage Amplifiers

 The output of one amplifier is the input to the next 
amplifier.
 The overall voltage gain is determined by the product of 
gains of the individual stages.
 The DC bias circuits are isolated from each other by the 
coupling capacitors.
 The DC calculations are independent of the cascading.
 The AC calculations for gain and impedance are 
interdependent.

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A1 = (36 mV)/(900 mV) = 40
A2 = (1.25 V)/(36 mV) = 34.722
A3 = (21 V)/(1.25 V) = 16.8

v3/v1 = A1 A2 A3 = (40)(34.722)(16.8) = 23,333

or
v3/v1 = (21 V)/( 900 mV) = 23,333

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 Coupling The Multistage Amplifiers

 There are two techniques used to couple or connect the 
output of one stage to the input of the next stage.  They are:

(i)  Capacitor or R‐C coupling

(ii) Direct coupling

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R‐C Coupled BJT Amplifiers

RL

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 RL

Input impedance, first stage:

Voltage gain:
Z i  R BB1 r  A V1   g m1 Z O1 Z i2 
Output impedance, second stage: A V2   g m2 Z O R L 
Z o  R C2 A V  A V1  A V2

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Direct Coupled BJT Amplifiers

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  g m1 Z O1 Z i2 
Input impedance, first stage: Voltage gain: A V1 
1  g m1R E1
Z i  R BB1 rπ  (1  β 1 )R E1   g m2 Z O R L 
A V2 
1  g m2 R E2
Ouput impedance, second stage: A V  A V1  A V2
Z o  R C2

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Cascode Connection
 This example is a CE–CB combination. This arrangement 
provides high input impedance but a low voltage gain.
 The low voltage gain of the input stage reduces the 
Miller input capacitance, making this combination 
suitable for high‐frequency applications.
1
C Mi  C bc (1  A V ) fHi 
2 π R THi C i

If AV approach unity, CMi

RC
will be minimum.
Therefore Ci=CMi+Cbe+Cwi
will also be minimum.
Thus fHi will increase.

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Voltage gain: A V1   g m1 R C1 //Z i2 
A V2  g m2 R C2
A V  A V1  A V2

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 chapter 3: (continue)
Amplifier Frequency Response

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Frequency Response
 When multi‐stages amplifier were used, the amplifier’s 
frequency response will be affected.
 If the low cut‐off frequency of each stage is unequal, the 
highest value will be choosen as the dominant 
frequency, fL(overall).
 For high cut‐off frequency, the lowest value will be 
choosen as the dominant frequency, fH(overall).
 But if each stage has equal fL and fH, the following 
expressions can be used:
fL
fL(overall) 
1
2 -1
n
n ≡ no of stages
1 fL ≡ dominant low cut-off freq. of each stage.
fH(overall)  fH 2 - 1 n fH ≡ dominant high cut-off freq. of each stage.

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Low Frequency Analysis

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fL due to C1:

1
f LC1 
2 πR S  Zi C1 R B rπ 1

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fL due to C2:

1
fLC2 
2πZ O  RL C2
Z O R C

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fL due to CB:

1
f LCB 
2 πR 1 R 2 C B

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High Frequency Analysis

CMi  Cbc1(1 A V1 )
 1   gm1 
CMo  Cbc11   CMi  Cbc11 
 A V1   gm2 
 r 2  g  gm2 
A V1  gm1     m1  CMo  Cbc11 
 1 β 2  gm2  gm1 

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 At input stage:

1
f Hi 
2 π R S Z i C be1  C Mi  Z i  R BB r π 1

At intermediate stage:

1
f Hint  rπ 2
2 πR Th (C mo  C be2 ) R Th 
1β 2

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At output stage:

1
fHo 
2πZ O RL Cbc2
Z O R C

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Example: Final Exam 2006/07 semester 2
Given the following transistors parameters:
BJT :   VBE = 0.7 V IC2 = 2 mAhfe =  = 200
E‐MOSFET :   k = 0.8 mA/V2 VT = VGS(Th) = 1 V
(a) Perform dc analysis to determine IDQ. 
(b) Draw the mid‐frequency ac equivalent circuit. 
(c) Calculate Ai = iL/ii  in dB and Zi2 for the amplifier system. 
(d) Determine the low cut‐off frequency produced by C2. 

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VBE 3  I E 3 R 3  V2  0
V2  VBE 3 15V  0.7 V
IE3    2.1 mA  I DQ
R3 6.8k

i L i L v  v O1 v gs
   
ii v  v O1 v gs ii
 A 
V 
V
 
 19.09  10 3  5.18  10 3  7.23 1  10 6  -714.95
A

 A i[ dB]  20 log10 714.95  57.09 dB 1
f 
2R 2  Zi 2 C 2
LC 2

Zi 2  R TH r  R 6 R L 1   1


 10k 2.6k  3.3k 10k 201 23.9k  9.8k 1F
 9.8 kΩ  11.6 Hz

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Darlington Pair Connection

 The Darlington circuit provides a very high current gain 
i.e.—the product of the individual  current gains:
βDP = β1+β2+β1β2 ≈ β1β2
 The practical significance is that the circuit provides a 
very high input impedance.
C

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 IC1  β1IB1
DC Analysis:
IE1  β1  1IB1
C IE1  IB2
IC = IC1 + IC2 IC2  β2IB2  β2 β1  1IB1
IC1 IC2
IB = IB1 IC  IC1  IC2
B  IB1β1  β2  β1β2 
 IB β1  β2  β1β2 
IE1 = IB2
IE IC
βDP 
IB
E
 β1  β2  β1β2
 β1β2

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 IC
gm(DP) 
2VT
r(DP)  r1  1 β1 r2
βDP βDP 2VT
r(DP)  @
gm(DP) IC

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Example

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 iL
vo Ai  where :
A VS  where : ii
vs
RC
v o  gmDP v πDP R C RL  iL   gmDP v πDP 
R C  RL
v πDP  v i v πDP  ibrπ DP 
Zi RBB
vi  vs ib  ii
Zi  RS RBB  rπ DP 

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.

Exercise
Given the following transistors parameters:
hFE1 = 60, hFE2 = 140, hfe1 = 40, hfe2 = 160 dan ro1 = ro2 = 
Determine:
(a) IE1, IE2 and IC
(b) Zi and Zo
+18v
(c) Gains AV and Ai R1
40k IC

C1
Q1

RS
Q2 C2
1k
R2 IE1
40k
RE RL
vS
750 2k

IE2

Zi ZO

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.

Exercise

For the circuit shown, determine: Q1 , Q2 :  = 100,

(a) IBQ1 for Q1 and VCEQ for Q2 VA = 
(b) VGSQ for Q3
(c) Draw the middle frequency ac equivalent circuit. Q3 : IDSS = 15 mA,
(d) Zi , ZO , Vo1/Es , Vo/Vo1 and iL/iS gm0 = 6 mS ,
(e) Draw an output waveform, Vo1 and Vo if Es = 10 sin t mV VDSQ = 9.7 V,
rd = 

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THE END

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