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Workshop Week 9.

This document discusses the properties of a direct-mapped cache with a 64-bit address. It asks the reader to determine the cache block size, number of blocks, and overhead ratio for the cache implementation. It then provides a series of byte-addressed cache references and asks the reader to identify each as a hit or miss, which bytes were replaced, the hit ratio, and the final cache state.

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Karen Diaz Ospino
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42 views1 page

Workshop Week 9.

This document discusses the properties of a direct-mapped cache with a 64-bit address. It asks the reader to determine the cache block size, number of blocks, and overhead ratio for the cache implementation. It then provides a series of byte-addressed cache references and asks the reader to identify each as a hit or miss, which bytes were replaced, the hit ratio, and the final cache state.

Uploaded by

Karen Diaz Ospino
Copyright
© © All Rights Reserved
We take content rights seriously. If you suspect this is your content, claim it here.
Available Formats
Download as PDF, TXT or read online on Scribd

Workshop Week 9.

For a direct-mapped cache design with a 64-bit address, the following bits of the address are
used to access the cache.

● What is the cache block size (in words)?


● How many blocks does the cache have?
● What is the ratio between total bits required for such a cache implementation over the
data storage bits?

Beginning from power on, the following byte-addressed cache references are recorded.

● For each reference, list (1) its tag, index, and offset, (2) whether it is a hit or a miss, and
(3) which bytes were replaced (if any).
● What is the hit ratio?
● List the final state of the cache, with each valid entry represented as a record of <index,
tag, data>. For example,

<0, 3, Mem[0xC00]-Mem[0xC1F]>

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