125 W Stereo Digital Amplifier Power Stage: Features Description

TM
TAS5352
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SLES204A – SEPTEMBER 2007 – REVISED OCTOBER 2007
125 W STEREO DIGITAL AMPLIFIER POWER STAGE

1FEATURES
• Total Power Output (Bridge Tied Load)
23
DESCRIPTION
– 2 × 125 W at 10% THD+N Into 4 Ω The TAS5352 is a high-performance, integrated
– 2 × 100 W at 10% THD+N Into 6 Ω stereo digital amplifier power stage designed to drive
a 4-Ω bridge-tied load (BTL) at up to 125 W per
• Total Power Output (Single Ended) channel with low harmonic distortion, low integrated
– 4 × 45 W at 10% THD+N Into 3 Ω noise, and low idle current.
– 4 × 35 W at 10% THD+N Into 4 Ω The TAS5352 has a complete protection system
• Total Power Output (Parallel Mode) integrated on-chip, safeguarding the device against a
– 1 × 250 W at 10% THD+N Into 2 Ω wide range of fault conditions that could damage the
system. These protection features are short-circuit
– 1 × 195 W at 10% THD+N Into 3 Ω protection, over-current protection, under voltage
• >110 dB SNR (A-Weighted With TAS5518 protection, over temperature protection, and a loss of
Modulator) PWM signal (PWM activity detector).
• <0.1% THD+N (1 W, 1 kHz) A power-on-reset (POR) circuit is used to eliminate
• Supports PWM Frame Rates of 192 kHz to power-supply sequencing that is required for most
432 kHz power-stage designs.
• Resistor-Programmable Current Limit BTL OUTPUT POWER
vs
• Integrated Self-Protection Circuitry, Including:
SUPPLY VOLTAGE
– Under Voltage Protection 150
– Overtemperature Warning and Error 140 TC = 75°C

130 THD+N at 10%
– Overload Protection
120
– Short-Circuit Protection
110
– PWM Activity Detector 4Ω
PO – Output Power – W
100
• Standalone Protection Recovery 90
• Power-On Reset (POR) to Eliminate System 80
Power-Supply Sequencing 70 6Ω
• High-Efficiency Power Stage (>90%) With 60
80-mΩ Output MOSFETs 50
• Thermally Enhanced 44-Pin HTSSOP Package 40
(DDV) 30
8Ω
• Error Reporting, 3.3-V and 5.0-V Compliant 20
• EMI Compliant When Used With 10
Recommended System Design 0

0 2 4 6 8 10 12 14 16 18 20 22 24 26 28 30 32 34
APPLICATIONS PVDD – Supply Voltage – V

• Mini/Micro Audio System
•
PurePath Digital™
DVD Receiver
• Home Theater
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
2 PurePath Digital, PowerPad are trademarks of Texas Instruments.
3 All other trademarks are the property of their respective owners.
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of the Texas Copyright © 2007, Texas Instruments Incorporated
Instruments standard warranty. Production processing does not
necessarily include testing of all parameters.
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These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam
during storage or handling to prevent electrostatic damage to the MOS gates.
GENERAL INFORMATION
Terminal Assignment
The TAS5352 is available in a thermally enhanced 44-pin HTSSOP PowerPad™ package (DDV)
This package contains a thermal pad that is located on the top side of the device for convenient thermal coupling
to the heatsink.
DDV PACKAGE
(TOP VIEW)
GVDD_B 1 44 GVDD_A
OTW 2 43 BST_A
NC 3 42 NC
NC 4 41 PVDD_A
SD 5 40 PVDD_A
PWM_A 6 39 OUT_A
RESET_AB 7 38 GND_A
PWM_B 8 37 GND_B
OC_ADJ 9 36 OUT_B
GND 10 35 PVDD_B
AGND 11 34 BST_B
VREG 12 33 BST_C
M3 13 32 PVDD_C
M2 14 31 OUT_C
M1 15 30 GND_C
PWM_C 16 29 GND_D
RESET_CD 17 28 OUT_D
PWM_D 18 27 PVDD_D
NC 19 26 PVDD_D
NC 20 25 NC
VDD 21 24 BST_D
GVDD_C 22 23 GVDD_D
P0016-02
2 Submit Documentation Feedback Copyright © 2007, Texas Instruments Incorporated
Product Folder Link(s): TAS5352

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Protection MODE Selection Pins

Protection modes are selected by shorting M1, M2, and M3 to VREG or GND.
MODE PINS
Mode Name PWM Input (1) Description
M3 M2 M1
0 0 0 BTL mode 1 2N All protection systems enabled
0 0 1 BTL mode 2 2N Latching shudown on, PWM activity detector and OLP disabled
0 1 0 BTL mode 3 1N All protection systems enabled
(2)
0 1 1 PBTL mode 1N / 2N All protection systems enabled
1 0 0 SE mode 1 1N All protection systems enabled (3)
1 0 1 SE mode 2 1N Latching shudown on, PWM activity detector and OLP disabled (3)
1 1 0
Reserved
1 1 1
(1) The 1N and 2N naming convention is used to indicate the number of PWM lines to the power stage per channel in a specific mode.
(2) PWM_D is used to select between the 1N and 2N interface in PBTL mode (Low = 1N; High = 2N). PWM_D is internally pulled low in
PBTL mode. PWM_A is used as the PWM input in 1N mode and PWM_A and PWM_B are used as inputs for the 2N mode.
(3) PPSC detection system disabled.
Package Heat Dissipation Ratings (1)

PARAMETER TAS5352DDV
RθJC (°C/W)—2 BTL or 4 SE channels 1.3
RθJC (°C/W)—1 BTL or 2 SE channel(s) 2.6
RθJC (°C/W)—1 SE channel 5.0
(2)
Power Pad area 36 mm2
(1) JC is junction-to-case, CH is case-to-heatsink.

(2) RθCH is an important consideration. Assume a 2-mil thickness of high performance grease with a thermal conductivity at 2.5W/m-K
between the pad area and the heat sink. The RθCH with this condition is 0.6°C/W for the DDV package.
Copyright © 2007, Texas Instruments Incorporated Submit Documentation Feedback 3

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ABSOLUTE MAXIMUM RATINGS

(1)
over operating free-air temperature range unless otherwise noted
TAS5352
VDD to AGND –0.3 V to 13.2 V
GVDD_X to AGND –0.3 V to 13.2 V
(2)
PVDD_X to GND_X –0.3 V to 53 V
(2)
OUT_X to GND_X –0.3 V to 53 V
(2)
BST_X to GND_X –0.3 V to 66.2 V
(2)
BST_X to GVDD_X –0.3 V to 53 V
VREG to AGND –0.3 V to 4.2 V
GND_X to GND –0.3 V to 0.3 V
GND_X to AGND –0.3 V to 0.3 V
GND to AGND –0.3 V to 0.3 V
PWM_X, OC_ADJ, M1, M2, M3 to AGND –0.3 V to 4.2 V
RESET_X, SD, OTW to AGND –0.3 V to 7 V
Maximum continuous sink current (SD, OTW) 9 mA
Maximum operating junction temperature range, TJ 0°C to 125°C
Storage temperature –40°C to 125°C
Lead temperature, 1,6 mm (1/16 inch) from case for 10 seconds 260°C
Minimum pulse duration, low 30 ns
(1) Stresses beyond those listed under "absolute maximum ratings" may cause permanent damage to the device. These are stress ratings
only, and functional operation of the device at these or any other conditions beyond those indicated under "recommended operating
conditions" is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
(2) These voltages represent the dc voltage + peak ac waveform measured at the terminal of the device in all conditions.
ORDERING INFORMATION (1)

TA PACKAGE DESCRIPTION
0°C to 70°C TAS5352DDV 44-pin HTSSOP
(1) For the most current package and ordering information, see the Package Option Addendum at the end of this document, or see the TI
website at www.ti.com.

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Terminal Functions
TERMINAL (1)
FUNCTION DESCRIPTION
NAME DDV NO.
AGND 11 P Analog ground
BST_A 43 P Bootstrap pin, A-Side
BST_B 34 P Bootstrap pin, B-Side
BST_C 33 P Bootstrap pin, C-Side
BST_D 24 P Bootstrap pin, D-Side
GND 10 P Ground
GND_A 38 P Power ground for half-bridge A
GND_B 37 P Power ground for half-bridge B
GND_C 30 P Power ground for half-bridge C
GND_D 29 P Power ground for half-bridge D
GVDD_A 44 P Gate-drive voltage supply; A-Side
GVDD_B 1 P Gate-drive voltage supply; B-Side
GVDD_C 22 P Gate-drive voltage supply; C-Side
GVDD_D 23 P Gate-drive voltage supply; D-Side
M1 15 I Mode selection pin (LSB)
M2 14 I Mode selection pin
M3 13 I Mode selection pin (MSB)
NC 3, 4, 19, 20, 25, 42 – No connect. Pins may be grounded.
OC_ADJ 9 O Analog overcurrent programming pin
OTW 2 O Overtemperature warning signal, open-drain, active-low
OUT_A 39 O Output, half-bridge A
OUT_B 36 O Output, half-bridge B
OUT_C 31 O Output, half-bridge C
OUT_D 28 O Output, half-bridge D
PVDD_A 40, 41 P Power supply input for half-bridge A
PVDD_B 35 P Power supply input for half-bridge B
PVDD_C 32 P Power supply input for half-bridge C
PVDD_D 26, 27 P Power supply input for half-bridge D
PWM_A 6 I PWM Input signal for half-bridge A
PWM_B 8 I PWM Input signal for half-bridge B
PWM_C 16 I PWM Input signal for half-bridge C
PWM_D 18 I PWM Input signal for half-bridge D
RESET_AB 7 I Reset signal for half-bridge A and half-bridge B, active-low
RESET_CD 17 I Reset signal for half-bridge C and half-bridge D, active-low
SD 5 O Shutdown signal, open-drain, active-low
VDD 21 P Input power supply
VREG 12 P Internal voltage regulator
(1) I = input, O = output, P = power

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TYPICAL SYSTEM BLOCK DIAGRAM
OTW
System
Microcontroller SD
I2C
TAS5518
OTW
SD
BST_A
Bootstrap
BST_B Capacitors
VALID RESET_AB
RESET_CD
PWM_A
OUT_A
Left- 2nd-Order L-C
Input Output
Channel Output Filter
H-Bridge 1 H-Bridge 1
Output OUT_B for Each
PWM_B
Half-Bridge
2-Channel
H-Bridge
BTL Mode
PWM_C OUT_C
2nd-Order L-C
Right- Output
Output Filter
Channel H-Bridge 2
Input OUT_D for Each
Output H-Bridge 2 Half-Bridge
PWM_D
GVDD_A, B, C, D
PVDD_A, B, C, D
M1
GND_A, B, C, D
BST_C
Hardwire M2
Mode Bootstrap
OC_ADJ
Control Capacitors
AGND
BST_D
VREG
GND
VDD
M3
4 4 4
PVDD GVDD
PVDD Power VDD
34.5 V Supply Hardwire
VREG
System Decoupling Power Supply OC Limit
Power Decoupling
Supply
GND
GND
GVDD (12 V)/VDD (12 V)

12 V
VAC
B0047-02

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FUNCTIONAL BLOCK DIAGRAM
4 VDD
Under-
OTW voltage 4
Protection
Internal Pullup VREG VREG
Resistors to VREG
SD
Power
On
M1
Reset AGND
Protection
M2 and
I/O Logic
M3 Temp.
Sense GND
RESET_AB
Overload
RESET_CD Isense OC_ADJ
Protection
GVDD_D
BST_D
PVDD_D
PWM Gate
PWM_D Ctrl. Timing OUT_D
Rcv. Drive
BTL/PBTL−Configuration
Pulldown Resistor
GND_D
GVDD_C
BST_C
PVDD_C
PWM Gate
PWM_C Ctrl. Timing OUT_C
Rcv. Drive
Pulldown Resistor
GND_C
GVDD_B
BST_B
PVDD_B
PWM Gate
PWM_B Ctrl. Timing OUT_B
Rcv. Drive
Pulldown Resistor
GND_B
GVDD_A
BST_A
PVDD_A
PWM Gate
PWM_A Ctrl. Timing OUT_A
Rcv. Drive
Pulldown Resistor
GND_A
B0034-03

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RECOMMENDED OPERATING CONDITIONS

MIN TYP MAX UNIT
PVDD_X Half-bridge supply voltage 0 34.5 37 V
Supply voltage for logic regulators and
GVDD_X 10.8 12 13.2 V
gate-drive circuitry
VDD Digital regulator supply voltage 10.8 12 13.2 V
RL (BTL) 3 4
Resistive load impedance (no Cycle-by_Cycle
RL (SE) current control), recommended demodulation 2.25 3 Ω
filter
RL (PBTL) 1.5 2
LOutput (BTL) 5 10
Minimum output inductance under
LOutput (SE) Output-filter inductance 5 10 μH
short-circuit condition
LOutput (PBTL) 5 10
fS PWM frame rate 192 384 432 kHz
tLOW Minimum low-state pulse duration per PWM
30 nS
Frame, noise shaper enabled
CPVDD PVDD close decoupling capacitors 0.1 μF
CBST Bootstrap capacitor, selected value supports
33 nF
PWM frame rates from 192 kHz to 432 kHz
ROC Over-current programming resistor Resistor tolerance = 5% 22 22 47 kΩ
REXT-PULLUP External pull-up resistor to +3.3V to +5.0V for
3.3 4.7 kΩ
SD or OTW
TJ Junction temperature 0 125 °C
AUDIO SPECIFICATIONS (BTL)

Audio performance is recorded as a chipset consisting of a TAS5518 pwm processor (modulation index limited to 97.7%) and
a TAS5352 power stage. PCB and system configuraton are in accordance with recommended guidelines. Audio frequency =
1kHz, PVDD_x = 34.5 V, GVDD_x = 12 V, RL = 4Ω, fS = 384 kHz, ROC = 22 kΩ, TC = 75°C, Output Filter: LDEM = 10 μH, CDEM
= 470 nF, unless otherwise noted.
TAS5352
PARAMETER TEST CONDITIONS UNIT
MIN TYP MAX
RL = 4 Ω, 10% THD+N, clipped input
125
signal
POMAX Maximum Power Output 100
signal
76 W
signal
RL = 4 Ω, 0 dBFS, unclipped input
96
signal
PO Unclipped Power Output 72
signal
57
signal
0 dBFS; AES17 filter 0.2%
THD+N Total harmonic distortion + noise
1 W; AES17 filter 0.09%
Vn Output integrated noise A-weighted, AES17 filter, Auto mute μV
50
disabled
(1)
SNR Signal-to-noise ratio A-weighted, AES17 filter, Auto mute
110 dB
disabled
A-weighted, input level = –60 dBFS,
DNR Dynamic range 110 dB
AES17 filter
DC Offset Output offset voltage +/- 15 mV
Pidle Power dissipation due to idle losses (IPVDD_X) PO = 0 W, all halfbridges switching (2) 2 W
(1) SNR is calculated relative to 0-dBFS input level.

(2) Actual system idle losses are affected by core losses of output inductors.

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AUDIO SPECIFICATIONS (Single-Ended Output)

= 1.0 μF, unless otherwise noted.
TAS5352
MIN TYP MAX
45
signal
POMAX Maximum Power Output
35
signal
W
35
signal
PO Unclipped Power Output
25
signal
Vn A-weighted, AES17 filter, Auto mute 40 μV
Output integrated noise
disabled
SNR A-weighted, AES17 filter, Auto mute 109 dB
Signal-to-noise ratio (1)
disabled
A-weighted, input level = –60 dBFS
AES17 filter
(2)
Pidle Power dissipation due to idle losses (IPVDD_X) PO = 0 W, all halfbridges switching 2 W

AUDIO SPECIFICATIONS (PBTL)

= 1 uF, unless otherwise noted.
TAS5352
MIN TYP MAX
195
signal
POMAX Maximum Power Output
250
signal
W
145
signal
PO Unclipped Power Output
190
signal
Vn A-weighted, AES17 filter, Auto mute 50 μV
Output integrated noise
disabled
SNR A-weighted, AES17 filter, Auto mute 110 dB
Signal-to-noise ratio (1)
disabled
A-weighted, input level = –60 dBFS
AES17 filter
DC Offset Output offset voltage +/- 15 mV
Pidle Power dissipation due to idle losses (IPVDD_X) PO = 0 W, all halfbridges switching (2) 2 W


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ELECTRICAL CHARACTERISTICS
PVDD_x = 34.5 V, GVDD_X = 12 V, VDD = 12 V, TC (Case temperature) = 75°C, fS = 384 kHz, unless otherwise specified.
TAS5352
MIN TYP MAX
Internal Voltage Regulator and Current Consumption
Voltage regulator, only used as a
VREG VDD = 12 V 3 3.3 3.6 V
reference node
Operating, 50% duty cycle 7.2 17
IVDD VDD supply current mA
Idle, reset mode 5.5 11
50% duty cycle 8 16
IGVDD_X Gate supply current per half-bridge mA
Reset mode 1 1.8
50% duty cycle, without output filter or load 13.6 25 mA
IPVDD_X Half-bridge idle current
Reset mode, no switching 525 630 μA
Output Stage MOSFETs
Drain-to-source resistance, Low
RDSon,LS TJ = 25°C, excludes metallization resistance, 80 89 mΩ
Side
Drain-to-source resistance, High
RDSon,HS TJ = 25°C, excludes metallization resistance, 80 89 mΩ
Side
I/O Protection
Undervoltage protection limit,
Vuvp,G 9.5 V
GVDD_X
Vuvp,hyst (1) Undervoltage protection limit, 250 mV
GVDD_X
BSTuvpF Puts device into RESET when BST 5.9 V
voltage falls below limit
BSTuvpR Brings device out of RESET when 7 V
BST voltage rises above limit
OTW (1) Overtemperature warning 115 125 135 °C
Temperature drop needed below
OTWHYST (1) OTW temp. for OTW to be inactive 25 °C
after the OTW event
OTE (1) Overtemperature error threshold 145 155 165 °C
OTE- OTE - OTW differential, temperature
30 °C
OTWdifferential (1) delta between OTW and OTE
OLPC Overload protection counter fS = 384 kHz 1.25 ms
Resistor—programmable, high-end,
IOC Overcurrent limit protection 10.9 A
ROC = 22 kΩ with 1 mS pulse
IOCT Overcurrent response time 150 ns
tACTIVITY Time for PWM activity detector to
Lack of transistion of any PWM input 13.2 μS
DETECTOR activite when no PWM is present
Connected when RESET is active to provide
Output pulldown current of each
IPD bootstrap capacitor charge. Not used in SE 3 mA
half-bridge
mode.
Static Digital Specifications
VIH High-level input voltage PWM_A, PWM_B, PWM_C, PWM_D, M1, 2 V
VIL Low-level input voltage M2, M3, RESET_AB, RESET_CD 0.8 V
ILeakage Input leakage current 100 μA
OTW/SHUTDOWN (SD)
Internal pullup resistance, OTW to
RINT_PU 20 26 32 kΩ
VREG, SD to VREG
Internal pullup resistor 3 3.3 3.6
VOH High-level output voltage V
External pullup of 4.7 kΩ to 5 V 4.5 5
VOL Low-level output voltage IO = 4 mA 0.2 0.4 V
(1) Specified by design

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ELECTRICAL CHARACTERISTICS (continued)

PVDD_x = 34.5 V, GVDD_X = 12 V, VDD = 12 V, TC (Case temperature) = 75°C, fS = 384 kHz, unless otherwise specified.
TAS5352
MIN TYP MAX
FANOUT Device fanout OTW, SD No external pullup 30 Devices
TYPICAL CHARACTERISTICS, BTL CONFIGURATION

TOTAL HARMONIC DISTORTION + NOISE OUTPUT POWER
vs vs
OUTPUT POWER SUPPLY VOLTAGE
10 150
TC = 75°C 140 TC = 75°C
5
THD+N at 10%
THD+N – Total Hamonic Distortion – %
130 THD+N at 10%

2 120
110
1 4Ω
100
0.5 90
80
0.2 4Ω 6Ω
70
0.1 60
6Ω
50
0.05
40
0.02
30
8Ω
20
0.01
10
8Ω
0.005 0
20m 50m 100m 200m 500m 1 2 5 10 20 50 100 200
0 2 4 6 8 10 12 14 16 18 20 22 24 26 28 30 32 34
PO – Output Power – W PVDD – Supply Voltage – V
Figure 1. Figure 2.
UNCLIPPED OUTPUT POWER SYSTEM EFFICIENCY

vs vs
SUPPLY VOLTAGE OUTPUT POWER
120 100
115 95
110 TC = 75°C
90
105
100 85
95 80
90 75 8Ω
85 6
8Ω
70
80
75 4Ω 65 4
8Ω
60
Efficiency – %
70
65 55
60 50
55
6Ω 45
50
45
40
40 35
35 30
30 25
25
20
20
8Ω 15 TC = 25°C
15
10 10 THD+N at 10%
5 5
0 0
0 2 4 6 8 10 12 14 16 18 20 22 24 26 28 30 32 34
0 40 80 120 160 200 240 280
PVDD – Supply Voltage – V 2 Channels Output Power – W

Figure 3. Figure 4.

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TYPICAL CHARACTERISTICS, BTL CONFIGURATION (continued)
SYSTEM POWER LOSS SYSTEM OUTPUT POWER

vs vs
OUTPUT POWER CASE TEMPERATURE
34 160
32
TC = 25°C 150
30 THD+N at 10% 140
28 130
6
4Ω
26 4Ω 120
24 110 4
8Ω
22 100
Power Loss – W
20
90
18
80
16
70
14
60
12 8Ω
10
50
8 6
8Ω 40
6 30
4 20
THD+N at 10%
2 8Ω 10
0
0
0 20 40 60 80 100 120 140 160 180 200 220 240 260 280
10 20 30 40 50 60 70 80 90 100 110 120
2 Channels Output Power – W
TC – Case Temperature – °C
Figure 5. Figure 6.
NOISE AMPLITUDE
vs
FREQUENCY
+0
–10 TC = 75°C
–20 VREF = 20.60 V
–30 Sample Rate = 48 kHz
FFT Size = 16384
–40
–50
Noise Amplitude – V
–60
–70
–80
–90
–100
–110
–120
–130
–140
–150
–160
0 1k 2k 3k 4k 5k 6k 7k 8k 9k 10k 11k 12k 13k 14k 15k 16k 17k 18k 19k 20k 21k 22k
f – Frequency – kHz
Figure 7.

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TYPICAL CHARACTERISTICS, SE CONFIGURATION

vs vs
10 60
57.5
5 TC = 75°C 55 TC = 75°C
52.5 THD+N at 10%

THD+N at 10% 50
2 47.5
45
1 42.5
40
0.5 37.5
35 3Ω
32.5
0.2 3Ω 30
27.5
0.1 25
22.5
0.05 20
17.5
15
0.02 4Ω 12.5
10
7.5
0.01 4Ω
5
2.5
0.005
0
20m 50m 100m 200m 500m 1 2 5 10 20 50 80 0 2 4 6 8 10 12 14 16 18 20 22 24 26 28 30 32 34
Figure 8. Figure 9.
OUTPUT POWER
vs
CASE TEMPERATURE
60
57.5
55
52.5
50
47.5
45
42.5
3Ω
40
37.5
35
32.5
30
4Ω
27.5
25
22.5
20
17.5
15
12.5
10
7.5
5
THD+N at 10%
2.5
0
10 20 30 40 50 60 70 80 90 100 110 120
Figure 10.

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TYPICAL CHARACTERISTICS, PBTL CONFIGURATION

vs vs
10 300
TC = 75°C 280 TC = 75°C
5
THD+N at 10% THD+N at 10%
4Ω 260
240
2
220
2
4Ω
1
200
0.5 180
160
0.2 2Ω 140 3Ω
4
120
0.1
4Ω
100
0.05
3Ω
80
60
0.02
40
0.01 8Ω 20 8Ω
0
0.005
0 2 4 6 8 10 12 14 16 18 20 22 24 26 28 30 32 34
20m 50m 100m 200m 500m 1 2 5 10 20 50 100 200 400

Figure 11. Figure 12.
SYSTEM OUTPUT POWER

vs
CASE TEMPERATURE
300
280
260
3
4Ω
240
220 2
8Ω
200
180
160
140
120
4
8Ω
100
80
60
40
8Ω
20 THD+N at 10%
0
10 20 30 40 50 60 70 80 90 100 110 120
Figure 13.

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APPLICATION INFORMATION
PCB Material Recommendation

FR-4 Glass Epoxy material with 2 oz. (70 μm) is recommended for use with the TAS5352. The use of this
material can provide for higher power output, improved thermal performance, and better EMI margin (due to
lower PCB trace inductance.
PVDD Capacitor Recommendation

The large capacitors used in conjunction with each full-birdge, are referred to as the PVDD Capacitors. These
capacitors should be selected for proper voltage margin and adequate capacitance to support the power
requirements. In practice, with a well designed system power supply, 1000 μF, 50-V will support more
applications. The PVDD capacitors should be low ESR type because they are used in a circuit associtated with
high-speed switching.
Decoupling Capacitor Recommendations

In order to design an amplifier that has robust performance, passes regulatory requirements, and exhibits good
audio performance, good quality decoupling capacitors should be used. In practice, X7R should be used in this
application.
The voltage of the decoupling capactors should be selected in accordance with good design practices.
Temperature, ripple current, and voltage overshoot must be considered. This fact is particularly true in the
selection of the 0.1μF that is placed on the power supply to each half-bridge. It must withstand the voltage
overshoot of the PWM switching, the heat generated by the amplifier during high power output, and the ripple
current created by high power power output. A minimum voltage rating of 50-V is required for use with a 34.5 V
power supply.
System Design Recommendations

The following schematics and PCB layouts illustrate "best practices" in the use of the TAS5352.
GVDD (+12 V)
PVDD
10 Ω 10 Ω
3.3 Ω
470 µF
100 nF 100 nF 50 V 10 nF
50 V
TAS5342DDV
GND GND
GVDD_B GVDD_A 10 µH GND
Microcontroller
OTW BST_A
33 nF 25 V 3.3 Ω
NC NC
I2C GND 1 nF
NC PVDD_A 50 V
GND 100 nF 10 nF
SD PVDD_A 50 V
100 nF 50 V
PWM1_P PWM_A OUT_A 50 V 470 nF
VALID RESET_AB GND_A
100 nF GND 10 nF
PWM1_M PWM_B GND_B GND 100 nF 50 V 1 nF 50 V
22 k 50 V 50 V GND
OC_ADJ OUT_B
GND PVDD_B 10 µH 3.3 Ω
GND 33 nF 25 V
AGND BST_B
VREG BST_C
33 nF 25V 10 µH 3.3 Ω
100 nF M3 PVDD_C
1 nF
M2 OUT_C 100 nF 50 V
GND 50 V 100 nF 10 nF
M1 GND_C 50 V
50 V
PWM2_P PWM_C GND_D
470 nF
RESET_CD OUT_D 10 nF
100 nF GND
PWM2_M PWM_D PVDD_D 100 nF 1 nF 50 V
50 V 50 V GND
50 V
NC PVDD_D
GND 3.3 Ω
TAS5508/18 NC NC 10 µH
0Ω GND
VDD BST_D
100 nF GVDD_C GVDD_D 33 nF 25 V PVDD
3.3 Ω
GND
470 µF
50 V 10 nF
100 nF 100 nF 50 V
10 Ω 10 Ω
GND GND
VDD (+12 V) GND GVDD (+12 V)
Figure 14. Typical Differential (2N) BTL Application With AD Modulation Filters

TAS5352
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GVDD (+12 V)
PVDD
10 Ω 10 Ω
3.3 Ω
470 µF
100 nF 100 nF 50 V 10 nF
50 V
TAS5352DDV
GND GND
Microcontroller
OTW BST_A
33 nF 25 V 3.3 Ω
NC NC
I2C GND 1 nF
NC PVDD_A 50 V
GND 100 nF 10 nF
SD PVDD_A 50 V
100 nF 50 V
PWM1_P PWM_A OUT_A 50 V 470 nF
100 nF GND 10 nF
PWM_B GND_B GND 100 nF 50 V 1 nF 50 V
22 k 50 V 50 V GND
OC_ADJ OUT_B
GND PVDD_B 10 µH 3.3 Ω
GND 33 nF 25 V
AGND BST_B
VREG BST_C
33 nF 25V 10 µH 3.3 Ω
100 nF M3 PVDD_C
1 nF
M2 OUT_C 100 nF 50 V
GND 50 V 100 nF 10 nF
M1 GND_C 50 V
50 V
PWM2_P PWM_C GND_D
470 nF
RESET_CD OUT_D 10 nF
100 nF GND
PWM_D PVDD_D 100 nF 1 nF 50 V
50 V 50 V GND
50 V
NC PVDD_D
GND 3.3 Ω
0Ω GND
VDD BST_D
3.3 Ω
GND
470 µF
50 V 10 nF
100 nF 100 nF 50 V
10 Ω 10 Ω
GND GND
Figure 15. Typical Non-Differential (1N) BTL Application With AD Modulation Filters

TAS5352
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GVDD (+12 V)
PVDD
10 Ω 10 Ω
3.3 Ω
470 µF
100 nF 100 nF 50 V 10 nF
50 V
TAS5352DDV
GND GND
GVDD_B GVDD_A 20 µH
Microcontroller
OTW BST_A A
33 nF 25 V
NC NC
I2C GND
NC PVDD_A
GND
SD PVDD_A
100 nF
PWM1_P PWM_A OUT_A 50 V
PWM2_P PWM_B GND_B GND 100 nF
22 k 50 V
OC_ADJ OUT_B
GND PVDD_B 20 µH
GND 33 nF 25 V
AGND BST_B B
VREG BST_C C
33 nF 25V 20 µH
100 nF M3 PVDD_C
M2 OUT_C 100 nF
M1 GND_C GND 50 V
PWM3_P PWM_C GND_D
RESET_CD OUT_D
100 nF
PWM4_P PWM_D PVDD_D 50 V
NC PVDD_D
GND
0Ω GND
VDD BST_D D
3.3 Ω
GND
470 µF
50 V 10 nF
100 nF 100 nF 50 V
10 Ω 10 Ω
GND GND
10 nF
10 nF 50 V
50 V
GND GND
3.3 Ω 3.3 Ω
A B
100nF 100 nF
PVDD 50V PVDD 50 V
10 k 1 µF 10 k 1 µF
470 µF 470 µF
100nF 50V 100 nF
50 V GND
50 V 50 V
GND
470 µF 3.3 Ω 470 µF 3.3 Ω

50 V 50 V
GND
GND 50 V 50 V GND
GND 10 nF
10 nF
10 nF 10 nF
50 V 50 V
GND 3.3 Ω GND

3.3 Ω
C D
100 nF 100 nF
PVDD 50 V PVDD 50 V
10 k 1 µF 10 k 1 µF
470 µF 470 µF
50 V 100 nF 50 V 100 nF
GND 50 V GND
50 V
470 µF 3. 3 Ω 470 µF 3.3 Ω

50 V 50 V
GND
50 V GND 50 V GND
GND 10 nF
10 nF
Figure 16. Typical SE Application

TAS5352
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GVDD (+12 V)
PVDD
10 Ω 10 Ω
3.3 Ω
470 µF
100 nF 100 nF 50 V 10 nF
50 V
TAS5352DDV
GND GND
Microcontroller
OTW BST_A
33 nF 25 V
NC NC
I2C GND
NC PVDD_A
GND
SD PVDD_A
100 nF
PWM1_P PWM_A OUT_A
PWM_B GND_B GND 100 nF 3.3 Ω
PWM1_M
22 k 50 V 1 nF
OC_ADJ OUT_B 50 V
1R 100 nF 10 nF
GND PVDD_B 10 µH 50 V
GND 33 nF 25 V 50 V
AGND BST_B
1 µF
VREG BST_C
33 nF 25V 10 µH 100 nF 10 nF
100 nF M3 PVDD_C 50 V 1 nF 50 V
50 V GND
M2 OUT_C 100 nF
M1 GND_C GND 50 V 3.3 Ω
PWM_C GND_D
RESET_CD OUT_D
100 nF
PWM_D PVDD_D 50 V
NC PVDD_D
GND
0Ω GND
VDD BST_D
3.3 Ω
GND
470 µF
50 V 10 nF
100 nF 100 nF 50 V
10 Ω 10 Ω
GND GND
Figure 17. Typical Differential (2N) PBTL Application With AD Modulation Filters
GVDD (+12 V)
PVDD
10 Ω 10 Ω
3.3 Ω
470 µF
100 nF 100 nF 50 V 10 nF
50 V
TAS5352DDV
GND GND
Microcontroller
OTW BST_A
33 nF 25 V
NC NC
I2C GND
NC PVDD_A
GND
SD PVDD_A
100 nF
PWM1_P PWM_A OUT_A 50 V
PWM_B GND_B GND 100 nF 3.3 Ω
PWM1_M
22 k 50 V 1 nF
OC_ADJ OUT_B 50 V
1R 100 nF 10 nF
GND PVDD_B 10 µH 50 V
GND 33 nF 25 V 50 V
AGND BST_B
1 µF
VREG BST_C
33 nF 25V 10 µH 100 nF 10 nF
100 nF M3 PVDD_C 50 V 1 nF 50 V
50 V GND
M2 OUT_C 100 nF
M1 GND_C GND 50 V 3.3 Ω
PWM_C GND_D
RESET_CD OUT_D
100 nF
PWM_D PVDD_D 50 V
NC PVDD_D
GND
0Ω GND
VDD BST_D
3.3 Ω
GND
470 µF
50 V 10 nF
100 nF 100 nF 50 V
10 Ω 10 Ω
GND GND
Figure 18. Typical Non-Differential (1N) PBTL Application

TAS5352
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THEORY OF OPERATION
Special attention should be paid to the power-stage

POWER SUPPLIES power supply; this includes component selection,
To facilitate system design, the TAS5352 needs only PCB placement, and routing. As indicated, each
a 12 V supply in addition to the (typical) 34.5 V half-bridge has independent power-stage supply pins
power-stage supply. An internal voltage regulator (PVDD_X). For optimal electrical performance, EMI
provides suitable voltage levels for the digital and compliance, and system reliability, it is important that
low-voltage analog circuitry. Additionally, all circuitry each PVDD_X pin is decoupled with a 100-nF
requiring a floating voltage supply, e.g., the high-side ceramic capacitor placed as close as possible to
gate drive, is accommodated by built-in bootstrap each supply pin. It is recommended to follow the PCB
circuitry requiring only an external capacitor for each layout of the TAS5352 reference design. For
half-bridge. additional information on recommended power supply
and required components, see the application
In order to provide outstanding electrical and diagrams given previously in this data sheet.
acoustical characteristics, the PWM signal path
including gate drive and output stage is designed as The 12 V supply should be from a low-noise,
identical, independent half-bridges. For this reason, low-output-impedance voltage regulator. Likewise, the
each half-bridge has separate gate drive supply 34.5 V power-stage supply is assumed to have low
(GVDD_X), bootstrap pins (BST_X), and power-stage output impedance and low noise. The power-supply
supply pins (PVDD_X). Furthermore, an additional pin sequence is not critical as facilitated by the internal
(VDD) is provided as supply for all common circuits. power-on-reset circuit. Moreover, the TAS5352 is fully
Although supplied from the same 12-V source, it is protected against erroneous power-stage turnon due
highly recommended to separate GVDD_A, to parasitic gate charging. Thus, voltage-supply ramp
GVDD_B, GVDD_C, GVDD_D, and VDD on the rates (dV/dt) are non-critical within the specified
printed-circuit board (PCB) by RC filters (see range (see the Recommended Operating Conditions
application diagram for details). These RC filters section of this data sheet).
provide the recommended high-frequency isolation.
Special attention should be paid to placing all SYSTEM POWER-UP/POWER-DOWN
decoupling capacitors as close to their associated SEQUENCE
pins as possible. In general, inductance between the
power supply pins and decoupling capacitors must be Powering Up
avoided. (See reference board documentation for
The TAS5352 does not require a power-up sequence.
additional information.)
The outputs of the H-bridges remain in a high-imped-
For a properly functioning bootstrap circuit, a small ance state until the gate-drive supply voltage
ceramic capacitor must be connected from each (GVDD_X) and VDD voltage are above the
bootstrap pin (BST_X) to the power-stage output pin undervoltage protection (UVP) voltage threshold (see
(OUT_X). When the power-stage output is low, the the Electrical Characteristics section of this data
bootstrap capacitor is charged through an internal sheet). Although not specifically required, it is
diode connected between the gate-drive power-- recommended to hold RESET_AB and RESET_CD in
supply pin (GVDD_X) and the bootstrap pin. When a low state while powering up the device. This allows
the power-stage output is high, the bootstrap an internal circuit to charge the external bootstrap
capacitor potential is shifted above the output capacitors by enabling a weak pulldown of the
potential and thus provides a suitable voltage supply half-bridge output.
for the high-side gate driver. In an application with
When the TAS5352 is being used with TI PWM
PWM switching frequencies in the range from 352
modulators such as the TAS5518, no special
kHz to 384 kHz, it is recommended to use 33-nF
attention to the state of RESET_AB and RESET_CD
ceramic capacitors, size 0603 or 0805, for the
is required, provided that the chipset is configured as
bootstrap supply. These 33-nF capacitors ensure
recommended.
sufficient energy storage, even during minimal PWM
duty cycles, to keep the high-side power stage FET
Powering Down
(LDMOS) fully turned on during the remaining part of
the PWM cycle. In an application running at a The TAS5352 does not require a power-down
reduced switching frequency, generally 192 kHz, the sequence. The device remains fully operational as
bootstrap capacitor might need to be increased in long as the gate-drive supply (GVDD_X) voltage and
value. VDD voltage are above the undervoltage protection
(UVP) voltage threshold (see the Electrical

TAS5352
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Characteristics section of this data sheet). Although signal using the system microcontroller and
not specifically required, it is a good practice to hold responding to an overtemperature warning signal by,
RESET_AB and RESET_CD low during power down, e.g., turning down the volume to prevent further
thus preventing audible artifacts including pops or heating of the device resulting in device shutdown
clicks. (OTE).
When the TAS5352 is being used with TI PWM To reduce external component count, an internal
modulators such as the TAS5518, no special pullup resistor to 3.3 V is provided on both SD and
attention to the state of RESET_AB and RESET_CD OTW outputs. Level compliance for 5-V logic can be
is required, provided that the chipset is configured as obtained by adding external pullup resistors to 5 V
recommended. (see the Electrical Characteristics section of this data
sheet for further specifications).
Mid Z Sequence Compatability
DEVICE PROTECTION SYSTEM
The TAS5352 is compatable with the Mid Z sequence
of the TAS5086 Modulator. The Mid Z Sequence is a The TAS5352 contains advanced protection circuitry
series of pulses that is generated by the modulator. carefully designed to facilitate system integration and
This sequence causes the power stage to slowly ease of use, as well as to safeguard the device from
enable its outputs as it begins to switch. permanent failure due to a wide range of fault
conditions such as short circuits, overload,
By slowly starting the PWM switching, the impulse overtemperature, and undervoltage. The TAS5352
response created by the onset of switching is responds to a fault by immediately setting the power
reduced. This impulse response is the acoustic stage in a high-impedance (Hi-Z) state and asserting
artifact that is heard in the output transducers the SD pin low. In situations other than overload and
(loudspeakers) and is commonly termed "click" or over-temperature error (OTE), the device
"pop". automatically recovers when the fault condition has
The low acoustic artifact noise of the TAS5352 will be been removed, i.e., the supply voltage has increased.
further decreased when used in conjunction with the The device will function on errors, as shown in the
TAS5086 modulator with the Mid Z Sequence following table
enabled.
BTL MODE PBTL MODE SE MODE
The Mid Z sequence is primarily used for the
Local Local Local
single-ended output configuration. It facilitates a Error Turns Off Error Turns Off Error Turns Off
"softer" PWM output start after the split cap output In In In
configuration is charged. A A A
A+B A+B
B B A+B+C B
ERROR REPORTING +D
C C C
The SD and OTW pins are both active-low, C+D C+D
D D D
open-drain outputs. Their function is for
protection-mode signaling to a PWM controller or Bootstrap UVP does not shutdown according to the
other system-control device. table, it shutsdown the respective halfbridge.
Any fault resulting in device shutdown is signaled by
the SD pin going low. Likewise, OTW goes low when Use of TAS5352 in High-Modulation-Index
the device junction temperature exceeds 125°C (see Capable Systems
the following table). This device requires at least 30 ns of low time on the
SD OTW DESCRIPTION output per 384-kHz PWM frame rate in order to keep
the bootstrap capacitors charged. As an example, if
0 0 Overtemperature (OTE) or overload (OLP) or
undervoltage (UVP) the modulation index is set to 99.2% in the TAS5508,
this setting allows PWM pulse durations down to 10
0 1 Overload (OLP) or undervoltage (UVP)
ns. This signal, which does not meet the 30-ns
1 0 Junction temperature higher than 125°C requirement, is sent to the PWM_X pin and this
(overtemperature warning)
low-state pulse time does not allow the bootstrap
1 1 Junction temperature lower than 125°C and no capacitor to stay charged. The TAS5352 device
OLP or UVP faults (normal operation)
requires limiting the TAS5508 modulation index to
Note that asserting either RESET_AB or RESET_CD 97.7% to keep the bootstrap capacitor charged under
low forces the SD signal high, independent of faults all signals and loads.
being present. TI recommends monitoring the OTW The TAS5352 contains a bootstrap capacitor under
voltage protection circuit (BST_UVP) that monitors
the voltage on the bootstrap capacitors. When the

TAS5352
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voltage on the bootstrap capacitors is less than In general, it is recommended to follow closely the
required for proper control of the High-Side external component selection and PCB layout as
MOSFETs, the device will initiate bootstrap capacitor given in the Application section.
recharge sequences until the bootstrap capacitors are
properly charged for robust operation. This function For added flexibility, the OC threshold is
programmable within a limited range using a single
may be activated with PWM pulses less than 30 nS.
external resistor connected between the OC_ADJ pin
Therefore, TI strongly recommends using a TI PWM and AGND. (See the Electrical Characteristics section
processor, such as TAS5518, TAS5086 or TAS5508, of this data sheet for information on the correlation
with the modulation index set at 97.7% to interface between programming-resistor value and the OC
with TAS5352. threshold.) It should be noted that a properly
functioning overcurrent detector assumes the
Overcurrent (OC) Protection With Current presence of a properly designed demodulation filter at
Limiting and Overload Detection the power-stage output. It is required to follow certain
guidelines when selecting the OC threshold and an
The device has independent, fast-reacting current
appropriate demodulation inductor:
detectors with programmable trip threshold (OC
threshold) on all high-side and low-side power-stage OC-Adjust Resistor Values Max. Current Before OC Occurs
FETs. See the following table for OC-adjust resistor (kΩ) (A), TC = 75°C
values. The detector outputs are closely monitored by 22 10.9
two protection systems. The first protection system 33 9.1
controls the power stage in order to prevent the 47 7.1
output current from further increasing, i.e., it performs
a current-limiting function rather than prematurely The reported max peak current in the table above is
shutting down during combinations of high-level measured with continuous current in 1 Ω, one
music transients and extreme speaker load channel active and the other one muted.
impedance drops. If the high-current situation
persists, i.e., the power stage is being overloaded, a Pin-To-Pin Short Circuit Protection (PPSC)
second protection system triggers a latching
shutdown, resulting in the power stage being set in The PPSC detection system protects the device from
the high-impedance (Hi-Z) state. Current limiting and permanent damage in the case that a power output
overload protection are independent for half-bridges pin (OUT_X) is shorted to GND_X or PVDD_X. For
A and B and, respectively, C and D. That is, if the comparison the OC protection system detects an over
bridge-tied load between half-bridges A and B causes current after the demodulation filter where PPSC
an overload fault, only half-bridges A and B are shut detects shorts directly at the pin before the filter.
down. PPSC detection is performed at startup i.e. when
• For the lowest-cost bill of materials in terms of VDD is supplied, consequently a short to either
component selection, the OC threshold measure GND_X or PVDD_X after system startup will not
should be limited, considering the power output activate the PPSC detection system. When PPSC
requirement and minimum load impedance. detection is activated by a short on the output, all half
Higher-impedance loads require a lower OC bridges are kept in a Hi-Z state until the short is
threshold. removed, the device then continues the startup
sequence and starts switching. The detection is
• The demodulation-filter inductor must retain at controlled globally by a two step sequence. The first
least 5 μH of inductance at twice the OC threshold step ensures that there are no shorts from OUT_X to
setting. GND_X, the second step tests that there are no
Unfortunately, most inductors have decreasing shorts from OUT_X to PVDD_X. The total duration of
inductance with increasing temperature and this process is roughly proportional to the capacitance
increasing current (saturation). To some degree, an of the output LC filter. The typical duration is < 15
increase in temperature naturally occurs when ms/μF. While the PPSC detection is in progress, SD
operating at high output currents, due to core losses is kept low, and the device will not react to changes
and the dc resistance of the inductor's copper applied to the RESET pins. If no shorts are present
winding. A thorough analysis of inductor saturation the PPSC detection passes, and SD is released. A
and thermal properties is strongly recommended. device reset will not start a new PPSC detection.
PPSC detection is enabled in BTL and PBTL output
Setting the OC threshold too low might cause issues configurations, the detection is not performed in SE
such as lack of enough output power and/or mode. To make sure not to trip the PPSC detection
unexpected shutdowns due to too-sensitive overload system it is recommended not to insert resistive load
detection. to GND_X or PVDD_X.

TAS5352
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Overtemperature Protection DEVICE RESET

The TAS5352 has a two-level temperature-protection Two reset pins are provided for independent control
system that asserts an active-low warning signal of half-bridges A/B and C/D. When RESET_AB is
(OTW) when the device junction temperature asserted low, all four power-stage FETs in half--
exceeds 125°C (typical) and, if the device junction bridges A and B are forced into a high-impedance
temperature exceeds 155°C (typical), the device is (Hi-Z) state. Likewise, asserting RESET_CD low
put into thermal shutdown, resulting in all half-bridge forces all four power-stage FETs in half-bridges C
outputs being set in the high-impedance (Hi-Z) state and D into a high-impedance state. Thus, both reset
and SD being asserted low. OTE is latched in this pins are well suited for hard-muting the power stage if
case. To clear the OTE latch, either RESET_AB or needed.
RESET_CD must be asserted. Thereafter, the device
resumes normal operation. In BTL modes, to accommodate bootstrap charging
prior to switching start, asserting the reset inputs low
Undervoltage Protection (UVP) and Power-On enables weak pulldown of the half-bridge outputs. In
Reset (POR) the SE mode, the weak pulldowns are not enabled,
and it is therefore recommended to ensure bootstrap
The UVP and POR circuits of the TAS5352 fully capacitor charging by providing a low pulse on the
protect the device in any power-up/down and PWM inputs when reset is asserted high.
brownout situation. While powering up, the POR
circuit resets the overload circuit (OLP) and ensures Asserting either reset input low removes any fault
that all circuits are fully operational when the information to be signalled on the SD output, i.e., SD
GVDD_X and VDD supply voltages reach stated in is forced high.
the Electrical Characteristics Table. Although A rising-edge transition on either reset input allows
GVDD_X and VDD are independently monitored, a the device to resume operation after an overload
supply voltage drop below the UVP threshold on any fault. To ensure thermal reliability, the rising edge of
VDD or GVDD_X pin results in all half-bridge outputs reset must occur no sooner than 4 ms after the falling
immediately being set in the high-impedance (Hi-Z) edge of SD.
state and SD being asserted low. The device
automatically resumes operation when all supply
voltages have increased above the UVP threshold.

PACKAGE OPTION ADDENDUM
www.ti.com 24-Aug-2018
PACKAGING INFORMATION
Orderable Device Status Package Type Package Pins Package Eco Plan Lead/Ball Finish MSL Peak Temp Op Temp (°C) Device Marking Samples
(1) Drawing Qty (2) (6) (3) (4/5)
TAS5352DDV NRND HTSSOP DDV 44 35 Green (RoHS CU NIPDAU Level-3-260C-168 HR 0 to 70 TAS5352

& no Sb/Br)
TAS5352DDVR NRND HTSSOP DDV 44 2000 Green (RoHS CU NIPDAU Level-3-260C-168 HR 0 to 70 TAS5352
& no Sb/Br)
(1)
The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may
reference these types of products as "Pb-Free".
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of <=1000ppm threshold. Antimony trioxide based
flame retardants must also meet the <=1000ppm threshold requirement.
(3)
MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
(4)
There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.
(5)
Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation
of the previous line and the two combined represent the entire Device Marking for that device.
(6)
Lead/Ball Finish - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead/Ball Finish values may wrap to two lines if the finish
value exceeds the maximum column width.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
Addendum-Page 1
PACKAGE OPTION ADDENDUM
www.ti.com 24-Aug-2018
Addendum-Page 2
PACKAGE MATERIALS INFORMATION
www.ti.com 14-Feb-2019
TAPE AND REEL INFORMATION
*All dimensions are nominal

Device Package Package Pins SPQ Reel Reel A0 B0 K0 P1 W Pin1
Type Drawing Diameter Width (mm) (mm) (mm) (mm) (mm) Quadrant
(mm) W1 (mm)
TAS5352DDVR HTSSOP DDV 44 2000 330.0 24.4 8.6 15.6 1.8 12.0 24.0 Q1
Pack Materials-Page 1
PACKAGE MATERIALS INFORMATION
www.ti.com 14-Feb-2019
*All dimensions are nominal

Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm)
TAS5352DDVR HTSSOP DDV 44 2000 350.0 350.0 43.0
Pack Materials-Page 2
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125 W Stereo Digital Amplifier Power Stage: Features Description

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125 W Stereo Digital Amplifier Power Stage: Features Description

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TM

125 W STEREO DIGITAL AMPLIFIER POWER STAGE

– Overtemperature Warning and Error 140 TC = 75°C

• EMI Compliant When Used With 10

Recommended System Design 0

APPLICATIONS PVDD – Supply Voltage – V

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Protection MODE Selection Pins

Package Heat Dissipation Ratings (1)

(1) JC is junction-to-case, CH is case-to-heatsink.

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ABSOLUTE MAXIMUM RATINGS

ORDERING INFORMATION (1)

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(1) I = input, O = output, P = power

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TYPICAL SYSTEM BLOCK DIAGRAM

GVDD (12 V)/VDD (12 V)

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FUNCTIONAL BLOCK DIAGRAM

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RECOMMENDED OPERATING CONDITIONS

AUDIO SPECIFICATIONS (BTL)

(1) SNR is calculated relative to 0-dBFS input level.

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AUDIO SPECIFICATIONS (Single-Ended Output)

(1) SNR is calculated relative to 0-dBFS input level.

AUDIO SPECIFICATIONS (PBTL)

(1) SNR is calculated relative to 0-dBFS input level.

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(1) Specified by design

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ELECTRICAL CHARACTERISTICS (continued)

TYPICAL CHARACTERISTICS, BTL CONFIGURATION

130 THD+N at 10%

UNCLIPPED OUTPUT POWER SYSTEM EFFICIENCY

PVDD – Supply Voltage – V 2 Channels Output Power – W

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TYPICAL CHARACTERISTICS, BTL CONFIGURATION (continued)

SYSTEM POWER LOSS SYSTEM OUTPUT POWER

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TYPICAL CHARACTERISTICS, SE CONFIGURATION

52.5 THD+N at 10%

PO – Output Power – W PVDD – Supply Voltage – V

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TYPICAL CHARACTERISTICS, PBTL CONFIGURATION

PO – Output Power – W PVDD – Supply Voltage – V

SYSTEM OUTPUT POWER

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PCB Material Recommendation

PVDD Capacitor Recommendation

Decoupling Capacitor Recommendations

System Design Recommendations

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470 µF 3.3 Ω 470 µF 3.3 Ω

GND 3.3 Ω GND

470 µF 3. 3 Ω 470 µF 3.3 Ω

Figure 16. Typical SE Application

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Figure 18. Typical Non-Differential (1N) PBTL Application

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Special attention should be paid to the power-stage

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Overtemperature Protection DEVICE RESET