SEQUENTIAL CIRCUITS
Consist of a combinational circuit to which storage
elements are connected to form a feedback path
State: – the state of the memory devices now, also
called current state
Next states and outputs are functions of inputs and
present states of storage elements
TWO TYPES OF SEQUENTIAL CIRCUITS
Asynchronous sequential circuit
Depends upon the input signals at any instant of
time and their change order
May have better performance but hard to design
Synchronous sequential circuit
Defined from the knowledge of its signals at
discrete instants of time
Much easier to design (preferred design style)
Synchronized by a periodic train of clock pulses
SYNCHRONOUS SEQUENTIAL CIRCUITS
MEMORY ELEMENTS
Latch -—a level-sensitive memory element
SR latches
D latches
Flip-Flop —
- an edge-triggered memory element
Master-slave flip-flop
Edge-triggered flip-flop
RAM and ROM — a mass memory element
LATCHES
A latch is binary storage element
Can store a 0 or 1
The most basic memory
Easy to build
Built with gates (NORs, NANDs, NOT)
LATCHES
S R Q0 Q Q’
SR Latch 0 0 0 0 1 Q = Q0
R 0 0
Q
S Q
0 1
Initial Value
LATCHES
S R Q0 Q Q’
SR Latch 0 0 0 0 1 Q = Q0
0 0 1 1 0 Q = Q0
R 0 1
Q
S Q
0 0
LATCHES
S R Q0 Q Q’
SR Latch 0 0 0 0 1
Q = Q0
0 0 1 1 0
0 1 0 0 1 Q=0
R 1 0
Q
S Q
0 1
LATCHES
S R Q0 Q Q’
SR Latch 0 0 0 0 1
Q = Q0
0 0 1 1 0
0 1 0 0 1 Q=0
R 1 1
Q
0 1 1 0 1 Q=0
S Q
0 0
LATCHES
S R Q0 Q Q’
SR Latch 0 0 0 0 1
Q = Q0
0 0 1 1 0
0 1 0 0 1
R 0
Q=0
0 0 1 1 0 1
Q 1 0 0 1 0 Q=1
S Q
1 1
LATCHES
S R Q0 Q Q’
SR Latch 0 0 0 0 1
Q = Q0
0 0 1 1 0
0 1 0 0 1
R 0
Q=0
1 0 1 1 0 1
Q 1 0 0 1 0 Q=1
1 0 1 1 0 Q=1
S Q
1 0
LATCHES
S R Q0 Q Q’
SR Latch 0 0 0 0 1
Q = Q0
0 0 1 1 0
0 1 0 0 1
R 1
Q=0
0 0 1 1 0 1
Q 1 0 0 1 0
Q=1
1 0 1 1 0
1 1 0 0 0 Q = Q’
S Q
1 10
LATCHES
S R Q0 Q Q’
SR Latch 0 0 0 0 1
Q = Q0
0 0 1 1 0
0 1 0 0 1
R 1
Q=0
10 0 1 1 0 1
Q 1 0 0 1 0
Q=1
1 0 1 1 0
1 1 0 0 0 Q = Q’
1 1 1 0 0 Q = Q’
S Q
1 0
SR LATCH
S R Q
R Q Q0 No change
0 0
0 1 0 Reset
1 0 1 Set
S Q 1 1 Q=Q’=0 Invalid
S S R Q
Q
0 0 Q=Q’=1 Invalid
0 1 1 Set
1 0 0 Reset
R Q
1 1 Q0 No change
SR LATCH
S R Q
R Q Q0 No change
0 0
0 1 0 Reset
1 0 1 Set
S Q 1 1 Q=Q’=0 Invalid
S S’ R’ Q
Q Invalid
0 0 Q=Q’=1
0 1 1 Set
Q 1 0 0 Reset
R Q0 No change
1 1
CONTROLLED LATCHES
SR Latch with Control Input
R R S S
Q Q
C C
S Q R Q
S R
C S R Q
0 x x Q0 No change
1 0 0 Q0 No change
1 0 1 0 Reset
1 1 0 1 Set
1 1 1 Q=Q’ Invalid
CONTROLLED LATCHES
Timing Diagram
D Latch (D = Data)
C
D S
Q
D
C
R Q Q
t
C D Q
Output may
0 x Q0 No change
change
1 0 0 Reset
1 1 1 Set
CONTROLLED LATCHES
Timing Diagram
D Latch (D = Data)
D S C
Q
C D
R Q
Q
C D Q Output may
0 x Q0 No change change
1 0 0 Reset
1 1 1 Set
GRAPHIC SYMBOLS FOR LATCHES
LEVEL VERSUS EDGE SENSITIVITY
Since the output of the D latch is controlled by the
level (0 or 1) of the clock input, the latch is said to be
level sensitive
All of the latches we have seen have been level
sensitive
It is possible to design a storage element for which
the output only changes a the point in time when the
clock changes from one value to another
Such circuits are said to be edge triggered
FLIP-FLOPS
Controlled latches are level-triggered
Flip-Flops are edge-triggered
CLK Positive Edge
CLK Negative Edge
FLIP-FLOPS
Master-Slave D Flip-Flop
D D Q D Q Q
D Latch D Latch
(Master) (Slave)
C C
Master Slave
CLK CLK
D
Looks like it is negative
edge-triggered QMaster
QSlave
FLIP-FLOPS
The circuit samples the D input and changes its
output at the negative edge of the clock, CLK.
When the clock is 0, the output of the inverter is 1.
The slave latch is enabled and its output Q is equal to
the master output Y. The master latch is disabled
(CLK = 0).
When the CLK changes to high, D input is transferred
to the master latch. The slave remains disabled as
long as CLK is low. Any change in the input changes
Y,but not Q.
The output of the flip-flop can change when CLK
makes a transition 1 → 0
FLIP-FLOPS
Edge-Triggered D Flip-Flop
D Q
Q
Q
CLK Positive Edge
Q
D Q
D
Q
Negative Edge
FLIP-FLOPS:
EDGE-TRIGGERED D FLIP-FLOP
FLIP-FLOPS
If D = 0 when CLK turns from 0 to 1, R → 0, Q = 0:
‘reset state’
If D changes while CLK is high →flip-flop will not
respond to the change.
When CLK turns from 1 to 0, Q = 0: , R → 1, flip-flop
will be in the same state (no change in output).
If D = 1 when CLK from 0 to 1, S →0, Q = 1: ‘set
state’
FLIP-FLOPS
JK Flip-Flop
J
D Q Q
K
CLK Q Q
J Q
D = JQ’ + K’Q
K Q
FLIP-FLOPS
JK Flip-Flop : D = JQ’ + K’Q
When J = 1 and K = 0, D = 1 → next clock edge sets
output to 1.
When J = 0 and K = 1, D = 0 → next clock edge
resets output to 0.
When J = 1 and K = 1, D= Q’ → next clock edge
complements output.
When J = 0 and K = 0, D= Q → next clock edge
leaves output unchanged.
FLIP-FLOPS
T Flip-Flop
T J Q T D Q
Q
K Q
T Q
D = JQ’ + K’Q
D = TQ’ + T’Q = T Q Q
FLIP-FLOP CHARACTERISTIC TABLES
D Q D Q(t+1)
0 0 Reset
Q 1 1 Set
J K Q(t+1)
J Q 0 0 Q(t) No change
0 1 0 Reset
K Q 1 0 1 Set
1 1 Q’(t) Toggle
T Q T Q(t+1)
0 Q(t) No change
Q 1 Q’(t) Toggle
FLIP-FLOP CHARACTERISTIC EQUATIONS
D Q D Q(t+1)
0 0 Q(t+1) = D
Q 1 1
J K Q(t+1)
J Q 0 0 Q(t)
0 1 0 Q(t+1) = JQ’ + K’Q
K Q 1 0 1
1 1 Q’(t)
T Q T Q(t+1)
0 Q(t) Q(t+1) = T Q
Q 1 Q’(t)
FLIP-FLOPS WITH DIRECT INPUTS
Asynchronous Reset
D Q R’ D CLK Q(t+1)
0 x x 0
Q 1 0 ↑ 0
R 1 1 ↑ 1
Reset
FLIP-FLOPS WITH DIRECT INPUTS
Asynchronous Reset
FLIP-FLOPS WITH DIRECT INPUTS
Asynchronous Preset and Clear
Preset
PR PR’ CLR’ D CLK Q(t+1)
D Q 1 0 x x 0
0 1 x x 1
Q 1 1 0 ↑ 0
CLR 1 1 1 ↑ 1
Reset
ANALYSIS OF CLOCKED SEQUENTIAL CIRCUITS:
THE STATE
State = Values of all Flip-Flops
Example
x
AB=00 D Q A
D Q B
CLK Q
y
ANALYSIS OF CLOCKED SEQUENTIAL CIRCUITS:
TERMINOLOGY
State Equation: A state equation (transition equation)
specifies the next state as a function of the present
state and inputs.
State Table: A state table (transition table) consists
of: present state, input, next state and output.
State Diagram: The information in a state table can
be represented graphically in a state diagram. The
state is represented by a circle and the transitions
between states are indicated by directed lines
connecting the circles.
ANALYSIS OF CLOCKED SEQUENTIAL CIRCUITS:
STATE/TRANSITION EQUATIONS
x
A(t+1) = DA D Q A
= A(t) x(t)+B(t) x(t)
Q
=Ax+Bx
B(t+1) = DB
= A’(t) x(t) D Q B
= A’ x CLK Q
y(t) = [A(t)+ B(t)] x’(t)
= (A + B) x’ y
ANALYSIS OF CLOCKED SEQUENTIAL CIRCUITS:
STATE /TRANSITION TABLE
x
Present Next D Q A
Input Output
State State
Q
A B x A B y
0 0 0 0 0 0
D Q B
0 0 1 0 1 0
0 1 0 0 0 1 CLK Q
0 1 1 1 1 0 y
1 0 0 0 0 1
1 0 1 1 0 0
1 1 0 0 0 1 A(t+1) = A x + B x
1 1 1 1 0 0 B(t+1) = A’ x
y(t) = (A + B) x’
t t+1 t
ANALYSIS OF CLOCKED SEQUENTIAL CIRCUITS:
STATE/TRANSITION TABLE
x
Present Next State Output D Q A
State x=0 x=1 x=0 x=1 Q
A B A B A B y y
0 0 0 0 0 1 0 0 D Q B
0 1 0 0 1 1 1 0
CLK Q
1 0 0 0 1 0 1 0
1 1 0 0 1 0 1 0 y
t t+1 t A(t+1) = A x + B x
B(t+1) = A’ x
y(t) = (A + B) x’
ANALYSIS OF CLOCKED SEQUENTIAL CIRCUITS:
STATE DIAGRAM
Present Next State Output
State x=0 x=1 x=0 x=1
AB input/output A B A B A B y y
0 0 0 0 0 1 0 0
0 1 0 0 1 1 1 0
0/0 1/0
1 0 0 0 1 0 1 0
0/1 1 1 0 0 1 0 1 0
00 10
x
D Q A
0/1 Q
1/0 0/1 1/0
D Q B
CLK Q
01 11
y
1/0 42
ANALYSIS OF CLOCKED SEQUENTIAL CIRCUITS:
D FLIP-FLOPS
Example:
x D Q A
Present Next y
Input
State State CLK Q
A x y A
0 0 0 0
0 0 1 1 A(t+1) = DA = A x y
0 1 0 1
0 1 1 0
1 0 0 1 01,10
1 0 1 0
00,11 0 1 00,11
1 1 0 0
1 1 1 1 01,10
ANALYSIS OF CLOCKED SEQUENTIAL CIRCUITS:
JK FLIP-FLOPS
J Q A
Example: x K Q
Present Next Flip-Flop
I/P J Q B
State State Inputs
A B x A B JA KA JB KB K Q
0 0 0 0 1 0 0 1 0 CLK
0 0 0 0 0 1
0 0 1 JA = B KA = B x’
0 1 0 1 1 1 1 1 0
JB = x’ KB = A x
0 1 1 1 0 1 0 0 1
1 0 0 1 1 0 0 1 1 A(t+1) = JA Q’A + K’A QA
1 0 1 1 0 0 0 0 0 = A’B + AB’ + Ax
1 1 0 0 0 1 1 1 1 B(t+1) = JB Q’B + K’B QB
1 1 1 1 1 1 0 0 0 = B’x’ + ABx + A’Bx’
ANALYSIS OF CLOCKED SEQUENTIAL CIRCUITS:
JK FLIP-FLOPS J Q A
Example: x K Q
Present Next Flip-Flop J Q B
I/P
State State Inputs
A B x A B JA KA JB KB K Q
0 0 0 0 1 0 0 1 0 CLK
0 0 1 0 0 0 0 0 1 1 0 1
0 1 0 1 1 1 1 1 0 00 11
0 1 1 1 0 1 0 0 1
0
1 0 0 1 1 0 0 1 1 0 0
1 0 1 1 0 0 0 0 0
1 1 0 0 0 1 1 1 1 01 10
1 1 1 1 1 1 0 0 0 1
1
ANALYSIS OF CLOCKED SEQUENTIAL CIRCUITS:
T FLIP-FLOPS x T Q
A
y
Example: R Q
Present Next F.F
I/P O/P
State State Inputs T Q
B
A B x A B TA TB y
R Q
0 0 0 0 0 0 0 0
0 0 1 0 1 0 1 0 CLK Reset
0 1 0 0 1 0 0 0
TA = B x TB = x
0 1 1 1 0 1 1 0
y =AB
1 0 0 1 0 0 0 0
1 0 1 1 1 0 1 0
A(t+1) = TA Q’A + T’A QA
= AB’ + Ax’ + A’Bx
1 1 0 1 1 0 0 1
1 1
B(t+1) = TB Q’B + T’B QB
1 1 1 0 0 1
=xB
ANALYSIS OF CLOCKED SEQUENTIAL CIRCUITS:
T FLIP-FLOPS x T Q
A
y
Example: R Q
Present Next F.F
I/P O/P
State State Inputs T Q
B
A B x A B TA TB y
R Q
0 0 0 0 0 0 0 0
0 0 1 0 1 0 1 0 CLK Reset
0 1 0 0 1 0 0 0 0/0 0/0
0 1 1 1 0 1 1 0 00 1/0 01
1 0 0 1 0 0 0 0
1 0 1 1 1 0 1 0 1/1 1/0
1 1 0 1 1 0 0 1 11 10
1 1 1 0 0 1 1 1 0/1 0/0
1/0
PRACTICE
A sequential circuit with two D flip-flops A and B. two
inputs x and y, and one output z is specified by the
following next-state and output equations
A(t + 1) = x ’y + x B
B(t + 1 ) = x ’A + x B
z=B
Draw the logic diagram of the circuit.
List the stale table for the sequential circuit.
Draw the corresponding state diagram.
PRACTICE
PRACTICE
PRACTICE
