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Experiment: 06: AIM: To Design and Simulate Ring Oscillator Using Cadence and Compare The Delay Between

A 3-stage ring oscillator circuit was designed and simulated using Cadence Virtuso 180nm technology. The ring oscillator contains 3 inverters connected in a loop, with the output of the last inverter feeding back to the input of the first. Simulation results showed a delay of 33ns between the input and output waveforms. Ring oscillators are commonly used as frequency synthesizers and to introduce delays in circuits.

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Uttkarsh Singh
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535 views3 pages

Experiment: 06: AIM: To Design and Simulate Ring Oscillator Using Cadence and Compare The Delay Between

A 3-stage ring oscillator circuit was designed and simulated using Cadence Virtuso 180nm technology. The ring oscillator contains 3 inverters connected in a loop, with the output of the last inverter feeding back to the input of the first. Simulation results showed a delay of 33ns between the input and output waveforms. Ring oscillators are commonly used as frequency synthesizers and to introduce delays in circuits.

Uploaded by

Uttkarsh Singh
Copyright
© © All Rights Reserved
We take content rights seriously. If you suspect this is your content, claim it here.
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Download as DOCX, PDF, TXT or read online on Scribd
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EXPERIMENT : 06

AIM : To design and simulate Ring Oscillator using Cadence and compare the delay between
input and output waveform .

TOOL USED : Cadence Virtuso

TECHNOLOGY USED : gpdk 180nm

THEORY :

A ring oscillator is a device composed of an odd number of NOT gates in a ring, whose output
oscillates between two voltage levels, representing true and false. The NOT gates, or inverters,
are attached in a chain and the output of the last inverter is fed back into the first. Each inverter
has intrinsic propagation delay and the output appears after finite time period.

Fig. 6.1 : 3-stage ring oscillator

OBSERVATION :

GIVEN SPECIFICATIONS :
Paramaters Value
PMOS W=8 µm , L=180 µm
NMOS W=4 µm , L=180 µm
VDD 1.8V
INPUT Vmax = 1.8 V, Vmin = 0 V, Time Period=100 ns, Pulse Width = 49.99 ns
Rise Time = 1 ps, Fall Time = 1ps
CLOCK Vmax = 1.8 V, Vmin = 0 V, Time Period=200 ns, Pulse Width = 99.99 ns
Rise Time = 1 ps, Fall Time = 1ps
Cload 1 pf

OBSERVATION TABLE:

Paramaters Value
Delay of output w.r.t. Input 33 ns
OUTPUT WAVEFORMS:

Fig 6.2 : 3 – stage Ring Oscillator using 3 NOT gate symbols

Fig. 6.3 : Ring Oscillator symbolic representation

Fig. 6.4 : Transient Analysis


RESULTS:

3 stage ring oscillator has been designed using Cadence Virtuso tool and verified successfully.

APPLICATIONS:

1.) Ring Oscillators are used as frequency synthesiser.


2.) Ring Oscillators find application in increase delays in circuit and are also widely used as
primary oscillators in many circuits .

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