VLSI Design

Chapter 3

CMOS Process Technology

Jin-Fu Li
 Chapter 3 CMOS Process Technology

• Silicon Semiconductor Technology

• Basic CMOS Technology
• Layout Design Rules
• Latchup

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 MOS Transistor – Basic Structure

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 MOS Transistor – Basic Structure

• Oxidation:
− Wet oxidation: use water vapor 900oC ~ 1000oC,
rapid
− Dry oxidation: use pure oxygen 1200oC,
acceptable growth rate
• Oxide
− Field oxide: thick for isolation purpose
− Gate oxide: thin Oxide. As thin as possible

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 Process Technology

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 Process Technology

Patterning Implant or n+ n+

SiO2 Layer Diffusion Implant of

p-substrate p-substrate
Impurities
Thin Oxide

SiO2 by
Gate Contact n+ n+
deposition
Oxidation Cuts
p-substrate p-substrate
Polysilicon
Al contacts

Patterning n+ n+
Patterning
Polysilicon
p-substrate Al Layer
p-substrate

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 CMOS Process Technology – nWell (1)
Cross Section of Physical Structure Mask (top view)

n-well mask

n-well
p-substrate
n-well

active mask

nitride
oxide

n-well
p-substrate
Active

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 CMOS Process Technology – nWell (2)
Implant (Boron) Resist

channel stop mask

p-channel
stop

n-well
p-substrate
Channel stop

n-well
p-substrate

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 CMOS Process Technology – nWell (3)
polysilicon mask

n-well
p-substrate
polysilicon

n+ mask

n+ n+
n-well
p-substrate
n+ mask

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 CMOS Process Technology – nWell (4)
Light implant heavier implant

oxide
poly poly

n- n- n- n-
n+ n+
Shadow drain implant LDD structure

p+ mask

n+ n+ p+ p+
n-well
p-substrate
p+ mask

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 CMOS Process Technology – nWell (5)
contact mask

n+ n+ p+ p+
n-well
p-substrate
contact mask

metal mask

n+ n+ p+ p+
n-well
p-substrate
metal mask

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CMOS Process Technology – Inverter (1)
in

out
Vdd Vss

in

out

Vdd Vss

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CMOS Process Technology – Inverter (2)

p+ p+ n+ n+

n-well

p-substrate

polysilicon metal gate oxide field oxide

contact cut

p+ p+ n+ n+

n-well
p-substrate

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 Multi-Layer Metal

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 Design Rules

• Interface between designer and process

engineer
• Guidelines for constructing process masks
• Unit dimension: minimum line width
− Scalable design rules: lambda parameter
∗ 1 lambda=half the minimum poly width
− Absolute dimensions: micron rules

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 Intra-Layer Design Rules

Same Potential Different Potential

9 2
0
Well or Polysilicon
6
10 2
3 3
Active Metal1
Contact
or Via 2
3 Hole 3
2 2
Select

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 Transistor Layout

Transistor
1

3 2

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 Vias and Contacts
2
4
Via
1 1
5
Metal to
Metal to Poly Contact
1
Active Contact 3 2

2
2

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 Select Layer
2
Select
3
2

1
3 3

2 5

Well
Substrate

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 Design Rule Checker

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 Guard Rings

Vdd

emitter
p+
p-plus
n-plus

n+
n-plus base
N-well collector
(substrate)

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 Latchup
Vdd

p+ n+ n+ p+ p+ n+
NPN PNP
Rwell

Rsubstrate

2.0mA
Rwell

I ramp

Trigger point
Rsubstrate
I ramp

-0 0 1 2 3 4 Holding Voltage

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 Latchup Prevention

• Latchup resistant CMOS process

− Reduce the sheet resistance of well and
substrate, or reduce the gain of parasitic
transistor
• Layout technique
− Place multiple well contacts to reduce well
resistance

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