1

Memory Management:

From Absolute Addresses

to Demand Paging

Joel Emer

Computer Science and Artificial Intelligence Laboratory

M.I.T.

Based on the material prepared by

Arvind and Krste Asanovic

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Memory Management

• The Fifties
- Absolute Addresses

- Dynamic address translation

• The Sixties

- Paged memory systems and TLBs

- Atlas’ Demand paging

• Modern Virtual Memory Systems

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Names for Memory Locations

Address Physical
ISA Memory
machine virtual Mapping physical
language address address (DRAM)
address

• Machine language address

– as specified in machine code
• Virtual address
– ISA specifies translation of machine code address
into virtual address of program variable (sometime
called effective address)
• Physical address

⇒ operating system specifies mapping of virtual

address into name for a physical memory location
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Absolute Addresses
EDSAC, early 50’s
virtual address = physical memory address

• Only one program ran at a time, with

unrestricted access to entire machine (RAM +
I/O devices)
• Addresses in a program depended upon where
the program was to be loaded in memory
• But it was more convenient for programmers

to write location-independent subroutines

How could location independence be achieved?

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Dynamic Address Translation

Motivation
In the early machines, I/O operations were slow
and each word transferred involved the CPU

Physical Memory
Higher throughput if CPU and I/O of 2 or more
programs were overlapped. How? prog1
⇒ multiprogramming

Location independent programs

Programming and storage management ease
⇒ need for a base register

Protection prog2
Independent programs should not affect

each other inadvertently

⇒ need for a bound register

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Simple Base and Bound Translation

Segment Length
Bound Bounds
Register ≤ Violation?

Main Memory
Physical current
Load X Effective Address segment
Address +

Base
Register
Base Physical Address
Program
Address
Space

Base and bounds registers are visible/accessible only

when processor is running in the supervisor mode
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Separate Areas for Program and Data

Bounds
Data Bound
Register
≤ Violation?
data
Effective Addr
Load X Register segment

Main Memory
Data Base
Register +

Program
Program Bound Bounds
Address Register ≤ Violation?
Space Program program
Counter segment
Program Base
Register +

What is an advantage of this separation?

(Scheme still used today on Cray vector supercomputers)
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Memory Fragmentation

Users 4 & 5 Users 2 & 5 free

OS arrive OS leave
OS
Space Space Space
user 1 16K user 1 16K 16K
user 1
user 2 24K user 2 24K 24K
user 4 16K
24K user 4 16K
8K 8K
user 3 32K user 3 32K user 3 32K

24K user 5 24K 24K

As users come and go, the storage is “fragmented”.

Therefore, at some stage programs have to be moved
around to compact the storage.
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Paged Memory Systems

• Processor generated address can be

interpreted as a pair <page number, offset>
page number offset
• A page table contains the physical address

of the base of each page

1
0 0 0
1 1
2 2
3 3 3
Address Space Page Table
of User-1 2
of User-1

Page tables make it possible to store the

pages of a program non-contiguously.
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Private Address Space per User

OS
User 1 VA1

Memory
Physical
pages
Page Table

User 2 VA1

Page Table

User 3 VA1

Page Table free

• Each user has a page table

• Page table contains an entry for each user page
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Where Should Page Tables Reside?

• Space required by the page tables (PT) is

proportional to the address space, number
of users, ...
⇒ Space requirement is large
⇒ Too expensive to keep in registers

• Idea: Keep PT of the current user in special

registers
– may not be feasible for large page tables
– Increases the cost of context swap

• Idea: Keep PTs in the main memory

– needs one reference to retrieve the page base address

and another to access the data word
⇒ doubles the number of memory references!

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Page Tables in Physical Memory

PT User 1

VA1
PT User 2
User 1

VA1

User 2

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A Problem in Early Sixties

• There were many applications whose data

could not fit in the main memory, e.g., payroll
– Paged memory system reduced fragmentation but still
required the whole program to be resident in the main
memory

• Programmers moved the data back and forth

from the secondary store by overlaying it
repeatedly on the primary store

tricky programming!

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Manual Overlays
• Assume an instruction can address all

the storage on the drum

40k bits
main
• Method 1: programmer keeps track of
addresses in the main memory and
initiates an I/O transfer when required 640k bits
drum
• Method 2: automatic initiation of I/O Central Store
transfers by software address
translation Ferranti Mercury
1956
Brooker’s interpretive coding, 1960

Problems?
Method1: Difficult, error prone
Method2: Inefficient
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Demand Paging in Atlas (1962)

“A page from secondary

storage is brought into the
primary storage whenever
it is (implicitly) demanded
by the processor.”
Tom Kilburn Primary
32 Pages
512 words/page

Primary memory as a cache

for secondary memory Secondary
Central (Drum)
User sees 32 x 6 x 512 words Memory 32x6 pages
of storage

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Hardware Organization of Atlas

Effective 16 ROM pages system code
Initial 0.4 ~1 µsec (not swapped)
Address
Address
Decode 2 subsidiary pages system data
PARs 1.4 µsec (not swapped)
0
48-bit words
512-word pages Main Drum (4)
8 Tape decks
32 pages 192 pages
88 sec/word
1.4 µsec
1 Page Address
31
Register (PAR)
<effective PN , status>
per page frame

Compare the effective page address against all 32 PARs

match ⇒ normal access
no match ⇒ page fault
save the state of the partially executed
instruction

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Atlas Demand Paging Scheme

• On a page fault:
– Input transfer into a free page is initiated

– The Page Address Register (PAR) is updated

– If no free page is left, a page is selected to be

replaced (based on usage)

– The replaced page is written on the drum

• to minimize drum latency effect, the first empty
page on the drum was selected

– The page table is updated to point to the new

location of the page on the drum

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Caching vs. Demand Paging

secondary
memory

primary primary
CPU cache CPU
memory memory

Caching Demand paging

cache entry page-frame
cache block (~32 bytes) page (~4K bytes)
cache miss (1% to 20%) page miss (<0.001%)
cache hit (~1 cycle) page hit (~100 cycles)
cache miss (~100 cycles) page miss(~5M cycles)
a miss is handled a miss is handled
in hardware mostly in software

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Five-minute break to stretch your legs

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Modern Virtual Memory Systems

Illusion of a large, private, uniform store

Protection & Privacy OS
several users, each with their private
address space and one or more
shared address spaces useri
page table ≡ name space
Swapping
Demand Paging Store
Provides the ability to run programs Primary
larger than the primary memory Memory

Hides differences in machine

configurations

The price is address translation on

each memory reference VA

mapping PA
TLB
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Linear Page Table

Data Pages
• Page Table Entry (PTE) Page Table
contains: PPN
PPN
– A bit to indicate if a page DPN
exists PPN
– PPN (physical page Data word
number) for a memory-
resident page
Offset
–
DPN (disk page number) for
a page on the disk

DPN
–
Status bits for protection
PPN
and usage PPN
• OS sets the Page Table DPN
Base Register
DPN
VPN
whenever active user DPN
process changes
PPN
PPN
PT Base Register VPN Offset
Virtual address
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Size of Linear Page Table

With 32-bit addresses, 4-KB pages & 4-byte PTEs:

⇒ 220 PTEs, i.e, 4 MB page table per user

⇒ 4 GB of swap needed to back up full virtual address
space

Larger pages?

• Internal fragmentation (Not all memory in a page is

used)
• Larger page fault penalty (more time to read from disk)

What about 64-bit virtual address space???

• Even 1MB pages would require 244 8-byte PTEs (35 TB!)
What is the “saving grace” ?
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Hierarchical Page Table

Virtual Address
31 22 21 12 11 0
p1 p2 offset

10-bit 10-bit
L1 index L2 index offset
Root of the Current
Page Table p2
p1

(Processor Level 1
Register) Page Table

Level 2
page in primary memory Page Tables
page in secondary memory

PTE of a nonexistent page

Data Pages
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Address Translation & Protection

Virtual Address Virtual Page No. (VPN) offset

Kernel/User Mode

Read/Write
Protection Address
Check Translation

Exception?
Physical Address Physical Page No. (PPN) offset

• Every instruction and data access needs address

translation and protection checks

A good VM design needs to be fast (~ one cycle) and

space efficient
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Translation Lookaside Buffers

Address translation is very expensive!

In a two-level page table, each reference

becomes several memory accesses

Solution: Cache translations in TLB

TLB hit ⇒ Single Cycle Translation

TLB miss ⇒ Page Table Walk to refill

virtual address VPN offset

VRWD tag PPN (VPN = virtual page number)

(PPN = physical page number)

hit? physical address PPN offset

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TLB Designs
• Typically 32-128 entries, usually fully associative
– Each entry maps a large page, hence less spatial locality
across pages Î more likely that two entries conflict
– Sometimes larger TLBs (256-512 entries) are 4-8 way set-
associative
• Random or FIFO replacement policy

• No process information in TLB?

• TLB Reach: Size of largest virtual address space
that can be simultaneously mapped by TLB

Example: 64 TLB entries, 4KB pages, one page per entry

TLB Reach = _____________________________?

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Variable Sized Page Support

Virtual Address
31 22 21 12 11 0
p1 p2 offset

10-bit 10-bit
L1 index L2 index offset
Root of the Current
Page Table p2
p1

(Processor Level 1
Register) Page Table

Level 2
page in primary memory
Page Tables
large page in primary memory
page in secondary memory
PTE of a nonexistent page
Data Pages
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Variable Size Page TLB

Some systems support multiple page sizes.

virtual address VPN offset

V R WD Tag PPN L

hit?

physical address PPN offset

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Handling A TLB Miss

Software (MIPS, Alpha)

TLB miss causes an exception and the operating system
walks the page tables and reloads TLB. A privileged
“untranslated” addressing mode used for walk

Hardware (SPARC v8, x86, PowerPC)

A memory management unit (MMU) walks the page
tables and reloads the TLB

If a missing (data or PT) page is encountered during the

TLB reloading, MMU gives up and signals a Page-Fault
exception for the original instruction

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Hierarchical Page Table Walk:

Emer

SPARC v8
Virtual Address Index 1 Index 2 Index 3 Offset
31 23 17 11 0
Context Context Table
Table
Register L1 Table
root ptr
Context
Register L2 Table
PTP L3 Table
PTP

PTE

31 11
Physical Address 0 PPN Offset

MMU does this table walk in hardware on a TLB miss

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Translation for Page Tables

• Can references to page tables TLB miss
• Can this go on forever?

User PTE Base

User Page Table
(in virtual space)

System PTE Base

System Page Table
(in physical space)

Data Pages
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Address Translation: Emer

putting it all together

Virtual Address
hardware
hardware or software
TLB software
Lookup
miss hit

Page Table Protection

Walk Check
the page is
∉ memory ∈ memory denied permitted

Page Fault
Update TLB Protection Physical
(OS loads page) Address
Fault
(to cache)
Where? SEGFAULT
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Thank you !