+

KT14203

Computer
Architecture
and
Organization

Presented by:
Dr. Mohd Hanafi Ahmad Hijazi
SKTM, UMS
Slides, with minor modifications, taken from
William Stallings Computer Organization and
Architecture, 10th Edition
+ Preface
Introduction to KT14203
+
Outline

 Aim.

 Course outcomes.

 Delivery.

 Assessment.

 Semester’s content.
 Aim | Course Outcomes | Delivery | Assessment | Content

+
Aim

 To enable student to explore the architecture of computer

systems and technology behind the computer design.
 Aim | Course Outcomes | Delivery | Assessment | Content

+
Course Learning Outcomes

1. To explain the fundamental concept of computer

architecture and organization of a machine – PLO1
(Knowledge)

2. To apply the fundamental concept of computer architecture

and organization to solve problems on study cases
provided – PLO1 (Knowledge)

3. To follow instructions to implement CPU and assembly

programming to solve problems on study cases provided –
PLO2 (Practical skills)
 Aim | Course Outcomes | Delivery | Assessment | Content

+
Delivery

 Lecture:
 Monday, 08:00 – 10:00, DKP27.

 Tutorial:
 Tuesday, 14:00-15:00 (BT5), 15:00-16:00 (BT5).

 Lab: Tuesday, 14:00-16:00 or Thursday or Friday (14:00-

16:00)

 Office hours for consultation (by appointment):

 Monday, 10:00 – 11:00.
 Tuesday, 10:00 – 11:00.
 Thursday, 09:00 – 10:00.

 Email: hanafi@ums.edu.my
 Aim | Course Outcomes | Delivery | Assessment | Content

+
Assessment

 Labs: 10%

 Quizzes: 5%

 Assignments: 25%

 Mid-term/ test: 20%

 Final exam: 40%

 Aim | Course Outcomes | Delivery | Assessment | Content

+
Semester’s Content

 Topic 1: Introduction: Function and Structures

 Topic 2: Computer Evolution and Performance
 Topic 3: Computer Function and Interconnection
 Topic 4: Memory: Cache Memory
 Topic 5: Internal Memory (RAM, ROM)
 Topic 6: External Memory (RAID Technology)
 Topic 7: Input/Output: External Devices, I/O, Interrupt-Driven I/O,
Direct Memory Access, I/O Channel
 Topic 8: Computer Arithmetic: ALU, Integer Presentation and
Arithmetic
 Topic 9: CPU Instruction Set: Characteristics and Function
 Topic 10: CPU Instruction Set: Addressing Modes and Formats
 Topic 11: CPU Structure and Function: Structure
 Topic 12: CPU Structure and Function: Function
+
Delivery Plan
Week TOPICS TASKS Deadline
1 Introduction: Function and Structures
2 Computer Evolution and Performance Tutorial 1
Lab 1 Tut - Intro
3 Computer Function and Interconnection
CPUSim
Lab 2 Tut -
4 Memory: Cache Memory Assignment 1 issued
CPUSim Exercise
5 Internal Memory (RAM, ROM) Tutorial 2, Quiz 1
Lab 2 Exercise: Submit CD
6 External Memory (RAID Technology) Tutorial 3, Quiz 2
and report
Assignment 1: Submit CD
7 Mid Test Tutorial 4
and report
Mid Term Break
Input/Output: External Devices, I/O, Interrupt-
8 Tutorial 5, Quiz 3
Driven I/O, Direct Memory Access, I/O Channel
Computer Arithmetic: ALU, Integer Presentation
9 Tutorial 6 Assignment 2 issued
and Arithmetic
CPU Instruction Set: Characteristics and
10 Tutorial 7, Quiz 4
Function
CPU Instruction Set: Addressing Modes and
11 Tutorial 8
Formats
Lab 3 Tut - Intro
12 CPU Structure and Function: Structure / Test Assignment 2 deadline
PCSpim
Lab 4 Tut –
13 CPU Structure and Function: Function
PCSpim exercise
Lab 5 Tut – Lab 4 Exercise: Submit
14 Revision
PCSpim CD and report
+
Some minor requirement

 Please download HP Reveal App from PlayStore or

AppleStore

 Open the app, search for ‘hanafi.ums’ user

 Click ‘Follow’ to follow hanafi.ums

TEST ME!!
+
Any questions?
+ Chapter 1
Introduction
+
Why study COA?

 IEEE/ACM Computer Science Curriculum lists computer

architecture as compulsory core subject.

 Comp. science professional should not regards the computer

just as a black box.

 To make best use of software tools and computer languages

to create programs, such as:
 System architecture (cache and bus level)
 Trade-offs between components of a computer
 Topic 7 Topics 4-6

Topic 3

X+Y
Topic 9;
Topics 10-11
Computer Architecture
Computer Organization
• Attributes of a system • Instruction set, number of
visible to the bits used to represent
programmer various data types, I/O
• Have a direct impact on mechanisms, techniques
the logical execution of a for addressing memory
program

Architectural
Computer
attributes
Architecture
include:

Organizational
Computer
attributes
Organization
include:

• Hardware details • The operational units and

transparent to the their interconnections
programmer, control that realize the
signals, interfaces architectural
between the computer specifications
and peripherals, memory
technology used
+
IBM System
370 Architecture
 IBM System/370 architecture
 Was introduced in 1970
 Included a number of models
 Could upgrade to a more expensive, faster model without having to
abandon original software
 New models are introduced with improved technology, but retain the
same architecture so that the customer’s software investment is
protected
 Architecture has survived to this day as the architecture of IBM’s
mainframe product line
+
Structure and Function

 Hierarchical system
 Structure
 Set of interrelated
 The way in which
subsystems
components relate to each
 Hierarchical nature of complex other
systems is essential to both
 Function
their design and their
description  The operation of individual
components as part of the
 Designer need only deal with structure
a particular level of the system
at a time
 Concerned with structure
and function at each level
+
Function

 A computer can perform

four basic functions:

● Data processing
● Data storage
● Data movement
● Control
+
Operations

(a)
Data movement
+
Operations

(b)
Data storage
+
Operations

(c)
Data processing –
in storage
+
Operations

(d)
Data processing –
between storage
and external
environment
 The
Computer
Structure
+
 CPU – controls the operation of
the computer and performs its
There are four data processing functions
main structural
components  Main Memory – stores data
of the computer:  I/O – moves data between the
computer and its external
environment

 System Interconnection –
some mechanism that provides
for communication among CPU,
main memory, and I/O
+  Control Unit
CPU
 Controls the operation of the CPU
and hence the computer
Major structural
 Arithmetic and Logic Unit (ALU)
components:
 Performs the computer’s data
processing function

 Registers
 Provide storage internal to the CPU

 CPU Interconnection
 Some mechanism that provides for
communication among the control
unit, ALU, and registers
+
Multicore Computer Structure

 Central processing unit (CPU)

 Portion of the computer that fetches and executes instructions
 Consists of an ALU, a control unit, and registers
 Referred to as a processor in a system with a single processing unit

 Core
 An individual processing unit on a processor chip
 May be equivalent in functionality to a CPU on a single-CPU system
 Specialized processing units are also referred to as cores

 Processor
 A physical piece of silicon containing one or more cores
 Is the computer component that interprets and executes instructions
 Referred to as a multicore processor if it contains multiple cores

© 2016 Pearson Education, Inc., Hoboken, NJ. All rights reserved.

+
Cache Memory

 Multiple layers of memory between the processor and main

memory

 Is smaller and faster than main memory

 Used to speed up memory access by placing in the cache

data from main memory that is likely to be used in the near
future

 A greater performance improvement may be obtained by

using multiple levels of cache, with level 1 (L1) closest to the
core and additional levels (L2, L3, etc.) progressively farther
from the core

© 2016 Pearson Education, Inc., Hoboken, NJ. All rights reserved.

 MOTHERBOARD
Main memory chips

Processor
I/O chips chip

PROCESSOR CHIP

Core Core Core Core

L3 cache L3 cache

Core Core Core Core

CORE
Arithmetic
Instruction and logic Load/
logic unit (ALU) store logic

L1 I-cache L1 data cache

L2 instruction L2 data
cache cache

Figure 1.2 Simplified View of Major Elements of a Multicore Computer

© 2016 Pearson Education, Inc., Hoboken, NJ. All rights reserved.

 +

Figure 1.3
Motherboard with Two Intel Quad-Core Xeon Processors

© 2016 Pearson Education, Inc., Hoboken, NJ. All rights reserved.

 Figure 1.4

zEnterprise
EC12 Processor
Unit (PU)
Chip Diagram

© 2016 Pearson Education, Inc., Hoboken, NJ. All rights reserved.

+ Summary
Introduction

Chapter 1
 Structure
 CPU
 Computer Organization
 Main memory

 Computer Architecture  I/O

 System interconnection
 Function
 Data processing  CPU structural components
 Control unit
 Data storage
 ALU
 Data movement  Registers
 Control  CPU interconnection

 Brief overview of multicore

computer structure and cache
+
Internet Resources
- Web site for book
 http://WilliamStallings.com/COA/COA9e.html
 Links to sites of interest
 Links to sites for courses that use the book
 Errata list for book
 Information on other books by W. Stallings

 http://WilliamStallings.com/StudentSupport.html
 Math
 How-to
 Research resources
 Misc