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Advanced MIPS Pipeline Design

This document outlines the parts of an assignment to design a 5-stage pipelined RISC processor that implements the MIPS integer instruction set. The assignment involves: 1) designing the format and fields of the pipeline registers; 2) proposing hazard detection logic; 3) designing a pipeline controller finite state machine; 4) augmenting the controller to handle stalls due to cache misses; 5) designing an architecture-level schematic; and 6) writing a Verilog model and validating it through simulation.

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75 views2 pages

Advanced MIPS Pipeline Design

This document outlines the parts of an assignment to design a 5-stage pipelined RISC processor that implements the MIPS integer instruction set. The assignment involves: 1) designing the format and fields of the pipeline registers; 2) proposing hazard detection logic; 3) designing a pipeline controller finite state machine; 4) augmenting the controller to handle stalls due to cache misses; 5) designing an architecture-level schematic; and 6) writing a Verilog model and validating it through simulation.

Uploaded by

Rishabh
Copyright
© © All Rights Reserved
We take content rights seriously. If you suspect this is your content, claim it here.
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Download as PDF, TXT or read online on Scribd

MEL G642: Assignment RISC

Part-A:
You have studied in the class a five-stage pipelined architecture for the
implementation of MIPS integer instruction set. Now expand upon that
understanding by designing the format of each pipeline registers in terms of its
different fields – specifying the purpose for which each field would be used, its bit-
width and encoding scheme. Prepare a report of the same.

Part-B:
Assuming that all hazard detection and amelioration is solely the responsibility of
processor hardware, and no internal forwarding of the operands is to be
implemented in this version of the processor, propose the logic (based on your
format(s) of pipeline registers) that would identify all the data and control hazard
conditions and provide them as inputs to the pipeline controller(that you would
design in Part-C) to stall the processor and give appropriate control signals to each
pipeline register during the stall period (which may be multiple clock cycles), as well
as when no stalling is necessary.
Part-C:
Design the pipeline controller FSM (as a Mealy machine) to control the actions of
various stages of the pipeline, based on the inputs provided to it by the hazard
detection logic designed by you in Part-B of the assignment.
Part-D:
Now assume that Memory Stage of the pipeline may also not accomplish its
memory read/write operation in a single clock cycle sometimes (due to cache miss),
thereby forcing a stall. Augment the design of your pipeline controller to take care
of such situations which can stall the pipeline for an indefinite number of clock
cycles until a cache hit is reported by the Memory Stage.
Part-E:
Design and document a detailed architecture level schematic diagram for
implementing MIPS integer instruction set using your work carried out in Parts A,
B, C and D of this assignment.
Part-F:
Using your architecture level schematic designed and documented in Part-E, write
the Verilog RTL model (code) for the processor. Validate your Verilog model
through simulation.

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