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Cache Memory Addressing Explained

This document discusses the addressing schemes used in main memory and cache memory. It explains that the number of bits used to represent the address of a word in main memory can be calculated as 2^m, where m is the number of bits and 2^m is the total number of words. It also describes direct mapping, set associative mapping, and the number of bits used for the tag, index/line number, and block offset in the cache memory address.

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Ramkumar V R
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29 views2 pages

Cache Memory Addressing Explained

This document discusses the addressing schemes used in main memory and cache memory. It explains that the number of bits used to represent the address of a word in main memory can be calculated as 2^m, where m is the number of bits and 2^m is the total number of words. It also describes direct mapping, set associative mapping, and the number of bits used for the tag, index/line number, and block offset in the cache memory address.

Uploaded by

Ramkumar V R
Copyright
© © All Rights Reserved
We take content rights seriously. If you suspect this is your content, claim it here.
Available Formats
Download as DOCX, PDF, TXT or read online on Scribd

Main Memory

The number of bits (m) required to represent the address of a word (may be 8 bit,16 bit of
size) in main memory can be calculated by

2m=total number of words in main memory

The number of bits in Block offset(or word as in the lecture)=n

2n=the number of words in a block of cache (it is same as the number of words in main
memory)

Main Memory Address(m bits)


Block Address( m-n bits) block offset( n bits)

Direct Mapping
In cache memory,n bits will be block offset .It has two other set of bits called TAG and
Line No

No of bits for TAG=p

No. of blocks∈ Mainmemory


2P= =Mainmemory ¿ ¿ Cache memory ¿ ¿ ¿ ¿
No . of blocks∈Cache memory

No.of bits for Index(Line No)=q

2q=Total number of Blocks in Cache

Cache Memory Address(m bits=p+q+n)


TAG(p bits) Line Number(q bits) block offset( n bits)

SET Associative Mapping

In cache memory,n bits will be block offset .It has two other set of bits called TAG and
SET(LINE No)
If there is r way associative mapping
No.of bits for SET=x

No . of blocks∈ Mainmemory
2x=
r

No of bits for TAG(y)=m-x-n

Cache Memory Address(m bits=x+y+n)


TAG(y bits) SET (x bits) block offset( n
bits)

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