Chapter 6
Program Control Instructions
Dr. Hanal Abuzant
Brey: The Intel Microprocessors, 7e © 2006 Pearson Education, Upper Saddle River, NJ 07458. All Rights Reserved.
JMP
The JMP instruction is a GOTO that is
found in all computer languages. JMP
passes program flow to another part of the
program.
The JMP instruction comes in 3 forms,
short, near, and far.
Short jumps are within +127 and -128
bytes from the JMP instruction.
Near jumps are within ±32K.
Far jumps are anywhere within the memory
system.
Brey: The Intel Microprocessors, 7e © 2006 Pearson Education, Upper Saddle River, NJ 07458. All Rights Reserved.
JMP stucture
Short
Near
Far
Brey: The Intel Microprocessors, 7e © 2006 Pearson Education, Upper Saddle River, NJ 07458. All Rights Reserved.
Short JMP
Brey: The Intel Microprocessors, 7e © 2006 Pearson Education, Upper Saddle River, NJ 07458. All Rights Reserved.
SATRT: MOV AX, 1
ADD AX, BX
JMP SHORT NEXT
.
.
.
.
NEXT: MOV BX,AX
JMP START
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Near JMP
0003H
0005H
Brey: The Intel Microprocessors, 7e © 2006 Pearson Education, Upper Saddle River, NJ 07458. All Rights Reserved.
SATRT: MOV AX, 1
ADD AX, BX
JMP NEXT
.
.
.
.
NEXT: MOV BX,AX
JMP START
Brey: The Intel Microprocessors, 7e © 2006 Pearson Education, Upper Saddle River, NJ 07458. All Rights Reserved.
EB: opcode for short jumb
offset
Short jmp
0E:displacement
=14 steps
abel: rset
Brey: The Intel Microprocessors, 7e © 2006 Pearson Education, Upper Saddle River, NJ 07458. All Rights Reserved.
Far JMP
Brey: The Intel Microprocessors, 7e © 2006 Pearson Education, Upper Saddle River, NJ 07458. All Rights Reserved.
SATRT: MOV AX, 1
ADD AX, BX
JMP NEXT
.
.
.
.
NEXT: MOV BX,AX
JMP FAR PTR START
JMP UP
Brey: The Intel Microprocessors, 7e © 2006 Pearson Education, Upper Saddle River, NJ 07458. All Rights Reserved.
Conditional Jumps
There are many conditional jump
instructions.
Conditional jump instructions, for the
most part, test the flag bits.
Conditional jumps can be either short
or near.
In protected mode a conditional jump
can have a 32-bit displacement.
Some check a single flag bit, while
some check multiple flag bits.
Brey: The Intel Microprocessors, 7e © 2006 Pearson Education, Upper Saddle River, NJ 07458. All Rights Reserved.
Brey: The Intel Microprocessors, 7e © 2006 Pearson Education, Upper Saddle River, NJ 07458. All Rights Reserved.
One set of conditional jumps test
unsigned numbers (JZ, JNZ, JA, JB,
JAE, or JBE).
One set of conditional jumps test
signed number (JZ, JNZ, JG, JL, JGE,
and JLE).
Two sets of conditional jumps are
needed because the numeric order of
signed and unsigned numbers differ.
(see next slide)
Brey: The Intel Microprocessors, 7e © 2006 Pearson Education, Upper Saddle River, NJ 07458. All Rights Reserved.
Indirect Jumps
Indirect jumps take two forms. One
jumps to the offset location addressed
by a register and the other jumps to
the location addressed by a memory
pointer.
JMP CX
JMP EDX
JMP NEAR PTR [BX]
JMP FAR PTR [ECX]
Brey: The Intel Microprocessors, 7e © 2006 Pearson Education, Upper Saddle River, NJ 07458. All Rights Reserved.
See page 185
Brey: The Intel Microprocessors, 7e © 2006 Pearson Education, Upper Saddle River, NJ 07458. All Rights Reserved.
Functions
In assembly language functions are
called procedures or subroutines.
The CALL instruction links to a
procedure and the RET instruction
returns from a procedure.
Procedures use a PROC directive to
start and procedure construct and the
ENDP directive to end the construct.
Brey: The Intel Microprocessors, 7e © 2006 Pearson Education, Upper Saddle River, NJ 07458. All Rights Reserved.
The Stack with CALL and
RET
CALL pushes the return address onto
the stack and RET retrieves the return
address from the stack.
The stack allows procedures to be
nested.
Brey: The Intel Microprocessors, 7e © 2006 Pearson Education, Upper Saddle River, NJ 07458. All Rights Reserved.
org 100h
mov dl,31h
start:
mov ah,2
int 21h
call delay ; call the procedure of offset 0111h then SP=SP-2 (as push IP=0109h)
inc dl ; its offset 0109h
cmp dl,35h
jb start
ret
delay: ;its offset is 0111h
mov cx,4
w:
nop
loop w
Ret ; end the procedure to return offset 0109h then SP=SP+2 (as pop IP=109h)
Brey: The Intel Microprocessors, 7e © 2006 Pearson Education, Upper Saddle River, NJ 07458. All Rights Reserved.
org 100h
mov dl,31h
mov cx,9
start:
mov ah,2
int 21h
call delay
inc dl
loop start
ret
delay:
push cx
mov cx,3
w:
nop
loop w
pop cx
ret
Brey: The Intel Microprocessors, 7e © 2006 Pearson Education, Upper Saddle River, NJ 07458. All Rights Reserved.
Offset
label proc
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Offset
label proc
Brey: The Intel Microprocessors, 7e © 2006 Pearson Education, Upper Saddle River, NJ 07458. All Rights Reserved.
MOV AX, 30
MOV BX, 40
PUSH AX
PUSH BX
CALL ADDM
ADDM PROC NEAR
PUSH BP
MOV BP, SP
MOV AX, [BP+4]
MOV AX, [BP+6]
POP BP
RET
ENDP
Brey: The Intel Microprocessors, 7e © 2006 Pearson Education, Upper Saddle River, NJ 07458. All Rights Reserved.
Emulator example
.code
start:
mov bx,0A10h
mov [2],120h
jmp [2]
mov ax,11
push ax
mov cx,5h
lo1: add ax,1
loop lo1
cmp ax,10h
jb start
re: mov ah,1
int 21h
cmp al,30h
jb re
mov dl,al
inc dl
mov ah,2
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Interrupts
Interrupts are accessed with software
through the INT instruction.
An interrupt is either a hardware call to a
procedure or a software call to a procedure.
The procedure called by the interrupt is
called a handler or an interrupt service
procedure (ISP).
Brey: The Intel Microprocessors, 7e © 2006 Pearson Education, Upper Saddle River, NJ 07458. All Rights Reserved.
Interrupts access the ISP through a
pointer or vector stored in the
interrupt vector table. Each entry is 4
bytes in length (8 bytes in protected
mode) that points to the ISP.
INT 10H access a vector stored at
address 4 * 10H or 40H. The vector is
stored at 40H, 41H, 42H, and 43H.
Later in the text a separate chapter
provides much more detain on
interrupts.
Brey: The Intel Microprocessors, 7e © 2006 Pearson Education, Upper Saddle River, NJ 07458. All Rights Reserved.
Brey: The Intel Microprocessors, 7e © 2006 Pearson Education, Upper Saddle River, NJ 07458. All Rights Reserved.
IN/OUT
if required you can read the data from port
using IN instruction, for example:
IN AX, 4
first operand of IN instruction (AX)
receives the value from port, second
operand (4) is a port number. first operand
must be AX or AL only. second operand
must be an immediate byte value (0..255)
or DX register (port number >255).
Brey: The Intel Microprocessors, 7e © 2006 Pearson Education, Upper Saddle River, NJ 07458. All Rights Reserved.
Stepper Motor
port 7 (byte):the stepper motor is
controlled by sending data to i/o port 7.
stepper motor is electric motor that can be
precisely controlled by signals from a
computer.
the motor turns through a precise angle
each time it receives a signal.
by varying the rate at which signal pulses
are produced, the motor can be run at
different speeds or turned through an
exact angle and then stopped.
Brey: The Intel Microprocessors, 7e © 2006 Pearson Education, Upper Saddle River, NJ 07458. All Rights Reserved.
This is a basic 3-phase stepper motor, it
has 3 magnets controlled by bits 0, 1 and
2. other bits (3..7) are unused.
When magnet is working it becomes red.
The arrow in the left upper corner shows
the direction of the last motor move. Green
line is here just to see that it is really
rotating.
Brey: The Intel Microprocessors, 7e © 2006 Pearson Education, Upper Saddle River, NJ 07458. All Rights Reserved.
For example, the code below will do three
clock-wise half-steps:
MOV AL, 001b ; initialize.
OUT 7, AL
MOV AL, 011b ; half step 1.
OUT 7, AL
MOV AL, 010b ; half step 2.
OUT 7, AL
MOV AL, 110b ; half step 3.
OUT 7, AL
Brey: The Intel Microprocessors, 7e © 2006 Pearson Education, Upper Saddle River, NJ 07458. All Rights Reserved.
