Scribd
Upload
84 views5 pages

Logic Gates Verilog Implementation

The document describes different models for implementing logic gates using Verilog including: 1) A dataflow model that assigns outputs of logic gates like AND, OR, NOT directly using assign statements. 2) A behavioural model that uses case statements to model the logic gate behaviour. 3) A structural model that instantiates basic gates like AND, OR, NOT as modules and connects them to model the complex logic gates. 4) A testbench module is also described to apply test vectors and simulate the models.

Uploaded by

Ravi Kiran
Copyright
© © All Rights Reserved
We take content rights seriously. If you suspect this is your content, claim it here.
Available Formats
Download as PDF, TXT or read online on Scribd
84 views5 pages

Logic Gates Verilog Implementation

The document describes different models for implementing logic gates using Verilog including: 1) A dataflow model that assigns outputs of logic gates like AND, OR, NOT directly using assign statements. 2) A behavioural model that uses case statements to model the logic gate behaviour. 3) A structural model that instantiates basic gates like AND, OR, NOT as modules and connects them to model the complex logic gates. 4) A testbench module is also described to apply test vectors and simulate the models.

Uploaded by

Ravi Kiran
Copyright
© © All Rights Reserved
We take content rights seriously. If you suspect this is your content, claim it here.
Available Formats
Download as PDF, TXT or read online on Scribd

LOGIC GATES

DATAFLOW MODEL:

module logicgates (a,b,y);


input a,b;
output [7:0]y;
assign y[7]=a&b;
assign y[6]=a|b;
assign y[5]=~(a&b);
assign y[4]=~(a|b);
assign y[3]=~a;
assign y[2]=a^b;
assign y[1]=~(a^b);
assign y[0]=a;
endmodule

BEHAVIOURAL MODEL (using case statement):


module logicgates (a,b,y);
input a,b;
output [7:0]y;
reg [7:0]y;
always@(*)
begin
case({a,b})
//and
2'b11:y[0]<=1'b1;
default:y[0]<=1'b0;
endcase
case({a,b})
//nand
2'b11:y[1]<=1'b0;
default:y[1]<=1'b1;
endcase
//or
case({a,b})
2'b00:y[2]<=1'b0;
default:y[2]<=1'b1;
endcase
//nor
case({a,b})
2'b00:y[3]<=1'b1;
default:y[3]<=1'b0;
endcase
//exor
case({a,b})
2'b00:y[4]<=0;
2'b01:y[4]<=1;
2'b10:y[4]<=1;
2'b11:y[4]<=0;
endcase
//exnor
case({a,b})
2'b00:y[5]<=1;
2'b01:y[5]<=0;
2'b10:y[5]<=0;
2'b11:y[5]<=1;
endcase
//not
case({a,b})
1'b0:y[6]<=1;
1'b1:y[6]<=0;
endcase
//buffer
case({a,b})
1'b1:y[7]<=1;
1'b0:y[7]<=0;
endcase
end
endmodule

STRUCTURAL MODEL:
Module logicgates (a,b,andout,nandout,orout,norout,xorout,xnorout,notout,bufout);
input a,b;
output andout,nandout,orout,norout,xorout,xnorout,notout,bufout;
and a1 (andout,a,b);
nand a2 (nandout,a,b);
or a3 (orout,a,b);
nor a4 (norout,a,b);
xor a5 (xorout,a,b);
xnor a6 (xnorout,a,b);
not a7 (notout,a);
buf a8 (bufout,a);
endmodule

TESTBENCH:

module logicgates_tb;
// Inputs
reg a;
reg b;
// Outputs
wire [7:0] y;
// Instantiate the Unit Under Test (UUT)
logicgates uut (
.a(a),
.b(b),
.y(y)
);
initial begin
// Initialize Inputs
a = 0;b = 0;
#10 a = 0;b = 1;
#10 a = 1; b = 0;
#10 a = 1; b = 1;
// Wait 100 ns for global reset to finish
#100;
// Add stimulus here
end
initial #100 $stop;
endmodule

You might also like