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System Design Lab-Ii: Malaviya National Institute of Technology, Jaipur

This document describes experiments conducted using Virtuoso to design and simulate various digital logic gates. In Experiment 1, a NOT gate was designed and its truth table and output were shown. Experiment 2 involved designing 2-input NAND and NOR gates along with their truth tables and outputs. Experiment 3 consisted of designing half and full adders, providing their truth tables, layouts, and outputs. The aim of all the experiments was to successfully design and simulate the given digital logic circuits using Virtuoso.

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PRAKRITI SANKHLA
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47 views11 pages

System Design Lab-Ii: Malaviya National Institute of Technology, Jaipur

This document describes experiments conducted using Virtuoso to design and simulate various digital logic gates. In Experiment 1, a NOT gate was designed and its truth table and output were shown. Experiment 2 involved designing 2-input NAND and NOR gates along with their truth tables and outputs. Experiment 3 consisted of designing half and full adders, providing their truth tables, layouts, and outputs. The aim of all the experiments was to successfully design and simulate the given digital logic circuits using Virtuoso.

Uploaded by

PRAKRITI SANKHLA
Copyright
© © All Rights Reserved
We take content rights seriously. If you suspect this is your content, claim it here.
Available Formats
Download as PDF, TXT or read online on Scribd

Malaviya National Institute Of Technology, Jaipur

SYSTEM DESIGN LAB-II


Session 2019-20

Submitted by: Submitted to:


AMISHA JAIN DR. MENKA YADAV
2016UEC1006 Assistant Professor
EXPERIMENT – 1
AIM: To design and simulate NOT gate using Virtuoso.

SOFTWARE USED: Virtuoso


DIAGRAM:

Fig 1: CMOS Circuit design of NOT gate.

TRUTH TABLE:

INPUT OUTPUT
1 0
0 1

LAYOUT:

Fig 2: CMOS implementation of NOT gate


OUTPUT:

Fig 3: Input and Output representation of NOT gate

RESULT: I have successfully designed and simulated NOT gate using virtuoso.
EXPERIMENT – 2(a)
AIM: To design and simulate 2-input NAND gate using Virtuoso.

SOFTWARE USED: Virtuoso


DIAGRAM:

Fig 1: CMOS Circuit design of 2-input NAND gate


TRUTH TABLE:
INPUT INPUT
OUTPUT
(A) (B)

0 0 1
0 1 1
1 0 1
1 1 0

LAYOUT:

Fig 2: CMOS implementation of 2-input NAND gate


OUTPUT:

Fig 3: Input and Output Implementation of 2-input NAND gate

RESULT: I have successfully designed and simulated 2-input NAND gate using
virtuoso.
EXPERIMENT – 2(b)
AIM: To design and simulate 2-input NOR gate using Virtuoso.

SOFTWARE USED: Virtuoso


DIAGRAM:

Fig 1: CMOS Circuit design of 2-input NOR gate

TRUTH TABLE:
INPUT INPUT
OUTPUT
(A) (B)
0 0 1
0 1 0
1 0 0
1 1 0
LAYOUT:

Fig 2: CMOS implementation of 2-input NOR gate


OUTPUT:

Fig 3: Input and Output Implementation of 2-input NOR gate

RESULT: I have successfully designed and simulated 2-input NOR gate using virtuoso.
EXPERIMENT – 3(a)
AIM: To design and simulate half adder using Virtuoso.

SOFTWARE USED: Virtuoso


DIAGRAM:

Fig 1: Circuit design of half adder

TRUTH TABLE:

INPUT INPUT
(A) (B) SUM CARRY

0 0 0 0
0 1 1 0
1 0 1 0
1 1 0 1
LAYOUT:

Fig 3: CMOS implementation of half adder

OUTPUT:

Fig 2: Input and Output Implementation of half adder

RESULT: I have successfully designed and simulated half adder using virtuoso.
EXPERIMENT – 3(b)
AIM: To design and simulate full adder using Virtuoso.

SOFTWARE USED: Virtuoso

DIAGRAM:

Fig 1: Circuit design of full adder

TRUTH TABLE:

INPUT INPUT INPUT CARRY


SUM
(A) (B) (Cin) OUT
0 0 0 0 0
0 0 1 1 0
0 1 0 1 0
0 1 1 0 1
1 0 0 1 0
1 0 1 0 1
1 1 0 0 1
1 1 1 1 1
LAYOUT:

Fig 3: CMOS implementation of full adder

OUTPUT:

Fig 2: Input and Output Implementation of full adder

RESULT: I have successfully designed and simulated full adder using virtuoso.

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