PG- 5103: Digital Electronics
Sample Questions
Chapter One: Digital Building Blocks
1. Draw a NAND/NOR latch, its simplified block symbol and truth table.
2. Draw simplified block symbol of a J-K flip-flop that responds only on negative edge of the
clock and also represent its truth table.
3. How can a S-C/J-K flip-flop be modified to operate as a D flip-flop.
4. Show in block diagram how can J-K FFs be used for parallel data transfer.
5. Show how can an edge-triggered D flip-flop be made to operate in the toggle mode. Apply a
1 kHz square wave to the CLK input and determine the Q wave form, assume that Q=0 initially.
6. Show one way to arrange J-K FFs to operate as 4-bit shift register and provide the wave form
as well.
7. What are the advantages of serial transfer over parallel data transfer?
8. Show how J-K FFs/clocked D FFs can be warred for a 3-bit binary up counter (MOD-8) and
provide waveforms as well.
9. Consider a counter circuit that contains six FFs.
a) Determine the counter’s MOD number.
b) Determine the frequency at the output of the last FF when input clock frequency is 1 MHz.
c) What is the range of counting states for this counter?
10. Construct a MOD-14 counter and provide wave forms in response to 1 kHz clock frequency,
show any glitches that might appear on any FF outputs.
11. Use J-K FFs and any other necessary logic to construct an appropriate MOD-60
asynchronous counter.
12. Design an asynchronous and a synchronous MOD-8 counter using J-K FFs.
13. What is the advantage of a synchronous counter over an asynchronous counter? What is
disadvantage?
14. Explain the difference between a DMUX and MUX.
15. Provide at lest 4 applications in digital system using multiplexer.
16. Design a 5x32 decoder using minimum number of 2x4 decoders with enable.
17. Design a 4x2 priority encoder with an enable pin, E (D3-D0), where D0 is the LSB and has the
highest priority; D3 has the lowest priority; E = 1 will enable the circuit.
Problems from Tocci (7th edition):
5-1, 5-3, 5-10, 5-11, 5-12, 5-14, 5-18, 5-25, 5-30, 5-31, 5-32, 7-4,7-13, 7-17, 7-19
Chapter Two: Timing Circuits
Problems from R P Jain (2nd edition):
9.9, 9.10, 9.11, 9.12, 9.13, 9.14, 9.15, 9.16
Chapter Three: A/D and D/A Converters
1. A five-bit DAC has a current output. For a digital input of 10100, an output current of 10 mA is
produced. What will IOUT be for a digital input of 11101?
2. What is the largest value of output voltage from an eight-bit DAC that produces 1.0 V for a
digital input of 00110010?
3. A five-bit DAC produces Vout = 0.2 V for a digital input of 00001. Find the value of Vout for an
input of 10001. What is the resolution (step size) of this DAC?
4. A 10-bit DAC has a step size of 10 mV. Determine the full-scale output voltage and percentage
resolution.
5. An eight-bit DAC has an output of 3.92 mA for an input of 01100010. What are the DAC’s
resolution, percentage resolution and full-scale output?
6. Consider a 12-bit DAC with BCD inputs and a resolution of 10 mV. What will its output be for
an input of 100001110011?
7. Draw the circuit diagrams of a DAC that use binary-weighted resistors and a R/2R ladder DAC.
8. What are the advantages of R/2R ladder DACs over those that use binary-weight resistors?
9. Discuss the four applications of DAC.
10. Draw the block diagram of the digital ramp ADC and describe its basic operation.
11. Assume the following values for a digital ramp ADC: clock frequency = 1 MHz; Vt = 0.1 mV;
DAC has F.S. output = 10.23 V and a 10-bit input. Determine the following values.
a) The digital equivalent obtained for VA = 3.728 V
b) The conversion time
c) The resolution of this converter
12. What is data acquisition? Draw a block diagram showing how a microcomputer is connected to a
digital-ramp ADC for the purpose of data acquisition. Describe the steps in a computer data
acquisition processes.
13. Draw the simplified block diagram and flow chart of operation of a successive approximation
ADC.
14. What is the main advantage of a SAC over a digital-ramp ADC?
Problems from Tocci (7th edition):
10-2, 10-3, 10-4, 10-5, 10-6, 10-10, 10-24, 10-30
Chapter Four: Semiconductor Memories
1. How many address inputs, data inputs and data outputs are required for a 16K×12 memory?
2. Outline the steps that take place when the CPU reads from memory.
3. Outline the steps that take place when the CPU writes to memory.
4. Describe with simplified diagram the internal architecture of a 16×8 ROM that uses a squire
register array.
5. Write short notes: MROM, PROM, EPROM and EEPROM.
6. Describe with diagram how a ROM look-up table and a DAC are used to generate a sine-wave
output signal.
7. Draw the internal organization of a 64×4 RAM.
8. The 2147H is an NMOS RAM that is organized as a 4K×1 with separate data input and output
and a single active-LOW chip select input. Draw the logic symbol for this chip, showing all pin
functions.
9. The MCM6206C is a CMOS RAM with 32K×8, common I/O pins, an active-LOW chip enable
and an active-LOW output enable. Draw the logic symbol. functions.
10. How does a static-RAM cell differ from a dynamic-RAM cell?
11. What RAM timing parameters determine its operating speed?
12. Draw the simplified architecture of a 4M×1 DRAM.
Problems from Tocci (7th edition):
11-1, 11-2, 11-3, 11-4, 11-6, 11-15, 11-23, 11-24, 11-37
Chapter Five: Programmable Logic Devices
1. What is PLD? Why it used?
2. How PROM could be programmed to generate following logic functions?
O0= A+BD+CD; O1= ABCD+ABCD; O2=ABC; O3= AB+CD
3. How does the architecture of a PAL differ from that of a PROM?
4. How PAL could be programmed to generate following logic functions?
O0= A+BD+CD; O1= ABCD+ABCD; O2=ABC; O3= AB+CD
5. Show in flow chart the steps involved in the designing, programming and testing of a PLD?
Chapter Six: Fundamentals of Microprocessors
1. List two 8-bit microprocessors with their process technology, data but width and address width.
2. List two 16-bit microprocessors with their process technology, data but width and address width.
3. Describe the functions of the three buses that are part of a typical microprocessor system.
4. Name the basic components of a microprocessor. Briefly describe each.
5. What are the flags in microprocessor? Briefly describe commonly used flags.
6. What is an op code?
7. Draw a functional block diagram of the 8085A microprocessor.
8. Name the groups of the instruction set of the 8085A microprocessor.
9. Write a program to transfer one byte of data from the memory location 0010H to 1000H.
10. Assume the contents of the accumulator and register C as 2EH and 6CH respectively. After
execution of the ADD C instruction what will the contents be of registers A, C and flags?
11. Assume the contents of the relevant memory location, registers and flags are as given bellow:
Accumulator = 3EH, Register H = 00H, Register L = 7CH, Memory location (007CH) = 9FH,
CY = 0, S = 0, P = 1, Z = 0, AC = 1. After execution of the SUB M instruction what will the
contents be of accumulator and flags?
12. Example 13.8 and Example 13.9 (R P Jain, 2nd edition)
13. Draw a functional block diagram of the 8086 microprocessor.
Problems from R P Jain (2nd edition):
13.4, 13.6, 13.7, 13.11
