CpE 487: Digital System Design

Fall 2009

Lecture 12
Package and libraries

Prof. Haibo He
Department of Electrical and Computer Engineering
Stevens Institute of Technology
Hoboken, NJ 07086

1
 Review of the previous lecture

• Subprograms
• Subprogram overloading
• Operator overloading

2
 Outline of this lecture

• Package declaration
• Package body
• Design libraries

3
 Packages

• A package provides a convenient mechanism to

store and share declarations that are common
across many design units.

– A package declaration and, optionally,

– A package body

4
 Essentials of Packages

• Package Declaration
– Declaration of the functions, procedures, and types
that are available in the package
– Serves as a package interface
– Only declared contents are visible for external use

• Items declared in a package declaration can be accessed

by other design units using the library and use clauses.

• Package body
– Implementation of the functions and procedures
declared in the package header
– Instantiation of constants provided in the package
header
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Example: Package declaration of std_logic_1164

package std_logic_1164 is
type std_ulogic is (‘U’, --Unitialized
‘X’, -- Forcing Unknown
‘0’, -- Forcing 0
‘1’, -- Forcing 1
‘Z’, -- High Impedance
‘W’, -- Weak Unknown
‘L’, -- Weak 0
‘H’, -- Weak 1
‘-’ -- Don’t care
);
type std_ulogic_vector is array (natural range <>) of std_ulogic;
function resolved (s : std_ulogic_vector) return std_ulogic;
subtype std_logic is resolved std_ulogic;
type std_logic_vector is array (natural range <>) of std_logic;
function “and” (l, r : std_logic_vector) return std_logic_vector;
--..<rest of the package definition>
end package std_logic_1164;

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 Example: Package Body

package body my_package is

--
-- type definitions, functions, and
procedures
--
end my_package;

• Package body primarily contains the behavior of the

subprograms and the values of deferred constants declared
in a package declaration.
• The package name must be the same as the name of its
corresponding package declaration.
• Packages are typically compiled into libraries

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 Essentials of Libraries

Design VHDL
File Analyzer

Library WORK Library STD Library IEEE

full_adder.vhd textio.vhd std_logic_1164.vhd

half_adder. vhd standard.vhd

.....

Sources and analyzed

design units

• Design units are analyzed (compiled) and placed in libraries

• Each design library has a logical name with which it is referenced
inside a VHDL description
• Libraries STD (packages STANDARD and TEXTIO) and WORK are
implicitly declared (pre-defined) 8
 Design Units

Primary Design Units

entity configuration package

declaration
binding

package
architecture-3 body
architecture-2
architecture-1

• Distinguish the primary and secondary design units

• Compilation order 9
 Implicit visibility

• An architecture body implicitly inherits all declarations in

the entity since it is tied to that entity by virtue of the
statement:
architecture architecture-name of entity-name is…

• A package body implicitly inherits all items declared in the

package declaration by virtue of its first statement:

package body package-name is ….

10
 Explicit visibility

• Explicit visibility of items declared in other design units

can be achieved using the following two clauses:
– library clause
– use clause

Example:

library ATT;
use ATT.TTL.all;

entity UART is
…
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 Library and use clause

Examples:
library CMOS;
use CMOS.NOR2

library IEEE;
use IEEE.STD_LOGIC_1164.STD_LOGIC;
-- std_logic is a type declared std_logic_1164 package.
-- the package std_logic_1164 is stored in the design library IEEE.

entity NAND2 is
port (A, B : in STD_LOGIC;…) ….

use IEEE.STD_LOGIC_1164.all;
-- make all items declared in package STD_LOGIC_1164 in design
library IEEE visible

use IEEE.all; 12
 Visibility Rules

library IEEE;
use IEEE.std_logic_1164.all;
entity design-1 is
.....
file.vhd

library IEEE;
use IEEE.std_logic_1164.rising_edge;
entity design-2 is
......

• When multiple design units are in the same file visibility of

libraries and packages must be established for each primary
design unit (entity, package declaration, configuration)
separately!
– Secondary design units (architecture body and package body)
derive library information from associated primary design
unit
• The use clause may selectively establish visibility, e.g., only 13the
function rising_edge() is visible within entity design-2
 Reference

The lectures notes and pictures are based on the following sources:

[1] J. Bhasker, A VHDL Primer,3rd edition, J. Bhasker, Prentice Hall, ISBN 0-13-096575-8, 1999
[2] S. Tewksbury, VHDL class notes
http://stewks.ece.stevens-tech.edu/CpE487-S05/
[2] J. V. Spiegel, VHDL tutorial.
http://www.seas.upenn.edu/~ese201/vhdl/vhdl_primer.html
[3] J. A. Starzyk, VHDL class lecture notes
http://www.ent.ohiou.edu/~starzyk/network/Class/ee515/index.html
[4] S. Yalamanchili, Introductory VHDL: From Simulation to Synthesis, Prentice Hall, ISBN 0-13-
080982-9, 2001.
[5] S. Yalamanchili, VHDL: A Starter's Guide,, Prentice Hall, ISBN: 0-13-145735-7, 2005.
[6] V. A. Pedroni, Circuit Design with VHDL,, MIT Press, ISBN: 0-262-16224-5, 2004.
[7] K. C. Chang, Digital Design and Modeling with VHDL and Synthesis, , IEEE Computer Society
Press, ISBN: 0-8186-7716-3, 1997
[8] J. M. Rabaey, A. Chandrakasan, B. Nikolic, Digital integrated circuits- a design perspective, 2nd
edition, prentice hall.

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