Lecture 19 – Differential Amplifier (6/24/14) Page 19-1

LECTURE 19 – DIFFERENTIAL AMPLIFIER

LECTURE ORGANIZATION
Outline
• Characterization of a differential amplifier
• Differential amplifier with a current mirror load
• Differential amplifier with MOS diode loads
• An intuitive method of small signal analysis
• Large signal performance of differential amplifiers
• Differential amplifiers with current source loads
• Design of differential amplifiers
• Summary
CMOS Analog Circuit Design, 3rd Edition Reference
Pages 198-217

CMOS Analog Circuit Design © P.E. Allen - 2016

Lecture 19 – Differential Amplifier (6/24/14) Page 19-2

CHARACTERIZATION OF A DIFFERENTIAL AMPLIFIER

What is a Differential Amplifier?
A differential amplifier is an amplifier that amplifies the difference between two
voltages and rejects the average or common mode value of the two voltages.
Differential and common mode voltages:
v1 and v2 are called single-ended voltages. They are voltages referenced to ac
ground.
The differential-mode input voltage, vID, is the voltage difference between v1 and v2.
The common-mode input voltage, vIC, is the average value of v1 and v2 .
v1+v2
 vID = v1 - v2 and vIC =  v1 = vIC + 0.5vID and v2 = vIC - 0.5vID
2
v1 + v2
vOUT = AVDvID ± AVCvIC = AVD(v1 - v2) ± AVC  2 
 
where
AVD = differential-mode voltage gain
AVC = common-mode voltage gain

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Lecture 19 – Differential Amplifier (6/24/14) Page 19-3

Differential Amplifier Definitions

• Common mode rejection rato (CMRR)
AVD
CMRR = A 
 VC 
CMRR is a measure of how well the differential amplifier rejects the common-mode
input voltage in favor of the differential-input voltage.
• Input common-mode range (ICMR)
The input common-mode range is the range of common-mode voltages over which
the differential amplifier continues to sense and amplify the difference signal with
the same gain.
Typically, the ICMR is defined by the common-mode voltage range over which all
MOSFETs remain in the saturation region.
• Output offset voltage (VOS(out))
The output offset voltage is the voltage which appears at the output of the differential
amplifier when the input terminals are connected together.
• Input offset voltage (VOS(in) = VOS)
The input offset voltage is equal to the output offset voltage divided by the
differential voltage gain.
VOS(out)
CMOS Analog Circuit Design
VOS = A © P.E. Allen - 2016
VD
Lecture 19 – Differential Amplifier (6/24/14) Page 19-4

Transconductance Characteristic of the Differential Amplifier

Consider the following n-channel differential VDD
amplifier (called a source-coupled pair). Where
iD1 iD2 M2 v
should bulk be connected? Consider a p-well, vG1 M1 G2
CMOS technology: v
+
v vGS2
+
D1 G1 S1 S2 G2 D2 VDD IBias ID GS1
- -
M4 M3 ISS
n+ n+ p+ n+ n+ n+
VBulk
p-well
n-substrate Fig. 5.2-2
Fig. 5.2-3

1.) Bulks connected to the sources: No modulation of VT but large common mode
parasitic capacitance.
2.) Bulks connected to ground: Smaller common mode parasitic capacitors, but
modulation of VT.
What are the implications of a large common mode capacitance?
+
R - R
vIN
vIN 0V
Little -
+ Large charging
charging of of capacitance
capacitance 070416-02
CMOS Analog Circuit Design © P.E. Allen - 2016
Lecture 19 – Differential Amplifier (6/24/14) Page 19-5

Transconductance Characteristic of the Differential Amplifier - Continued

Defining equations:
iD1 iD2
2iD1 2iD2 M1
vID = vGS1 − vGS2 =  −  and ISS = iD1 + iD2 vID
+
vGS1
M2
vGS2
+
- -
Solution: 141009-01
ISS
ISS ISS vID 2vID1/2 ISS ISS vID 2vID1/2
2 4 2 4
iD1 = 2 + 2  I − 2  and iD2 = 2 − 2  I − 2 
SS 4ISS
  SS 4ISS  
which are valid for vID  2(ISS/)1/2. iD/ISS
Illustration of the result: 1.0
0.8
iD1
0.6
0.4 iD2
0.2
vID
-2.0 -1.414 0.0 1.414 2.0 (ISS/ß)0.5 Fig. 5.2-4
Differentiating iD1 (or iD2) with respect to vID and setting VID =0V gives
diD1 ISS K'1ISSW1
gm = (V = 0) = = (half the gm of an inverting amplifier)
dvID ID 4 4L1

CMOS Analog Circuit Design © P.E. Allen - 2016

Lecture 19 – Differential Amplifier (6/24/14) Page 19-6

DIFFERENTIAL AMPLIFIER WITH A CURRENT MIRROR LOAD

Voltage Transfer Characteristic of the Differential Amplifier
In order to obtain the voltage transfer characteristic, a load for the differential amplifier
must be defined. We will select a current mirror load as illustrated below.
VDD
2mm 2mm
1mm 1mm
M3 M4
iD3 iD4 iOUT
2mm
1mm iD1 2mm iD2 +
1mm
VDD
M1 M2 2
+ vGS2 +
vGS1 vOUT
- -
vG1 2mm
1mm ISS vG2
Note that output signal to ground is M5
- - -
equivalent to the differential output VBias
signal due to the current mirror. Fig. 5.2-5

The short-circuit, transconductance is given as

diOUT K'1ISSW1
gm = (VID = 0) = ISS =
dvID L1

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Lecture 19 – Differential Amplifier (6/24/14) Page 19-7

Voltage Transfer Function of the Differential Amplifer with a Current Mirror Load

Regions of operation of the transistors:

M2 is saturated when,
vDS2  vGS2-VTN → vOUT-VS1  VIC-0.5vID-VS1-VTN → vOUT  VIC-VTN
where we have assumed that the region of transition for M2 is close to vID = 0V.
M4 is saturated when,
vSD4  vSG4 - |VTP| → VDD-vOUT  VSG4-|VTP| → vOUT  VDD-VSG4+|VTP|
The regions of operations shown on the voltage transfer function assume ISS = 100µA.
2·50
50·2 +|VTP| = 1 + |VTP|  vOUT  5 - 1 - 0.7 + 0.7 = 4V
Note: VSG4 =
CMOS Analog Circuit Design © P.E. Allen - 2016
Lecture 19 – Differential Amplifier (6/24/14) Page 19-8

Input Common Mode Range (ICMR) VDD

2mm 2mm
ICMR is found by setting vID = 0 and varying vIC 1mm 1mm
M3 M4
until one of the transistors leaves the saturation. iD3 iD4 iOUT
Highest Common Mode Voltage 2mm
1mm iD1 2mm iD2 +
1mm
VDD
Path from G1 through M1 and M3 to VDD: +
M1 M2 2
vGS1 vGS2 + vOUT
VIC(max) =VG1(max) =VG2(max) - -
vG1 2mm
1mm ISS vG2
=VDD -VSG3 -VDS1(sat) +VGS1 M5
- - -
or VBias
VIC(max) = VDD - VSG3 + VTN1 Fig. 330-02

Path from G2 through M2 and M4 to VDD:

VIC(max)’ =VDD -VSD4(sat) -VDS2(sat) +VGS2
=VDD -VSD4(sat) + VTN2
 VIC(max) = VDD - VSG3 + VTN1
Lowest Common Mode Voltage (Assume a VSS for generality)
VIC(min) = VSS +VDS5(sat) + VGS1 = VSS +VDS5(sat) + VGS2
where we have assumed that VGS1 = VGS2 during changes in the input common mode
voltage.
CMOS Analog Circuit Design © P.E. Allen - 2016
Lecture 19 – Differential Amplifier (6/24/14) Page 19-9

Small-Signal Analysis of the Differential-Mode of the Diff. Amp

A requirement for differential-mode operation is that the differential amplifier is
balanced†.
VDD

C3
M3 M4 D1=G3=D3=G4
iD3 iD4 iout G1 G2 rds1 S1=S2 rds2 D2=D4
+ vid -
+ + i3 +
iD1 iD2 +
vg1 vg2 rds5 i3 vout
rds4 C2
C1 1
M1 M2 gm3 rds3 gm1vgs1 gm2vgs2
- - -
vid vout S3 S4

M5 iout'
ISS G1 G2 D1=G3=D3=G4 D2=D4
- + vid -
VBias + + i3 +
vgs1 vgs2 C3
vout
gm1vgs1 1
C1 gm2vgs2 i3 rds2 rds4 C2
- - rds1 rds3 gm3 -
S1=S2=S3=S4
Differential Transconductance: Fig. 330-03

Assume that the output of the differential amplifier is an ac short.

gm1gm3rp1
iout’ = v − gm2vgs2  gm1vgs1 − gm2vgs2 = gmdvid
1 + gm3rp1 gs1
where gm1 = gm2 = gmd, rp1 = rds1rds3 and i'out designates the output current into a short
circuit.

†It can be shown that the current mirror causes this requirement to be invalid because the drain loads are not matched. However, we will continue to
use the assumption regardless.
CMOS Analog Circuit Design © P.E. Allen - 2016
Lecture 19 – Differential Amplifier (6/24/14) Page 19-10

Small-Signal Analysis of the Differential-Mode of the Diff. Amplifier - Continued

Output Resistance: Differential Voltage Gain:
1 vout gmd
rout = g + g = rds2||rds4 Av = v = g + g
ds2 ds4 id ds2 ds4
If we assume that all transistors are in saturation and replace the small signal parameters
of gm and rds in terms of their large-signal model equivalents, we achieve
vout (K'1ISSW1/L1)1/2 2 K'1W11/2 1
Av = = =   
vid (2 + 4)(ISS/2) 2 + 4  ISSL1  ISS
Note that the small-signal gain is inversely
vout
proportional to the square root of the bias current! vin Strong Inversion
Example: Weak
Invers-
If W1/L1 = 2µm/1µm and ISS = 50µA (10µA), then ion
log(IBias)
» 1µA
Av(n-channel) = 46.6V/V (104.23V/V) 060614-01

Av(p-channel) = 31.4V/V (70.27V/V)

1 1
rout = g + g = 25µA·0.09V-1 = 0.444M (2.22M)
ds2 ds4

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Lecture 19 – Differential Amplifier (6/24/14) Page 19-11

Common Mode Analysis for the Current Mirror Load Differential Amplifier
The current mirror load differential amplifier is not a good example for common mode
analysis because the current mirror rejects the common mode signal.

Total common  Common mode  Common mode

 mode Output  =  output due to  -  output due to 
 due to vic  M1-M3-M4 path  M2 path 
Therefore:
• The common mode output voltage should ideally be zero.
• Any voltage that exists at the output is due to mismatches in the gain between the two
different paths.

CMOS Analog Circuit Design © P.E. Allen - 2016

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DIFFERENTIAL AMPLIFIER WITH MOS DIODE LOADS

Small-Signal Analysis of the Common-Mode of the Differential Amplifier
The common-mode gain of the differential amplifier with a current mirror load is ideally
zero.
To illustrate the common-mode gain, we need a different type of load so we will consider
the following:
VDD VDD VDD

M3 M4 M3 M4 M3 M4
vo1 vo2 vo1 vo2 vo1 vo2

v1 v2
M1 M2 M1 M2 M1 M2
ISS 1
M5x 2 ISS
vid vid ISS 2 2
2 2 vic vic
M5
VBias VBias

Differential-mode circuit General circuit Common-mode circuit

110214-02

Differential-Mode Analysis:
vo1 gm1 vo2 gm2
vid ≈ -2gm3 and v ≈ + 2g
id m4

Note that these voltage gains are half of the active load inverter voltage gain.
CMOS Analog Circuit Design © P.E. Allen - 2016
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Small-Signal Analysis of the Common-Mode of the Differential Amplifier – Cont’d

Common-Mode Analysis:
+ vgs1 - gm1vgs1
Assume that rds1 is large and can be ignored + +
rds1 rds3
(greatly simplifies the analysis). vic 2rds5 1 vo1
gm3
 vgs1 = vg1-vs1 = vic - 2gm1rds5vgs1 - -
Fig. 330-06
Solving for vgs1 gives
vic
vgs1 = 1 + 2g r
m1 ds5
The single-ended output voltage, vo1, as a function of vic can be written as
vo1 gm1[rds3||(1/gm3)] (gm1/gm3) gds5
vic = - 1 + 2gm1rds5  - 1 + 2gm1rds5  - 2gm3
Common-Mode Rejection Ratio (CMRR):
|vo1/vid| gm1/2gm3
CMRR = |v /v | = g /2g = gm1rds5
o1 ic ds5 m3
How could you easily increase the CMRR of this differential amplifier?

CMOS Analog Circuit Design © P.E. Allen - 2016

Lecture 19 – Differential Amplifier (6/24/14) Page 19-14

Frequency Response of the Differential Amplifier

Back to the current mirror load differential amplifier:
VDD
Cgs3+Cgs4
G1 G2 D1=G3=D3=G4 D2=D4
Cbd3 M3 M4 + vid -
Cbd4 + + i3 +
vgs1 vgs2 C3
v vout
Cgd4 rds4 C2
Cgd1 gm1 gs1 1 i3
Cgd2 + gm3 C1 gm2vgs2 rds2
Cbd1 - - -
vout S1=S2=S3=S4
Cbd2 CL
vid -
M1 M2
+ vid -
M5 + + i3 +
vgs1 vgs2 vout
VBias gm1vgs1 1 i3 rds2 rds4 C2
- - gm3 gm2vgs2 -
070416-03
Ignore the zeros that occur due to Cgd1, Cgd2 and Cgd4.
C1 = Cgd1+Cbd1+Cbd3+Cgs3+Cgs4, C2 = Cbd2 +Cbd4+Cgd2+CL and C3 = Cgd4
The poles are p1 = - gm3/C1 and p2 = -(gds2+gds4)/C2. Since |p1| >> |p2|, then we can write
gm1  2  gds2 + gds4
Vout(s)  g + g  [Vgs1(s) - Vgs2(s)] where 2 ≈
ds2 ds4 s + 2 C2
The approximate frequency response of the differential amplifier reduces to
Vout(s)  gm1   2 
  
Vid(s)  gds2 + gds4 s + 2
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Lecture 19 – Differential Amplifier (6/24/14) Page 19-15

SMALL SIGNAL PERFORMANCE OF THE DIFFERENTIAL AMPLIFIER

Simplification of Small Signal Analysis
Small signal analysis is used so often in analog circuit design that it becomes desirable to
find faster ways of performing this important analysis.
Intuitive Analysis (or Schematic Analysis)
Technique:
1.) Identify the transistor(s) that convert the input voltage to current (these transistors are
called transconductance transistors).
2.) Trace the currents to where they flow into an equivalent resistance to ground.
3.) Multiply this resistance by the current to get the voltage at this node to ground.
4.) Repeat this process until the output is reached.
Simple Example: VDD VDD

R1 M2
vo1 gm2vo1 vout
gm1vin

vin M1 R2

Fig. 5.2-10C

vo1 = -(gm1vin) R1 → vout = -(gm2vo1)R2 → vout = (gm1R1gm2R2)vin

CMOS Analog Circuit Design © P.E. Allen - 2016
Lecture 19 – Differential Amplifier (6/24/14) Page 19-16

Intuitive Analysis of the Current-Mirror Load Differential Amplifier

1.) i1 = 0.5gm1vid and i2 = -0.5gm2vid VDD

2.) i3 = i1 = 0.5gm1vid M3 M4
3.) i4 = i3 = 0.5gm1vid gm1vid gm1vid rout
2 2
4.) The short-circuit output current is +
M1 gm1vid gm2vid M2
i4 - i2 = 0.5gm1vid + 0.5gm2vid = gm1vid + 2 2 -
vid vid
vout
4.) The resistance at the output node, rout, is 2 - + 2

1 + -
rds2||rds4 or g M5 vid
-
ds2 + gds4 VBias
140624-02
5.)  vout = (0.5gm1vid+0.5gm2vid )rout
gm1vin gm2vin vout gm1
= g +g = 
ds2 ds4 gds2+gds4 vin = gds2+gds4

CMOS Analog Circuit Design © P.E. Allen - 2016

Lecture 19 – Differential Amplifier (6/24/14) Page 19-17

Some Concepts to Help Extend the Intuitive Method of Small-Signal Analysis

1.) Approximate the output resistance of any cascode circuit as
Rout  (gm2rds2)rds1
where M1 is a transistor cascoded by M2.
2.) If there is a resistance, R, in series with the source of the transconductance transistor,
let the effective transconductance be
gm
gm(eff) = 1+g R
m
Proof:
gm2(eff)vin gm2(eff)vin
gm2vgs2 iout
M2 M2 + vgs2 -
vin rds1
vin M1 vin
rds1
VBias Small-signal model
Fig. 5.2-11A

vin
 vgs2 = vg2 - vs2 = vin - (gm2rds1)vgs2  vgs2 = 1+g r
m2 ds1

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Lecture 19 – Differential Amplifier (6/24/14) Page 19-18

gm2vin
Thus, iout = 1+g r = gm2(eff) vin
m2 ds1

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Lecture 19 – Differential Amplifier (6/24/14) Page 19-19

Noise Analysis of the Differential Amplifier

VDD VDD
M5
M5 M5
VBias VBias
en12 en22 eeq2

* M1 M2 * * M1 M2
ito2 vOUT
en32 en42
M3 * * M4 Vout M3 M4

Fig. 5.2-11C
Solve for the total output-noise current to get,
ito 2 = gm12en12 + gm22en22 + gm32en32 + gm42en42
This output-noise current can be expressed in terms of an equivalent input noise voltage,
eeq2, given as ito2 = gm12eeq2
Equating the above two expressions for the total output-noise current gives,
gm3 2
eeq = en1 + en2 + g  en32 + en42 
2 2 2
 m1
1/f Noise (en12=en22 and en32=en42): Thermal Noise (en12=en22 and en32=en42):
2BP  K’N BN L12 16kT  W3L1K'3
eeq (1/f) = fW L 1+  K’ B  L  
2 2
eeq (th) = 1+ 
1 1  P P   3  3[2K'1 (W/L) I
1 1 ] 1/2  L3 1 1
W K'
CMOS Analog Circuit Design © P.E. Allen - 2016
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CMOS Input Offset Voltage - Strong Inversion

Circuit:
VDD
RD1 RD2
ID1 ID2

V1 VOUT
+ +
VGS1 VGS2
-
V2 -
140423-04
ISS

Input Offset Voltage:

2ID1 L1  2ID2 L2 
VIO = VGS1 – VGS2 = VT1 – VT2 +  · -  · 
 K' W1  K' W2
But ID1R D1 = ID2R D2, therefore
2L1  ID2RD2 ID2 2IDL1  RD2 1
VIO = VT + W1 

K1RD1 - K2  = VT +

W1 

K1RD1 -

K2
where ID1 ≈ ID2 = ID and VT = VT1-VT2.
Assuming matched geometries, W1/L1 = W2/L2 = W/L,
2IDL  RD2 1
VIO = VT +  - 
W  K1RD1 K2
CMOS Analog Circuit Design © P.E. Allen - 2016
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CMOS Input Offset Voltage - Strong Inversion

Define the following,
RD1 = R + 0.5R, RD2 = R - 0.5R, K1 = K + 0.5K, and K2 = K - 0.5K
where R = 0.5(RD1 + RD2), R = RD1 - RD2, K = 0.5(K1 + K2), and K = K1 - K2.
Substituting these relationships into the expression for VIO gives,
2IDL  R - 0.5R 1 
VIO = VT +  
W  (K + 0.5K)(R + 0.5R) - K - 0.5K
Factoring out R and K gives,
2IDL  1 - 0.5R/R 1 
VIO = VT +  
KW  (1 + 0.5K/K)(1 + 0.5R/R) - 1 - 0.5K/K
Approximating 1/(1 ± ) as 1∓  results in,
2IDL  
VIO ≈ VT +  (1 - 0.5R/R)(1 - 0.5K/K)(1 - 0.5R/R) - 1 + 0.5  K/K 
KW
Finally, multiplying terms and ignoring higher order terms and letting x ≈ 0.5x gives,
1 R K 2IDL 1 R K
VIO ≈ VT - 2  R + K  = VT - 2  R + K  (VGS - VT)
  KW  

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Lecture 19 – Differential Amplifier (6/24/14) Page 19-22

CMOS Input Offset Voltage Temperature Drift – Strong Inversion

Assumptions:
Drain current is constant, R/R and K/K have very little temperature dependence.
Therefore only VT and K will considered in the expression below
1 R K 2IDL
VIO ≈ VT -  + 
2 R K  KW
Assuming VT(T) = VT(To) - (T- To) and K(T) = kT-1.5, then we get,
V T d
dT = dT [VT1 – (T- To) - VT2 + (T- To)] =  –  =   
and
d 2IDL 2IDL  3 T-2.5  3 2IDL
dT KW = KW -2 T-1.5 = -2T KW
Therefore,
dVIO 3 R K 2IDL 3 R K 1 2 1
=  +  =  +  (VGS - VT) =
dT 4T  R K  KW 4T  R K  400 100 10 = 5µV/°C
Comments:
When the overdrive is large, the input offset voltage temperature drift will be larger
Typical values of dVIO/dT are 1-10µV/°C
CMOS Input Offset Voltage Temperature Drift – Weak Inversion
CMOS Analog Circuit Design © P.E. Allen - 2016
Lecture 19 – Differential Amplifier (6/24/14) Page 19-23

Repeating the previous analysis with the following model for the transistors
W æV - V ö
iD = IT 1 exp çç GS T ÷
÷
L è nVt ø
gives,
æi L ö æi L ö æi LI W ö
VIO = VGS1 - VGS2 = VT 1 + nVt ln çç D1 1 ÷ - V + nV ln ç
÷ T 2 t
D2 2
çI W ÷
÷ = DV + nV ln ç D1 1 T 2 2 ÷
T t çi L I W ÷
I W
è T1 1 ø è T2 2 ø è D2 2 T 1 1 ø
But iD1RD1 = iD2R D2 and W1/L1 = W2/L2 = W/L which gives,
æR I ö
VIO = DVT + ln çç D2 T 2 ÷÷
Define the following, è RD1IT 1 ø
RD1 = R + 0.5R, RD2 = R - 0.5R, IT1 = IT + 0.5IT, and IT2 = IT - 0.5IT
where R = 0.5(RD1 + RD2), R = RD1 - RD2, IT = 0.5(IT1 + IT2), and IT = IT1 – IT2.
Substituting these relationships into the expression for VIO gives,
æ (R - 0.5DR)(I - 0.5DI ) ö æ (1 - 0.5DR R)(1 - 0.5DI I ) ö
VIO = DVT + nVt ln çç T T ÷
÷ = DVT + nVt ln çç T T ÷
÷
è (R + 0.5DR)(IT + 0.5DIT ) ø è (1 + 0.5DR R)(1 + 0.5DIT IT ) ø
» DVT + nVt ln éë(1 - 0.5DR R)2(1 - 0.5DIT IT )2 ùû » DVT + nVt ln éë1 - DR R - DIT IT ùû
æ DR DI ö
» DVT - nVt çç + T ÷÷
è R IT ø

CMOS Analog Circuit Design © P.E. Allen - 2016

Lecture 19 – Differential Amplifier (6/24/14) Page 19-24

LARGE SIGNAL PERFORMANCE OF THE DIFFERENTIAL AMPLIFIER

Linearization of the Transconductance
iout iout
Goal:
ISS ISS

Linearization
vin vin

-ISS -ISS
060608-03

Method (degeneration):
VDD VDD
M3 M4 M3 M4
iout iout

M1 M2 M1 M2
+ RS RS VDD or + VDD
vin 2 2 2 vin RS 2
- -
M5
VNBias1 M5 VNBias1 M6
060118-10

CMOS Analog Circuit Design © P.E. Allen - 2016

Lecture 19 – Differential Amplifier (6/24/14) Page 19-25

Linearization with Active Devices

VDD VDD
M3 M4 M3 M4
iout iout

M1 VBias M2 M1 M2
+ VDD + VDD
or
vin M6 2 M6 2
vin
- M7
M5x1/2 -
VNBias1 M5x1/2 M5
VNBias1 M6

M6 is in deep triode region 060608-05 M6 and M7 are in the triode region

Note that these transconductors on this slide and the last can all have a varying
transconductance by changing the value of ISS.

CMOS Analog Circuit Design © P.E. Allen - 2016

Lecture 19 – Differential Amplifier (6/24/14) Page 19-26

Slew Rate of the Differential Amplifier

Slew Rate (SR) = Maximum output-voltage rate (either positive or negative)
dvOUT
It is caused by, iOUT = CL dt . When iOUT is a constant, the rate is a constant.
Consider the following current-mirror load, differential amplifiers:
VDD VDD
M5
M3 M4
iD4 iOUT VBias IDD
iD3
- -
vSG1 vSG2
iD1 iD2 + + +
M1 M2
CL + +
M1 M2 iD1 iD2 iOUT
+
vGS1 vGS2 +
- - iD3 iD4 +
vG1 ISS vG2 vOUT vG1 vG2
M3 M4 CL vOUT
M5
- - - - - -
VBias
Fig. 5.2-11B
Note that slew rate can only occur when the differential input signal is large enough to
cause ISS (IDD) to flow through only one of the differential input transistors.
ISS IDD
SR = C = C  If CL = 5pF and ISS = 10µA, the slew rate is SR = 2V/µs.
L L
(For the BJT differential amplifier slewing occurs at ±100mV whereas for the MOSFET
differential amplifier it can be ±2V or more.)
CMOS Analog Circuit Design © P.E. Allen - 2016
Lecture 19 – Differential Amplifier (6/24/14) Page 19-27

DIFFERENTIAL AMPLIFIERS WITH CURRENT SOURCE LOADS

Current-Source Load Differential Amplifier
VDD
Gives a truly balanced differential amplifier.
M3 M4
X1
X1 X1
M7 I3 I4
v3 v4
Also, the upper input common-mode range is
IBias v1 I1 I2 v2
extended.
M1 X1 X1 M2
M6 M5 I5
X1 X2
However, a problem occurs if I1 I3 or if I2  I4.
Fig. 5.2-12

Current Current
I1 I3
I3 I1

0 vDS1 0 vDS1
0 VDS1<VDS(sat) VDD 0 VSD3<VSD(sat) VDD
(a.) I1>I3. (b.) I3>I1. Fig. 5.2-13

CMOS Analog Circuit Design © P.E. Allen - 2016

Lecture 19 – Differential Amplifier (6/24/14) Page 19-28

A Differential-Output, Differential-Input Amplifier

Probably the best way to solve the current mismatch problem is through the use of
common-mode feedback.
Consider the following solution to the previous problem.
VDD
M3 M4
IBias MC3
MC4 v3 I3 I4 v4
Common- IC3 IC4
mode feed- Self-
back circuit resistances
MC1 MC2A of M1-M4
v1 v2
VCM M1 M2
MC2B
MC5 M5
MB

VSS Fig. 5.2-14

Operation:
• Common mode output voltages are sensed at the gates of MC2A and MC2B and
compared to VCM.
• The current in MC3 provides the negative feedback to drive the common mode output
voltage to the desired level.
• With large values of output voltage, this common mode feedback scheme has flaws.
CMOS Analog Circuit Design © P.E. Allen - 2016
Lecture 19 – Differential Amplifier (6/24/14) Page 19-29

Common-Mode Stabilization of the Diff.-Output, Diff.-Input Amplifier - Continued

The following circuit avoids the large differential output signal swing problems.
VDD
M3 M4
IBias MC3
MC4 v3 I3 I4 v4
Common- IC3 IC4 RCM1
mode feed- Self-
back circuit resistances
RCM2
MC1 MC2 of M1-M4
v1 v2
VCM M1 M2

MC5 M5
MB

VSS Fig. 5.2-145

Note that RCM1 and RCM2 must not load the output of the differential amplifier.
(We will examine more CM feedback schemes in Lecture 28.)

CMOS Analog Circuit Design © P.E. Allen - 2016

Lecture 19 – Differential Amplifier (6/24/14) Page 19-30

DESIGN OF DIFFERENTIAL AMPLIFIERS

Design of a CMOS Differential Amplifier with a Current Mirror Load
Design Considerations: VDD

Constraints Specifications
Power supply Small-signal gain M3 M4
Technology Frequency response (CL) vout
CL
Temperature ICMR +
Slew rate (CL) vin M1 M2
-
Power dissipation
I5
Relationships
VBias M5
Av = gm1Rout
VSS ALA20
-3dB = 1/RoutCL
VIC(max) = VDD - VSG3 + VTN1
VIC(min) = VSS +VDS5(sat) + VGS1 = VSS +VDS5(sat) + VGS2
SR = ISS/CL
Pdiss = (VDD+|VSS|)x(All dc currents flowing from VDD or to VSS)

CMOS Analog Circuit Design © P.E. Allen - 2016

Lecture 19 – Differential Amplifier (6/24/14) Page 19-31

Design of a CMOS Differential Amplifier with a Current Mirror Load - Continued

Schematic-wise, the design procedure is illustrated as

shown:

Procedure:
1.) Pick ISS to satisfy the slew rate knowing CL or
the power dissipation
2.) Check to see if Rout will satisfy the frequency
response, if not change ISS or modify circuit
3.) Design W3/L3 (W4/L4) to satisfy the upper ICMR
4.) Design W1/L1 (W2/L2) to satisfy the gain
5.) Design W5/L5 to satisfy the lower ICMR
6.) Iterate where necessary

CMOS Analog Circuit Design © P.E. Allen - 2016

Lecture 19 – Differential Amplifier (6/24/14) Page 19-32

Example 19-1 - Design of a MOS Differential Amp. with a Current Mirror Load
Design the currents and W/L values of the current mirror load MOS differential amplifier
to satisfy the following specifications: VDD = -VSS = 2.5V, SR  10V/µs (CL=5pF), f-
3dB  100kHz (CL=5pF), a small signal gain of 100V/V, -1.5VICMR2V and Pdiss
 mW. Use the parameters of KN’=110µA/V2, KP’=50µA/V2, VTN=0.7V, VTP=-0.7V,
N=0.04V-1 and P=0.05V-1.
Solution
1.) To meet the slew rate, ISS  50µA. For maximum Pdiss, ISS  200µA.
2
2.) f-3dB of 100kHz implies that Rout  318k Therefore Rout =  318k
(N+P)ISS
 ISS  70µA Thus, pick ISS = 100µA
3.) VIC(max) = VDD - VSG3 + VTN1 → 2V = 2.5 - VSG3 + 0.7
2·50µA
VSG3 = 1.2V = + 0.7
50µA/V2(W3/L3)
W3 W4 2
 L =L = 2 =8
3 4 (0.5)

CMOS Analog Circuit Design © P.E. Allen - 2016

Lecture 19 – Differential Amplifier (6/24/14) Page 19-33

Example 19-1 - Continued

gm1 2·110µA/V2(W1/L1) W1 W1 W2
L1 → L1= L2 = 18.4
4.) 100=gm1Rout=g +g = = 23.31
ds2 ds4 (0.04+0.05) 50µA
5.) VIC(min) = VSS +VDS5(sat)+VGS1
2·50µA
-1.5 = -2.5+VDS5(sat)+ + 0.7
110µA/V2(18.4)
W5 2ISS
VDS5(sat) = 0.3 - 0.222 = 0.0777  L = = 150.6
5 KN’VDS5(sat)2
We probably should increase W1/L1 to reduce VGS1. If we choose W1/L1 = 40, then
VDS5(sat) = 0.149V and W5/L5 = 41. (Larger than specified gain should be okay.)

CMOS Analog Circuit Design © P.E. Allen - 2016

Lecture 19 – Differential Amplifier (6/24/14) Page 19-34

SUMMARY
• Differential amplifiers are compatible with the matching properties of IC technology
• The differential amplifier has two modes of signal operation:
- Differential mode
- Common mode
• Differential amplifiers are excellent input stages for voltage amplifiers
• Differential amplifiers can have different loads including:
- Current mirrors
- MOS diodes
- Current sources/sinks
- Resistors
• The small signal performance of the differential amplifier is similar to the inverting
amplifier in gain, output resistance and bandwidth
• The large signal performance includes slew rate and the linearization of the
transconductance
• The design of CMOS analog circuits uses the relationships of the circuit to design the
dc currents and the W/L ratios of each transistor
CMOS Analog Circuit Design © P.E. Allen - 2016