Unit-4
Asynchronous sequential Machine
In many practical situations, synchronous circuits lead to more
power consumption and delay than asynchronous circuits.
Moreover, within large synchronous systems, it is often
desirable to allow certain subsystems to operate
asynchronously, thereby avoiding some of the problems
associated with clocking.
x1, x2, . . . , xl are referred as external input variables
Z1, Z2….., zm are referred as output variables.
y1, y2, . . . , yk are referred to as secondary or internal variables
Y1, Y2, . . . , Yk are called excitation variables.
For a given input state, the circuit is said to be in a stable state if and
only if yi = Yi for i = 1, 2, . . . , k.
As in the case of synchronous circuits, the least systematic step in the synthesis
procedure is that of transforming a verbal statement of the desired circuit
behaviour into a precise description that specifies the circuit operation for every
applicable input sequence. A convenient method for describing the behaviour of
an asynchronous circuit is by means of a flow table. As an example, consider the
combinational logic produces a new set of values for the excitation variables (Y).
As a result, the circuit enters what is called an unstable state. When the secondary
variables assume their new values, i.e., the y’s become equal to the corresponding
Y ’s, the circuit enters its “next” stable state. Thus, a transition from one stable
state to another occurs only in response to a change in the input state.
Two important point to note that,
1. after a change in input values has occurred, there is no other change in any
input value until the circuit enters a stable state. Such a mode of operation
is often referred to as the fundamental mode.
2. If only a single input value is allowed to change at any given time, it is
called a single-input-change (SIC) fundamental mode, otherwise a multiple
input-change (MIC) fundamental mode.
Question: A sequential circuit with two inputs, x1 and x2, and one output, z. The
initial input state is x1 = x2 = 0. The output value is to be 1 if and only if the input
state is x1 = x2 = 1 and the preceding input state is x1 = 0, x2 = 1.
A possible pair of input sequences and the corresponding output sequence are
illustrated below
Step-1 Finding Possible States
Step-2 Primitive Flow Table
Step-3 Merger Graph
Compatible pairs: {123, 45} or {145, 23}
Step-4 Reduction of flow table
Compatible pairs: {123, 45}
Step-5 State Assignment
Step-6 Finding expression for Y and Z using K-Map
Step-7 Circuit Diagram
Step-8 Circuit Verification
Another Compatibility pair
Step-4 Reduction of flow table
Compatible pairs: {145, 23}
Step-5 State Assignment
Step-6 Finding expression for Y and Z using K-Map
Step-7 Circuit Diagram
Step-8 Circuit Verification
Step-2 Primitive Flow Table