Team’s members:
Lê Nguyễn Thái Hà ( Leader)
- Transistor Transistor Logic, PDN structure, PDN-PUN, CMOS
NOT, CMOS NAND, CMOS NOR, CMOS AND, Ex3.1, Ex3.2
Nguyễn Đức Gia Phong
- NMOS NOT, NMOS NAND, NMOS NOR, NMOS AND, NMOS
OR
Nguyễn Kim Hưng Thịnh
- OR, AND, NOT, NOR, Diode Transistor Logic
Session 1: TTL Logic Gates
X1 X2 Y
0 0 0
0 1 1
1 0 1
1 1 1
Case 1: Input x1 = 0; x2 = 0 Output y = 0
When x1 = 0; x2 = 0, the input voltage of x1 and x2 is logic value 0, voltage in Anode is smaller than voltage
in Cathode of both diode D1 and D2 is opened no current through y received voltage logic value 0.
Case 2: Input x1 = 0; x2 = 1 Output y = 1
When x1 = 0; x2 =1, the input voltage of x1 is logic value 0, x2 is logic value 1, D1 has voltage in Anode
smaller than Cathode, D2 has voltage in Anode rather than Cathode D1 is opened; D2 is closed current
through D2 y received logic value 1
Case3: Input x1 = 1; x2 = 0 Output y = 1
When x1 = 1; x2 = 0; the input voltage of x1 is logic value 1, x2 is logic value 0, D2 has voltage in Anode
smaller than Cathode, D1 has voltage in Anode rather than Cathode D2 is opened; D1 is closed current
through D1 y received logic value 1
Case 4: Input x1 = 1; x2 = 1 Output y = 1
When x1 = 1; x2 = 1, the input voltage of x1 and x2 is logic value 0, voltage in Anode is rather than voltage in
Cathode of both diode D1 and D2 is closed current through D1 and D2 y received voltage logic value
0.
X1 X2 Y
0 0 0
0 1 0
1 0 0
1 1 1
Case 1: Input x1 = 0; x2 = 0 Output y = 0
When x1 = 0; x2 = 0, the input voltage of x1 and x2 is logic value 0, voltage in Anode is rather than voltage in
Cathode of both diode D1 and D2 is closed current through D1 and D2 D1 and D2 received a lot of voltage
from Vcc y received voltage logic value 0
Case 2: Input x1 = 0; x2 = 1 Output y = 0
When x1 = 0; x2 =1, the input voltage of x1 is logic value 0, x2 is logic value 1, D2 has voltage in Anode smaller
than Cathode, D1 has voltage in Anode rather than Cathode D2 is opened; D1 is closed current through D1
D1 received a lot of voltage from Vcc y received logic value 0
Case3: Input x1 = 1; x2 = 0 Output y = 0
When x1 = 1; x2 = 0; the input voltage of x1 is logic value 1, x2 is logic value 0, D1 has voltage in Anode smaller
than Cathode, D2 has voltage in Anode rather than Cathode D1 is opened; D2 is closed current through D2
D2 received a lot of voltage from Vcc y received logic value 0
Case 4: Input x1 = 1; x2 = 1 Output y = 1
When x1 = 1; x2 = 1, the input voltage of x1 and x2 is logic value 0, voltage in Anode is smaller than voltage in
Cathode of both diode D1 and D2 is opened no current through D1 and D2 D1 and D2 didn’t received
voltage from Vcc y received voltage logic value 1.
X Y
0 1
1 0
Case 1: Input x = 0 Output y = 1
When x = 0, the input voltage of x1 is logic value 0. Because V B < VC Cut-off Q1 is
opened y received voltage logic value 1
Case 2: Input x = 1 Output y = 0
When x = 1, the input voltage of x1 is logic value 1. Because V B > VC Saturation Q1 is
closed Vcc will connect to the ground, lost voltage y received voltage logic value 0
X1 X2 Y
0 0 1
0 1 0
1 0 0
1 1 0
Case 1: Input x1 = 0; x2 = 0 Output y = 1
When x1 = 0; x2 = 0, the input voltage of x1 and x2 is logic value 0, voltage in V B < VE of both diode Cut-off Q1 and Q2
is opened no current through Q1 and Q2 y received voltage logic value 1
Case 2: Input x1 = 0; x2 = 1 Output y = 0
When x1 = 0; x2 =1, the input voltage of x1 is logic value 0, x2 is logic value 1, Q2 has V B > VE Saturation; Q1 has VB <
VE Cut-off Q1 is opened; Q2 is closed current through Q2 connect to the ground, lost voltage y received logic
value 0
Case 3: Input x1 = 1; x2 = 0 Output y = 0
WhenDon’t
x1 =use1;this
x2 one,
=0, because
the input twovoltage of x1 is logic value 1, x2 is logic value 0, Q1 has V B > VE Saturation; Q2 has VB <
VE inputs x1 and
Cut-off Q2 be
x2 will opened; Q1 is closed current through Q1 connect to the ground, lost voltage y received logic
is disturbed
value 0
Case 4: Input x1 = 1; x2 = 1 Output y = 1
When x1 = 1; x2 = 1, the input voltage of x1 and x2 is logic value 1; Q1, Q2 has VB < VE Cut-off Q1 and Q2 is opened
current through Q1 and Q2 connect to the ground, lost voltage y received logic value 0
X1 X2 Y
0 0 1
0 1 1
1 0 1
1 1 0
Case 1: Input x1 = 0, x2 = 0 Output y = 1
When x1 = 0; x2 = 0, the input voltage of x1 and x2 is logic value 0; D1 and D2 has voltage in Anode smaller than Cathode
D1 and D2 is closed Voltage in A is 0.6V Not enough voltage for D4, D3 and Q Q is opened Vcc isn’t connected
to the ground y received logic value 1
Case 2: Input x1 = 0, x2 = 1 Output y = 1
When x1 = 0; x2 = 1, the input voltage of x1 is logic value 0. x2 is logic value 1; D1 has voltage in Anode smaller than
Cathode, D2 has voltage in Anode rather than Cathode D1 is closed, D2 is opened Voltage in A is 0.6V Not enough
voltage for D4, D3 and Q Q is opened Vcc isn’t connected to the ground y received logic value 1
Case 3: Input x1 = 1, x2 = 0 Output y = 1
When x1 = 1; x2 = 0, the input voltage of x1 is logic value 1. x2 is logic value 0; D2 has voltage in Anode smaller than
Cathode, D1 has voltage in Anode rather than Cathode D2 is closed, D1 is opened Voltage in A is 0.6V Not enough
voltage for D4, D3 and Q Q is opened Vcc isn’t connected to the ground y received logic value 1
Case 1: Input x1 = 1, x2 = 1 Output y = 0
When x1 = 1; x2 = 1, the input voltage of x1 and x2 is logic value 1; D1 and D2 has voltage in Anoderather than Cathode D1
and D2 is open Voltage in A is enough for D4, D3 and Q Q is closed Vcc is connected to the ground, lost voltage y
received logic value 0
Case 1: Input x1 = 0,
x2 = 0 Output f =
1
or Input x1 = 0,
x2 = 1 Output f =
1
or Input x1 = 1,
x2 = 0 Output f =
1
When x1 or x2 or
both has logic value
0, circuit polarization
on Q1 is small such
that Q2 not enough
voltage to close.
Then, Q3 is closed.
VCC through Q4 and
D to y y received
logic value 1
Case 2: Input x1 = 1,
x2 = 1 Output f =
0
When x1 and x2 = 1,
Q1will affect Q2,
makes Q2 saturation.
VCC through Q2 and
Q3 to mass y
received logic value
0
Session 2: MOSFET, CMOS Logic Gates
NMOS NOT
Case 1 : Input x = 0 Output f = 1
When x=0, the logic voltage is low so NMOS transistor switch will be opened voltage
through Vf is received logic value 1.
Case 2: Input x = 1 Output f = 0
When x = 1, the logic voltage is high so NMOS transistor switch will be closed. Thus
VDD run through R and Vx to the ground voltage through Vf is received logic value 0.
Case 1: Input x1 = 0; x2 = 0 Output f = 1;
When x1 = 0, x2 = 0, The input voltage for Vx1’s and Vx2’s
NMOS NAND NMOS is low switches will be opened voltage
through Vf is received logic value 1.
Case 2: Input x1 = 0; x2 = 1 Output f = 1;
When x1 = 0, the input voltage is low for Vx1’s NMOS
switch switch open.
When x2 = 1, the input voltage is high for Vx2’s NMOS
switch switch close.
Thus voltage can’t run through Vx1 voltage through Vf is
logic value 1.
Case 3: Input x1 =1; x2 = 0 Output f = 1;
When x1 = 1, the input voltage is high for Vx1’s NMOS
switch switch close
When x2 = 0, the input voltage is low for Vx2’s NMOS
switch switch open
Thus this case is vice versa to case 2. Current can’t reach to
Vx2 voltage through Vf is received logic value 1.
Case 4: Input x1 = 1; x2 = 1. Output f = 0;
When x1 = x2 = 1, the input voltage is high for both Vx’s
NMOS switches switch close.
Thus voltage through Vx1 and Vx2 voltage through Vf is
received logic value 0.
Case 1 : Input x1 = 0, x2 = 0 Output f = 1;
When x1 = x2 = 0. Input voltage are low for both Vx’s NMOS
NMOS NOR switches switches will open. Thus no voltage through Vx1
and Vx2 Current through Vf is received logic value 1.
Case 2: Input x1 = 0, x2 = 1 Output f = 0;
WhenCase
x1 1:= Input
0. Input
x1 = voltage is Output
0, x2 = 0 low forf =Vx1’s
0; NMOS switch
switch willx1open.
When = x2 = 0. Input voltage are low for both Vx’s NMOS switches
switches will open.
When x2 = 1. Input voltage is high for Vx2’s NMOS switch
NMOS AND switch
Nowill through Vx1 and Vx2 voltage through A is high.
close.
voltage
A’s NMOS switch will close voltage through Vf is received logic
ThusThus
voltage Vx2 voltage through Vf is received logic
value 0
value 0.
Case 2 : Input x1 = 0, x2 = 1 Output f =0;
Case 3: Input x1 = 1, x2 = 0 Output f = 0;
When x1 = 0. Input voltage is low for Vx1’s NMOS switch switch open.
WhenWhen
x1 =x21.= Input voltage is high for Vx1’s NMOS switch
1 Input voltage is low for Vx2’s NMOS switch switch close.
switch will close.
Voltage got cut off at Vx1 voltage through A is high.
When x2 = 0. Input voltage is low for Vx2’s NMOS switch
Thus A’s NMOS switch will close voltage through Vf is received logic
switch will
value 0 open.
ThusCase
voltage through
3: Input x2 =0
x1 = 1, Vx1 voltage
Output f =through
0; Vf is received
logic value 0.
When x1 = 1 Input voltage is high for Vx1’s NMOS switch switch close.
CaseWhen
4: Input
x2 = x1 x2 = 1is
= 1,voltage
0 Input lowOutput
for Vx2’sf NMOS
=0; switch switch open.
WhenVoltage
x1 = got
x2 cut
=1.offInput voltage
at Vx2 arethrough
voltage high for
A isboth
high. Vx’s NMOS
Thus switches
switches willwill
A’s NMOS switch close.
close voltage through Vf is received logic
value 0
Thus voltage through Vx1 and Vx2 voltage through Vf is
received
Case logic
4: Inputvalue
x1 = 1,0.x2 = 1 Output f = 1;
s
Case 1: x1 = 0, x2 = 0 Output f = 0;
When x1 = x2 = 0. Input voltage are low for both Vx’s NMOS switches
Switches open. Voltage cannot through Vx1 and Vx2 voltage output of
NMOS NOR is high
Thus, NMOS NOT switch will close, VDD connect to the ground voltage
through Vf is received logic value 0
NMOS OR
Case 2 : Input x1 = 0, x2 = 1 Output f = 1;
When x1 = 0. Input voltage is low for Vx1’s NMOS switch switch
open.
When x2 = 1. Input voltage is low for Vx2’s NMOS switch switch
close.Voltage through Vx2 voltage output of NMOS NOR is low.
Thus NMOS NOT switch will open voltage through Vf is received
logic value 1.
Case 3: Input x1 = 1, x2 =0 Output f = 1;
When x1 = 1. Input voltage is high for Vx1’s NMOS switch switch
close.
When x2 = 0. Input voltage is low for Vx2’s NMOS switch switch
open.
Voltage through Vx1 voltage output of NMOS NOR switch is low.
Thus NMOS NOT switch will open voltage through Vf is received
logic value 1.
Case 4: Input x1 = 1, x2 = 1 Output f = 1;
When x1 = x2 =1. Input voltage are high for both Vx’s NMOS switches
switches close.
Voltage through Vx1 and Vx2 voltage output of NMOS NOR switch is
low.
Thus NMOS NOT switch will open voltage through Vf is received
logic value 1.
PDN – PUN: CMOS technology was created to avoid the wasted power
when the current through the resistor (complement).
CMOS NOT
From NMOS NOT, we can create the
CMOS NOT by using PMOS instead
of the resistor.
Case 1: Input x = 0 Output f = 1
When x = 0, the input voltage of x is
logic value 0 T1 = “ low”, T2 = “
low” T1 is closed, T2 is opened
the voltage from VDD through T1 to Vf
f received logic value 1
Case 2: Input = 1 Output f = 0
When x = 1, the input voltage of x is
logic value 1 T1 = “ high”, T2 = “
high” T1 is opened, T2 is closed
the voltage from VDD cannot through
T1 to Vf f received logic value 0
CMOS NAND
Case 1: Input x1 = 0, x2 = 0 Output f = 1
When x1 = 0, x2 = 0; the input voltage of x1 and x2 is logic value 0
T1, T2, T3, T4 = “ low” T1 and T2 is closed, T3 and T4 is opened
the voltage from VDD through T1 and T2 to Vf, VDD cannot connect to
the ground f received logic value 1
Case 2: Input x1 = 0, x2 = 1 Output f = 1
When x1 = 0, x2 = 1; the input voltage of x1 is logic value 0, x2 is logic
value 1 T1 and T3 = “ low”, T2 and T4 = “ high” T1 and T4 is
closed, T2 and T3 is opened voltage from VDD through T1 to Vf.
Although T4 is closed, VDD cannot connect to the ground because T3 is
opened f received logic value 1.
Case 3: Input x1 = 1, x2 = 0 Output f = 1
When x1 = 1, x2 = 0; the input voltage of x1 is logic value 1, x2 is logic
value 0 T1 and T3 = “ high”, T2 and T4 = “ low” T1 and T4 is
opened, T2 and T3 is closed voltage from VDD through T2 to Vf.
Although T3 is closed, VDD cannot connect to the ground because T4 is
opened f received logic value 1.
Case 4: Input x1 = 1, x2 = 1 Output f = 0
When x1 = 1, x2 = 1; the input voltage of x1 and x2 is logic value 1
T1, T2, T3, T4 = “ high” T1 and T2 is opened, T3 and T4 is closed
the voltage from VDD cannot through to Vf f received logic value 0
The formula of f can be calculated by using K-Map. From f, we can get
~f easily.
CMOS NOR
Case 1: Input x1 = 0, x2 = 0 Output = 1
When x1 = 0, x2 = 0; the input voltage of x1 x2 is logic
value 0 T1, T2, T3, T4 = “ low” T1 and T2 is closed,
T3 and T4 is opened the voltage from VDD through T1
and T2 to Vf f received logic value 1
Case 2: Input x1 = 0, x2 = 1 Output = 0
When x1 = 0, x2 = 1; the input voltage of x1 is logic value
0, x2 is logic value 1 T1 and T3 = “ low”, T2 and T4 = “
high” T1 and T4 is closed, T2 and T3 is opened the
voltage from VDD through T1, but cannot come to Vf
because T2 and T3 is opened f received logic value 0
Case 3: Input x1 = 1, x2 = 0 Output = 0
When x1 = 1, x2 = 0; the input voltage of x1 is logic value
1, x2 is logic value 2 T1 and T3 = “ high”, T2 and T4 = “
low” T1 and T4 is opened, T2 and T3 is closed the
voltage from VDD cannot through to Vf because T1 is
opened f received logic value 0
Case 4: Input x1 = 1, x2 =1 Output = 0
When x1 = 1, x2 = 1; the input voltage of x1 x2 is logic
value 1 T1, T2, T3, T4 = “ high” T1 and T2 is
opened, T3 and T4 is closed the voltage from VDD cannot
through T1 and T2 to Vf because T1 is opened f received
logic value 0
Formula of f can be calculated by using K-Map. From f, we
can get ~f easily.
CMOS AND
Case 1: Input x1 = 0, x2 = 0 Output = 0
When x1 = 0, x2 = 0; the input voltage of x1 and x2 is logic value 0
T1, T2, T3, T4 = “ low” T1 and T2 is closed, T3 and T4 is
opened the voltage from VDD through T1 and T2 to A A
received logic value 1 T5 is opened, T6 is closed VDD2 cannot
through to Vf, voltage from VDD will be lost because VDD is
connected to the ground f received logic value 0
Case 2: Input x1 = 0, x2 = 1 Output = 0
When x1 = 0, x2 = 1; the input voltage of x1 is logic value 0, x2 is
logic value 1 T1, T3 = “ low”, T2, T4 = “ high” T1 and T4 is
closed, T2 and T3 is opened the voltage from VDD through T1 to
A, VDD cannot connect to the ground because T3 is opened A
received logic value 1 T5 is opened, T6 is closed VDD2 cannot
through to Vf, voltage from VDD will be lost because VDD is
connected to the ground f received logic value 0
Case 3: Input x1 = 1, x2 = 0 Output = 0
When x1 = 1, x2 = 0; the input voltage of x1 is logic value 1, x2 is
X1 X2 T1 T2 T3 T4 T5 T6 f logic value 0 T1, T3 = “ high”, T2, T4 = “ low” T1 and T4 is
opened, T2 and T3 is closed the voltage from VDD through T2 to
A, VDD cannot connect to the ground because T4 is opened A
0 0 ON ON OFF OFF OFF ON 0 received logic value 1 T5 is opened, T6 is closed VDD2 cannot
through to Vf, voltage from VDD will be lost because VDD is
0 1 ON OFF OFF ON OFF ON 0 connected to the ground f received logic value 0
Case 4: Input x1 = 1, x2 = 1 Output = 1
1 0 OFF ON ON OFF OFF ON 0 When x1 = 1, x2 = 1; the input voltage of x1 and x2 is logic value 1
T1, T2, T3, T4 = “ high” T1 and T2 is opened, T3 and T4 is
1 1 OFF OFF ON ON ON OFF 1 closed the voltage from VDD cannot through to A A received
logic value 0 T6 is opened, T5 is closed VDD2 through T5 to Vf,
f received the logic value 1
X1 X2 X3 T1 T2 T3 T4 T5 T6 f
0 0 0 ON ON ON OFF OFF OFF 1
0 0 1 ON ON OFF OFF OFF ON 1
0 1 0 ON OF ON OFF ON OFF 1
F
0 1 1 ON OF OFF OFF ON ON 1
F
1 0 0 OFF ON ON ON OFF OFF 1
1 0 1 OFF ON OFF ON OFF ON 0
1 1 0 OFF OF ON ON ON OFF 0
F
1 1 1 OFF OF OFF ON ON ON 0
F
Example 3.1
Case 1: Input x1 = 0, x2 = 0, x3 = 0 Output f = 1
When x1, x2, x3 = 0, the input voltage of x1, x2, x3 is logic value 0 T1, T2, T3, T4, T5, T6 = “ low” T1, T2, T3 is closed, T4,
T5, T6 is opened the voltage from VDD through T1, T2, T3 to Vf f received the logic value 1
Case 2: Input x1 = 0, x2 = 0, x3 = 1 Output f = 1
When x1, x2 = 0, x3 = 1, the input voltage of x1, x2 is logic value 0, x3 is logic value 1 T1, T2, T4, T5 = “ low”; T3, T6 = “ high”
T1, T2, T6 is closed; T3, T4, T5 is opened the voltage from VDD through T1 to Vf f received the logic value 1
Case 3: Input x1 = 0, x2 = 1, x3 = 0 Output f = 1
When x1, x3 = 0, x2 = 1, the input voltage of x1, x3 is logic value 0, x2 is logic value 1 T1, T3, T4, T6 = “ low”; T2, T5 = “
high” T1, T3, T5 is closed; T2, T4, T6 is opened the voltage from VDD through T1 to Vf f received the logic value 1
Case 4: Input x1 = 0, x2 = 1, x3 = 1 Output f = 1
When x2, x3 = 1, x1 = 0, the input voltage of 2, x3 is logic value 1, x1 is logic value 0 T2, T3, T5, T6 = “ high”; T1, T4 = “ low”
T1, T5, T6 is closed; T2, T3, T4 is opened the voltage from VDD through T1 to Vf f received the logic value 1
Case 5: Input x1 = 1, x2 = 0, x3 = 0 Output f = 1
When x2, x3 = 0, x1 = 1, the input voltage of 2, x3 is logic value 0, x1 is logic value 1 T2, T3, T5, T6 = “ low”; T1, T4 = “ high”
T1, T5, T6 is opened; T2, T3, T4 is closed the voltage from VDD through T2 and T3 to Vf f received the logic value 1
Case 6: Input x1 = 1, x2 = 0, x3 = 1 Output f = 0
When x1, x3 = 1, x2 = 0, the input voltage of x1, x3 is logic value 1, x2 is logic value 0 T1, T3, T4, T6 = “ high”; T2, T5 = “
low” T1, T3, T5 is opened; T2, T4, T6 is closed the voltage from VDD cannot through to Vf f received the logic value 0
Case 7: Input x1 = 1, x2 = 1, x3 = 0 Output f = 0
When x1, x2 = 1, x3 = 0, the input voltage of x1, x2 is logic value 1, x3 is logic value 0 T1, T2, T4, T5 = “ high”; T3, T6 = “ low”
T1, T2, T6 is opened; T3, T4, T5 is closed the voltage from VDD cannot through T1 to Vf f received the logic value 0
Case 8: Input x1 = 1, x2 = 1 , x3 = 1 Output f = 0
When x1, x2, x3 = 1, the input voltage of x1, x2, x3 is logic value 1 T1, T2, T3, T4, T5, T6 = “ high” T1, T2, T3 is opened, T4,
T5, T6 is closed the voltage from VDD cannot through to Vf f received the logic value 1
From truth table, we can create K-map to generate the formula of f
f X2 X3 00 01 11 10
X1
0 1 1 1 1
1 1 0 0 0
f = ~x1 + ~x2.~x3
!f = x1.(x2 + x3)
X1 X2 X3 X4 T1 T2 T3 T4 T5 T6 T7 T8 f
0 0 0 0 ON ON ON ON OFF OFF OFF OFF 1
0 0 0 1 ON ON ON OFF OFF OFF OFF ON 1
0 0 1 1 ON ON OFF OFF OFF OFF ON ON 1
0 1 0 0 ON OFF ON ON OFF ON OFF OFF 1
0 1 0 1 ON OFF ON OFF OFF ON OFF ON 1
0 1 1 0 ON OFF OFF ON OFF ON ON OFF 1
0 1 1 1 ON OFF OFF OFF OFF ON ON ON 1
1 0 0 0 OFF ON ON ON ON OFF OFF OFF 1
1 0 0 1 OFF ON ON OFF ON OFF OFF ON 0
1 0 1 0 OFF ON OFF ON ON OFF ON OFF 1
1 0 1 1 OFF ON OFF OFF ON OFF ON ON 0
1 1 0 0 OFF OFF ON ON ON ON OFF OFF 1
1 1 0 1 OFF OFF ON OFF ON ON OFF ON 0
1 1 1 0 OFF OFF OFF ON ON ON ON OFF 0
1 1 1 1 OFF OFF OFF OFF ON ON ON ON 0
Truth table
From the function:
In step 1, we can draw VDDFrom
separate into of
formula 2 PUN, we can get the formula
branches: of PDN easily
one of them is ~x1 (1), In step 2, we continue to draw PDN part.
another is (~x2 + ~x3).~x4 (2).
From T4 to Vf, we draw T5 connected to the
In branch (1), for PUN part, wePMOS
final draw T1of PUN
connected with VDD
Draw T5 (input from x1) series with (x2.x3 +
In branch (2), for PUN part,
x4)we draw VDD
connect with (T2 parallel with T3 ) (figure)
In (x2.x3 + x4), we draw T6 parallel with T7
After that, we draw T4 series with ( T2 // T3)
(figure). Then, draw T8 parallel with them and
and the output Vf before draw PUN in step 2
connect to the ground.
