Combinational Logic Implementation

Using Multiplexers

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 Use of Multiplexers

Multi-point connections
A0 A1 B0 B1
Multiple input sources
Sa MUX MUX Sb

A B

Sum

Ss DEMUX Multiple output destinations

S0 S1

2
General Concept of Using Multiplexers
n
2 data inputs, n control inputs, 1 output
n
used to connect 2 points to a single point

control signal pattern form binary index of input connected to output

Z = A' I 0 + A I 1
A Z I1 I0 A Z
0 I0 0 0 0 0
1 I1 0 0 1 0
0 1 0 1
0 1 1 0
1 0 0 0
Functional form 1 0 1 1
Logical form 1 1 0 1
1 1 1 1

Two alternative forms

for a 2:1 Mux Truth Table
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 I0 Use
2:1
of Multiplexers/Selectors
mux Z Z = A' I 0 + A I 1
I1

I0
I1
4:1 Z Z = A' B' I0 + A' B I1 + A B' I2 + A B I3
I2 mux
I3

A B

I0
I1
I2
I3
8:1 Z = A' B' C' I0 + A' B' C I1 + A' B C' I2 + A' B C I3 +
I4 mux Z
I5 A B' C' I4 + A B' C I5 + A B C' I6 + A B C I7
I6
I7 n -1
2
In general, Z = S m I
k=0 k k
A B C in minterm shorthand form for a 2 n :1 Mux
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 Design of Large Multiplexers
Large multiplexers can be implemented by cascaded smaller ones

I0 0 4:1 8:1 Control signals B and C simultaneously

I1 1 mux mux choose one of I0-I3 and I4-I7
I2 2
I3 3S S 0 2:1 Z Control signal A chooses which of the
1 0
mux upper or lower MUX's output to gate to Z
I4 1 S
0 4:1
I5 I0 0
1 mux
I6 2 I1 1 S
I7 3S S
1 0
C
I2 0
B C A 0
I3 1 S
1
Alternative 8:1 Mux Implementation C 2
Z
I4 0
3 S0 S1
I5 1 S

A B
C
I6 0
I7 1 S
5
C
 Multiplexers/Selectors as General
n-1
Purpose Blocks
2 :1 multiplexer can implement any function of n variables

n-1 control variables; remaining variable is a data input to the mux

Example:
F(A,B,C) = m0 + m2 + m6 + m7
= A' B' C' + A' B C' + A B C' + A B C

= A' B' (C') + A' B (C') + A B' (0) + A B (1)

1 0 A B C F
0 1 0 0 0 1 C 0
1 2
C F
F 0 0 1 0 C 1 4:1
0 3 8:1 0
0 1 0 1 2 MUX
0 4 MUX C 1
0 0 1 1 0 3
5 S1 S0
1 6 1 0 0 0
0 A B
1 7 S2 S1 S0 1 0 1 0
1 1 0 1
A B C 1
1 1 1 1
"Lookup Table"
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 Generalization of Multiplexer/Selector
I I … I
Logic F
1 2 n

… 0 0 0 1 1 Four possible
n-1 Mux 0 1 0 1 configurations
control variables 1 of the truth table rows
single Mux
data variable 0 In In 1 Can be expressed as
a function of In, 0, 1

Example:
G(A,B,C,D) can be implemented by an 8:1 MUX:
1 0
K-map D 1
Choose A,B,C 0 2
as control variables 8:1 G
1 3
D 4 mux
D 5
Multiplexer D 6
Implementation D 7 S2 S1 S0
TTL package efficient A B C
May be gate inefficient
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 Decoders/Demultiplexers
n
Decoder: single data input, n control inputs, 2 outputs

control inputs (called select S) represent Binary index of output to which

the input is connected

data input usually called "enable" (G)

1:2 Decoder: 3:8 Decoder:

O0 = G • S; O1 = G • S O0 = G • S0 • S1 • S2

O1 = G • S0 • S1 • S2
2:4 Decoder:
O0 = G • S0 • S1 O2 = G • S0 • S1 • S2

O1 = G • S0 • S1 O3 = G • S0 • S1 • S2

O2 = G • S0 • S1 O4 = G • S0 • S1 • S2

O3 = G • S0 • S1 O5 = G • S0 • S1 • S2

O6 = G • S0 • S1 • S2

O7 = G • S0 • S1 • S2 8
 Decoder as a Logic Building Block
0 ABC
1 ABC
2 ABC Decoder Generates Appropriate
Enb
3:8 3 ABC Minterm based on Control Signals
dec 4 ABC
5 ABC
6 ABC
S2 S1 S0 7 ABC

A B C

Example Function:
F1 = A' B C' D + A' B' C D + A B C D
F2 = A B C' D' + A B C
F3 = (A' + B' + C' + D')

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 Decoder as a Logic Building Block
0 ABCD
1 ABCD
F1
2 ABCD
3 ABCD
4 ABCD
5 ABCD
Enb 6 ABCD
4:16
7 ABCD
dec
8 ABCD F2
9 ABCD
10 ABCD
11 ABCD
12 ABCD
13 ABCD
14 ABCD
F3
S3 S2 S1 S0 15 ABCD

A B C D
If active low enable, then use NAND gates!

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