Scribd
Upload
116 views22 pages

Lab 6 Firna Frilanisa

The document describes the design and testing of two 4-bit registers. The first register (1-1) has synchronous reset and load functionality. The second register (1-2) adds a synchronous set signal. VHDL code and testbenches are provided to implement and test each register design. The inputs and outputs are mapped to switches and LEDs on the FPGA board for hardware verification.

Uploaded by

Firna Frilanisa
Copyright
© © All Rights Reserved
We take content rights seriously. If you suspect this is your content, claim it here.
Available Formats
Download as DOCX, PDF, TXT or read online on Scribd
116 views22 pages

Lab 6 Firna Frilanisa

The document describes the design and testing of two 4-bit registers. The first register (1-1) has synchronous reset and load functionality. The second register (1-2) adds a synchronous set signal. VHDL code and testbenches are provided to implement and test each register design. The inputs and outputs are mapped to switches and LEDs on the FPGA board for hardware verification.

Uploaded by

Firna Frilanisa
Copyright
© © All Rights Reserved
We take content rights seriously. If you suspect this is your content, claim it here.
Available Formats
Download as DOCX, PDF, TXT or read online on Scribd

LAB 6

FIRNA FRILANISA / 175060307111004

Metode / Rencana Pengerjaan :


1. Memahami rangkaian gerbang logika.
2. Menentukan model VHDL.
3. Memasukkan input/output, variabel, dll.
4. Menentukan alur proses sesuai dengan model.
5. Membuat kode implementasi.
6. Membuat test bench.
7. Mengecek syntax.
8. Melakukan simulasi.

1-1. Model a 4-bit register with synchronous reset and load using the model
provided above. Develop a testbench and simulate the design. Assign Clk
to SW0, D input to SW4-SW1, reset to SW5, load to SW6, and output Q to
LED3-LED0. Verify the design in hardware.

Desain
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;

entity lab6_1_1 is
Port ( clk : in STD_LOGIC;
load : in STD_LOGIC;
reset : in STD_LOGIC;
D : in STD_LOGIC_VECTOR (3 downto 0);
Q : out STD_LOGIC_VECTOR (3 downto 0));
end lab6_1_1;

architecture Behavioral of lab6_1_1 is

begin

process (clk) begin


if rising_edge(clk) then
if (reset = '1') then
Q <= "0000";
elsif (load = '1') then
Q <= D;
end if;
end if;
end process;

end Behavioral;

Testbench :
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;

-- Uncomment the following library declaration if using


-- arithmetic functions with Signed or Unsigned values
--USE ieee.numeric_std.ALL;

ENTITY tb_lab6_1_1 IS
END tb_lab6_1_1;

ARCHITECTURE behavior OF tb_lab6_1_1 IS

-- Component Declaration for the Unit Under Test (UUT)

COMPONENT lab6_1_1
PORT(
clk : IN std_logic;
load : IN std_logic;
reset : IN std_logic;
D : IN std_logic_vector(3 downto 0);
Q : OUT std_logic_vector(3 downto 0)
);
END COMPONENT;

--Inputs
signal clk : std_logic := '0';
signal load : std_logic := '0';
signal reset : std_logic := '0';
signal D : std_logic_vector(3 downto 0) := (others => '0');

--Outputs
signal Q : std_logic_vector(3 downto 0);

-- Clock period definitions

BEGIN

-- Instantiate the Unit Under Test (UUT)


uut: lab6_1_1 PORT MAP (
clk => clk,
load => load,
reset => reset,
D => D,
Q => Q
);

-- Stimulus process
stim_proc: process
begin

clk <= '0'; load <= '0'; reset <= '0'; D <= "0000"; wait for 100 ns;
clk <= '1'; load <= '0'; reset <= '0'; D <= "0000"; wait for 100 ns;
clk <= '0'; load <= '0'; reset <= '0'; D <= "0101"; wait for 100 ns;
clk <= '1'; load <= '0'; reset <= '0'; D <= "0101"; wait for 100 ns;
clk <= '0'; load <= '0'; reset <= '0'; D <= "0101"; wait for 100 ns;
clk <= '1'; load <= '0'; reset <= '0'; D <= "0101"; wait for 100 ns;
clk <= '0'; load <= '1'; reset <= '0'; D <= "0101"; wait for 100 ns;
clk <= '1'; load <= '1'; reset <= '0'; D <= "0101"; wait for 100 ns;
clk <= '0'; load <= '0'; reset <= '0'; D <= "1001"; wait for 100 ns;
clk <= '1'; load <= '0'; reset <= '0'; D <= "1001"; wait for 100 ns;
clk <= '0'; load <= '0'; reset <= '0'; D <= "1001"; wait for 100 ns;
clk <= '1'; load <= '0'; reset <= '0'; D <= "1001"; wait for 100 ns;
clk <= '0'; load <= '1'; reset <= '0'; D <= "1001"; wait for 100 ns;
clk <= '1'; load <= '1'; reset <= '0'; D <= "1001"; wait for 100 ns;
clk <= '0'; load <= '0'; reset <= '0'; D <= "1001"; wait for 100 ns;
clk <= '1'; load <= '0'; reset <= '1' after 50 ns; D <= "1001"; wait for 100 ns;
clk <= '0'; load <= '0'; reset <= '1'; D <= "1001"; wait for 100 ns;
clk <= '1'; load <= '0'; reset <= '1'; D <= "1001"; wait for 100 ns;
clk <= '0'; load <= '0'; reset <= '1'; D <= "1001"; wait for 100 ns;
clk <= '1'; load <= '1' after 50 ns; reset <= '1'; D <= "1001"; wait for 100 ns;
clk <= '0'; load <= '1'; reset <= '1'; D <= "1001"; wait for 100 ns;
clk <= '1'; load <= '0' after 50 ns; reset <= '1'; D <= "1001"; wait for 100 ns;
clk <= '0'; load <= '0'; reset <= '1'; D <= "1001"; wait for 100 ns;
clk <= '1'; load <= '0'; reset <= '1'; D <= "1001"; wait for 100 ns;
clk <= '0'; load <= '0'; reset <= '0'; D <= "1001"; wait for 100 ns;
clk <= '1'; load <= '0'; reset <= '0'; D <= "1001"; wait for 100 ns;
clk <= '0'; load <= '0'; reset <= '0'; D <= "1001"; wait for 100 ns;
clk <= '1'; load <= '0'; reset <= '0'; D <= "1001"; wait for 100 ns;
clk <= '0'; load <= '1'; reset <= '0'; D <= "1001"; wait for 100 ns;
clk <= '1'; load <= '1'; reset <= '0'; D <= "1001"; wait for 100 ns;

end process;

END;
1-2. Model a 4-bit register with synchronous reset, set, and load signals. Assign
Clk to SW0, D input to SW4-SW1, reset to SW5, set to SW6, load to SW7, and
output Q to LED3-LED0. Verify the design in hardware.

Desain
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;

entity lab6_1_2 is
Port ( clk : in STD_LOGIC;
load : in STD_LOGIC;
reset : in STD_LOGIC;
set : in STD_LOGIC;
D : in STD_LOGIC_VECTOR (3 downto 0);
Q : out STD_LOGIC_VECTOR (3 downto 0));
end lab6_1_2;

architecture Behavioral of lab6_1_2 is

begin

process (clk) begin


if rising_edge(clk) then
if (reset = '0') then
Q <= "0000";
elsif (load = '1') and (set = '1') then
Q <= D;
end if;
end if;
end process;

end Behavioral;

Testbench
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;

-- Uncomment the following library declaration if using


-- arithmetic functions with Signed or Unsigned values
--USE ieee.numeric_std.ALL;

ENTITY tb_lab6_1_2 IS
END tb_lab6_1_2;
ARCHITECTURE behavior OF tb_lab6_1_2 IS

-- Component Declaration for the Unit Under Test (UUT)

COMPONENT lab6_1_2
PORT(
clk : IN std_logic;
load : IN std_logic;
reset : IN std_logic;
set : IN std_logic;
D : IN std_logic_vector(3 downto 0);
Q : OUT std_logic_vector(3 downto 0)
);
END COMPONENT;

--Inputs
signal clk : std_logic := '0';
signal load : std_logic := '0';
signal reset : std_logic := '0';
signal set : std_logic := '0';
signal D : std_logic_vector(3 downto 0) := (others => '0');

--Outputs
signal Q : std_logic_vector(3 downto 0);

-- Clock period definitions


-- constant clk_period : time := 10 ns;

BEGIN

-- Instantiate the Unit Under Test (UUT)


uut: lab6_1_2 PORT MAP (
clk => clk,
load => load,
reset => reset,
set => set,
D => D,
Q => Q
);

-- Clock process definitions


-- clk_process :process
-- begin
-- clk <= '0';
-- wait for clk_period/2;
-- clk <= '1';
-- wait for clk_period/2;
-- end process;

-- Stimulus process
stim_proc: process
begin

clk <= '0'; load <= '0'; reset <= '0'; set <= '0'; D <= "0000"; wait for 100 ns;
clk <= '1'; load <= '0'; reset <= '0'; set <= '0'; D <= "0000"; wait for 100 ns;
clk <= '0'; load <= '0'; reset <= '0'; set <= '0'; D <= "0101"; wait for 100 ns;
clk <= '1'; load <= '0'; reset <= '0'; set <= '0'; D <= "0101"; wait for 100 ns;
clk <= '0'; load <= '0'; reset <= '0'; set <= '0'; D <= "0101"; wait for 100 ns;
clk <= '1'; load <= '0'; reset <= '0'; set <= '0'; D <= "0101"; wait for 100 ns;
clk <= '0'; load <= '1'; reset <= '0'; set <= '0'; D <= "0101"; wait for 100 ns;
clk <= '1'; load <= '1'; reset <= '0'; set <= '0'; D <= "0101"; wait for 100 ns;
clk <= '0'; load <= '0'; reset <= '0'; set <= '0'; D <= "1001"; wait for 100 ns;
clk <= '1'; load <= '0'; reset <= '0'; set <= '0'; D <= "1001"; wait for 100 ns;
clk <= '0'; load <= '0'; reset <= '0'; set <= '0'; D <= "1001"; wait for 100 ns;
clk <= '1'; load <= '0'; reset <= '0'; set <= '0'; D <= "1001"; wait for 100 ns;
clk <= '0'; load <= '1'; reset <= '0'; set <= '0'; D <= "1001"; wait for 100 ns;
clk <= '1'; load <= '1'; reset <= '0'; set <= '0'; D <= "1001"; wait for 100 ns;
clk <= '0'; load <= '0'; reset <= '0'; set <= '0'; D <= "1001"; wait for 100 ns;
clk <= '1'; load <= '0'; reset <= '1' after 50 ns; set <= '1' after 50 ns; D <=
"1001"; wait for 100 ns;
clk <= '0'; load <= '0'; reset <= '1'; set <= '1'; D <= "1001"; wait for 100 ns;
clk <= '1'; load <= '0'; reset <= '1'; set <= '1'; D <= "1001"; wait for 100 ns;
clk <= '0'; load <= '0'; reset <= '1'; set <= '1'; D <= "1001"; wait for 100 ns;
clk <= '1'; load <= '1' after 50 ns; reset <= '1'; set <= '1'; D <= "1001"; wait for
100 ns;
clk <= '0'; load <= '1'; reset <= '1'; set <= '1'; D <= "1001"; wait for 100 ns;
clk <= '1'; load <= '0' after 50 ns; reset <= '1'; set <= '1'; D <= "1001"; wait for
100 ns;
clk <= '0'; load <= '0'; reset <= '1'; set <= '1'; D <= "1001"; wait for 100 ns;
clk <= '1'; load <= '0'; reset <= '1'; set <= '1'; D <= "1001"; wait for 100 ns;
clk <= '0'; load <= '0'; reset <= '0'; set <= '0'; D <= "1001"; wait for 100 ns;
clk <= '1'; load <= '0'; reset <= '0'; set <= '0'; D <= "1001"; wait for 100 ns;
clk <= '0'; load <= '0'; reset <= '0'; set <= '0'; D <= "1001"; wait for 100 ns;
clk <= '1'; load <= '0'; reset <= '0'; set <= '0'; D <= "1001"; wait for 100 ns;
clk <= '0'; load <= '1'; reset <= '0'; set <= '0'; D <= "1001"; wait for 100 ns;
clk <= '1'; load <= '1'; reset <= '0'; set <= '0'; D <= "1001"; wait for 100 ns;

end process;

END;
1-3. Model a 1-bit delay line shift register using the above code. Develop a
testbench and simulate the design using the stimuli provided below. Assign
Clk to SW0, ShiftIn to SW1, and output ShiftOut to LED0. Verify the design in
hardware.

Desain
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;

entity lab6_1_3 is
Port ( clk : in STD_LOGIC;
shift_in : in STD_LOGIC;
shift_out : out STD_LOGIC);
end lab6_1_3;

architecture Behavioral of lab6_1_3 is

signal shift_reg : std_logic_vector (2 downto 0);

begin

process (clk) begin


if rising_edge(clk) then
shift_reg <= shift_reg(1 downto 0) & shift_in;
end if;
shift_out <= shift_reg(2);
end process;

end Behavioral;

Testbench
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;

-- Uncomment the following library declaration if using


-- arithmetic functions with Signed or Unsigned values
--USE ieee.numeric_std.ALL;

ENTITY tb_lab6_1_3 IS
END tb_lab6_1_3;

ARCHITECTURE behavior OF tb_lab6_1_3 IS

-- Component Declaration for the Unit Under Test (UUT)


COMPONENT lab6_1_3
PORT(
clk : IN std_logic;
shift_in : IN std_logic;
shift_out : OUT std_logic
);
END COMPONENT;

--Inputs
signal clk : std_logic := '0';
signal shift_in : std_logic := '0';

--Outputs
signal shift_out : std_logic;

-- Clock period definitions


constant clk_period : time := 50 ns;

BEGIN

-- Instantiate the Unit Under Test (UUT)


uut: lab6_1_3 PORT MAP (
clk => clk,
shift_in => shift_in,
shift_out => shift_out
);

-- Clock process definitions


clk_process :process
begin
clk <= '0';
wait for clk_period/2;
clk <= '1';
wait for clk_period/2;
end process;

-- Stimulus process
stim_proc: process
begin

-- insert stimulus here


shift_in <= '0'; wait for 50 ns;
shift_in <= '1'; wait for 50 ns;
shift_in <= '1'; wait for 50 ns;
end process;

END;

1-4. Model a 4-bit parallel in left shift register using the above code. Develop a
testbench and simulate the design using the stimuli provided below. Assign
Clk to SW0, ParallelIn to SW4-SW1, load to SW5, ShiftEn to SW6, ShiftIn to
SW7, RegContent to LED3-LED0, and ShiftOut to LED7. Verify the design in
hardware.

Desain
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;

entity lab6_1_4 is
Port ( clk : in STD_LOGIC;
load : in STD_LOGIC;
shift_en : in STD_LOGIC;
shift_in : in STD_LOGIC;
parallel_in : in STD_LOGIC_VECTOR (3 downto 0);
shift_out : out STD_LOGIC);
end lab6_1_4;

architecture Behavioral of lab6_1_4 is

signal shift_reg : std_logic_vector (3 downto 0);

begin

process (clk) begin


if rising_edge(clk) then
if (load = '1') then
shift_reg <= parallel_in;
elsif (shift_en = '1') then
shift_reg <= shift_reg(2 downto 0) & shift_in;
end if;
end if;
shift_out <= shift_reg(3);

end process;
end Behavioral;

Testbench
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;

-- Uncomment the following library declaration if using


-- arithmetic functions with Signed or Unsigned values
--USE ieee.numeric_std.ALL;

ENTITY tb_lab6_1_4 IS
END tb_lab6_1_4;

ARCHITECTURE behavior OF tb_lab6_1_4 IS

-- Component Declaration for the Unit Under Test (UUT)

COMPONENT lab6_1_4
PORT(
clk : IN std_logic;
load : IN std_logic;
shift_en : IN std_logic;
shift_in : IN std_logic;
parallel_in : IN std_logic_vector(3 downto 0);
shift_out : OUT std_logic
);
END COMPONENT;

--Inputs
signal clk : std_logic := '0';
signal load : std_logic := '0';
signal shift_en : std_logic := '0';
signal shift_in : std_logic := '0';
signal parallel_in : std_logic_vector(3 downto 0) := (others => '0');

--Outputs
signal shift_out : std_logic;

-- Clock period definitions


constant clk_period : time := 10 ns;

BEGIN

-- Instantiate the Unit Under Test (UUT)


uut: lab6_1_4 PORT MAP (
clk => clk,
load => load,
shift_en => shift_en,
shift_in => shift_in,
parallel_in => parallel_in,
shift_out => shift_out
);

-- Clock process definitions


clk_process :process
begin
clk <= '0';
wait for clk_period/2;
clk <= '1';
wait for clk_period/2;
end process;

-- Stimulus process
stim_proc: process
begin

load <= '0'; shift_en <= '0'; parallel_in <= "0000";


wait for 20 ns;
load <= '0'; shift_en <= '0'; parallel_in <= "0101";
wait for 40 ns;
load <= '1'; shift_en <= '0'; parallel_in <= "0101";
wait for 20 ns;
load <= '0'; shift_en <= '0'; parallel_in <= "0101";
wait for 20 ns;
load <= '0'; shift_en <= '1'; parallel_in <= "0101";
wait for 70 ns;
load <= '0'; shift_en <= '1'; parallel_in <= "1001";
wait for 30 ns;
load <= '1'; shift_en <= '1'; parallel_in <= "1001";
wait for 20 ns;
load <= '0'; shift_en <= '1'; parallel_in <= "1001";
wait for 75 ns;
load <= '1'; shift_en <= '1'; parallel_in <= "1001";
wait for 20 ns;

end process;

END;

2-1. Design a 8-bit counter using T flip-flops, extending the above structure to 8-
bits. Your design needs to be hierarchical, using a T flip-flop in behavioral
modeling, and rest either in dataflow or gate-level modeling. Develop a
testbench and validate the design. Assign Clock input to SW0, Clear_n to
SW1, Enable to SW2, and Q to LED7-LED0. Implement the design and verify
the functionality in hardware.

Desain
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;

entity lab6_2_1 is
Port ( clk : in STD_LOGIC;
En : in STD_LOGIC;
clr : in STD_LOGIC;
Q : inout STD_LOGIC_VECTOR (7 downto 0));
end lab6_2_1;

architecture Structural of lab6_2_1 is

component T_FlipFlop is
Port ( T : in STD_LOGIC;
En : in STD_LOGIC;
clk : in STD_LOGIC;
clr : in STD_LOGIC;
Q : inout STD_LOGIC);
end component;

signal and_1 : std_logic;


signal and_2 : std_logic;
signal and_3 : std_logic;
signal and_4 : std_logic;
signal and_5 : std_logic;
signal and_6 : std_logic;
signal and_7 : std_logic;

begin

and_1 <= En and Q (0);


and_2 <= and_1 and Q(1);
and_3 <= and_2 and Q(2);
and_4 <= and_3 and Q(3);
and_5 <= and_4 and Q(4);
and_6 <= and_5 and Q(5);
and_7 <= and_6 and Q(6);
TFF0 : T_flipflop port map (
T => En,
En => En,
clk => clk,
clr => clr,
Q => Q(0)
);
TFF1 : T_flipflop port map (
T => and_1,
En => En,
clk => clk,
clr => clr,
Q => Q(1)
);
TFF2 : T_flipflop port map (
T => and_2,
En => En,
clk => clk,
clr => clr,
Q => Q(2)
);
TFF3 : T_flipflop port map (
T => and_3,
En => En,
clk => clk,
clr => clr,
Q => Q(3)
);
TFF4 : T_flipflop port map (
T => and_4,
En => En,
clk => clk,
clr => clr,
Q => Q(4)
);
TFF5 : T_flipflop port map (
T => and_5,
En => En,
clk => clk,
clr => clr,
Q => Q(5)
);
TFF6 : T_flipflop port map (
T => and_6,
En => En,
clk => clk,
clr => clr,
Q => Q(6)
);
TFF7 : T_flipflop port map (
T => and_7,
En => En,
clk => clk,
clr => clr,
Q => Q(7)
);

end Structural;

Testbench
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;

-- Uncomment the following library declaration if using


-- arithmetic functions with Signed or Unsigned values
--USE ieee.numeric_std.ALL;

ENTITY tb_lab6_2_1 IS
END tb_lab6_2_1;

ARCHITECTURE behavior OF tb_lab6_2_1 IS

-- Component Declaration for the Unit Under Test (UUT)

COMPONENT lab6_2_1
PORT(
clk : IN std_logic;
En : IN std_logic;
clr : IN std_logic;
Q : INOUT std_logic_vector(7 downto 0)
);
END COMPONENT;

--Inputs
signal clk : std_logic := '0';
signal En : std_logic := '0';
signal clr : std_logic := '0';

--BiDirs
signal Q : std_logic_vector(7 downto 0);

-- Clock period definitions


constant clk_period : time := 10 ns;
BEGIN

-- Instantiate the Unit Under Test (UUT)


uut: lab6_2_1 PORT MAP (
clk => clk,
En => En,
clr => clr,
Q => Q
);

-- Clock process definitions


clk_process :process
begin
clk <= '0';
wait for clk_period/2;
clk <= '1';
wait for clk_period/2;
end process;

-- Stimulus process
stim_proc: process
begin
clr <= '0';
En <= '0';
wait for 20 ns;
En <= '1';
clr <= '0';
wait for 20 ns;
En <= '1';
clr <= '1';
wait for 80 ns;
En <= '0';
wait for 80 ns;
En <= '1';
wait for 300 ns;
end process;

END;

2-2. Modify the 8-bit counter using D flip-flops. The design should be hierarchical,
defining D flip-flop in behavioral modeling, creating T flip-flop from the D flip-
flop, implementing additional functionality using dataflow modeling. Assign
Clock input to SW0, Clear_n to SW1, Enable to SW2, and Q to LED7-LED0.
Implement the design and verify the functionality in hardware.
Desain
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;

entity lab6_2_2 is
Port ( D : in STD_LOGIC;
clk : in STD_LOGIC;
clr : in STD_LOGIC;
Q : inout STD_LOGIC_VECTOR (7 downto 0));
end lab6_2_2;

architecture Structural of lab6_2_2 is

component D_FlipFlop is
Port ( D : in STD_LOGIC;
clk : in STD_LOGIC;
clr : in STD_LOGIC;
Q : inout STD_LOGIC);
end component;

begin

DFF0 : D_Flipflop port map (


D => D xor Q(0),
clk => clk,
clr => clr,
Q => Q(0)
);
DFF1 : D_Flipflop port map (
D => Q(0) xor Q(1),
clk => clk,
clr => clr,
Q => Q(1)
);
DFF2 : D_Flipflop port map (
D => Q(1) xor Q(2),
clk => clk,
clr => clr,
Q => Q(2)
);
DFF3 : D_Flipflop port map (
D => Q(2) xor Q(3),
clk => clk,
clr => clr,
Q => Q(3)
);
DFF4 : D_Flipflop port map (
D => Q(3) xor Q(4),
clk => clk,
clr => clr,
Q => Q(4)
);
DFF5 : D_Flipflop port map (
D => Q(4) xor Q(5),
clk => clk,
clr => clr,
Q => Q(5)
);
DFF6 : D_Flipflop port map (
D => Q(5) xor Q(6),
clk => clk,
clr => clr,
Q => Q(6)
);
DFF7 : D_Flipflop port map (
D => Q(6) xor Q(7),
clk => clk,
clr => clr,
Q => Q(7)
);

end Structural;

Testbench
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;

-- Uncomment the following library declaration if using


-- arithmetic functions with Signed or Unsigned values
--USE ieee.numeric_std.ALL;

ENTITY tb_lab6_2_2 IS
END tb_lab6_2_2;

ARCHITECTURE behavior OF tb_lab6_2_2 IS

-- Component Declaration for the Unit Under Test (UUT)

COMPONENT lab6_2_2
PORT(
D : IN std_logic;
clk : IN std_logic;
clr : IN std_logic;
Q : INOUT std_logic_vector(7 downto 0)
);
END COMPONENT;

--Inputs
signal D : std_logic := '0';
signal clk : std_logic := '0';
signal clr : std_logic := '0';

--BiDirs
signal Q : std_logic_vector(7 downto 0);

-- Clock period definitions


constant clk_period : time := 10 ns;

BEGIN

-- Instantiate the Unit Under Test (UUT)


uut: lab6_2_2 PORT MAP (
D => D,
clk => clk,
clr => clr,
Q => Q
);

-- Clock process definitions


clk_process :process
begin
clk <= '0';
wait for clk_period/2;
clk <= '1';
wait for clk_period/2;
end process;

-- Stimulus process
stim_proc: process
begin
clr <= '0';
D <= '0';
wait for 20 ns;
D <= '1';
clr <= '0';
wait for 20 ns;
D <= '1';
clr <= '1';
wait for 80 ns;
D <= '0';
wait for 80 ns;
D <= '1';
wait for 300 ns;
end process;

END;

2-3. Model a 4-bit up-counter with synchronous load, enable, and clear as given
in the code above. Develop a testbench (similar to the waveform shown
below) and verify the design works. Assign Clock input to SW0, Clear to
SW1, Enable to SW2, Load to SW3, and Q to LED3-LED0. Implement the
design and verify the functionality in hardware.

Desain
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.NUMERIC_STD.ALL;

entity lab6_2_3 is
Port ( clk : in STD_LOGIC;
En : in STD_LOGIC;
clr : in STD_LOGIC;
load : in STD_LOGIC;
count : inout STD_LOGIC_VECTOR (3 downto 0);
cnt_done : inout STD_LOGIC;
Q : out STD_LOGIC_VECTOR (3 downto 0));
end lab6_2_3;

architecture Behavioral of lab6_2_3 is

begin

cnt_done <= not (count(3) or count(2) or count(1) or count(0));


Q <= count;
process (clk) begin
if rising_edge(clk) then
if (clr = '1') then
count <= "0000";
elsif (En = '1') then
if ((load or cnt_done) = '1') then
count <= "1010";
else
count <= STD_LOGIC_VECTOR(unsigned(count) - 1);
end if;
end if;
end if;
end process;

end Behavioral;

Testbench
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;

-- Uncomment the following library declaration if using


-- arithmetic functions with Signed or Unsigned values
--USE ieee.numeric_std.ALL;

ENTITY tb_lab6_2_3 IS
END tb_lab6_2_3;

ARCHITECTURE behavior OF tb_lab6_2_3 IS

-- Component Declaration for the Unit Under Test (UUT)

COMPONENT lab6_2_3
PORT(
clk : IN std_logic;
En : IN std_logic;
clr : IN std_logic;
load : IN std_logic;
count : INOUT std_logic_vector(3 downto 0);
cnt_done : INOUT std_logic;
Q : OUT std_logic_vector(3 downto 0)
);
END COMPONENT;

--Inputs
signal clk : std_logic := '0';
signal En : std_logic := '0';
signal clr : std_logic := '0';
signal load : std_logic := '0';

--BiDirs
signal count : std_logic_vector(3 downto 0);
signal cnt_done : std_logic;
--Outputs
signal Q : std_logic_vector(3 downto 0);

-- Clock period definitions


constant clk_period : time := 10 ns;

BEGIN

-- Instantiate the Unit Under Test (UUT)


uut: lab6_2_3 PORT MAP (
clk => clk,
En => En,
clr => clr,
load => load,
count => count,
cnt_done => cnt_done,
Q => Q
);

-- Clock process definitions


clk_process :process
begin
clk <= '0';
wait for clk_period/2;
clk <= '1';
wait for clk_period/2;
end process;

-- Stimulus process
stim_proc: process
begin
En <= '0';
clr <= '0';
load <= '0';
wait for 20 ns;
En <= '1';
wait for 20 ns;
clr <= '1';
wait for 20 ns;
clr <= '0';
wait for 20 ns;
load <= '1';
wait for 10 ns;
load <= '0';
wait for 80 ns;
En <= '0';
wait for 40 ns;
En <= '1';
wait for 80 ns;
end process;

END;

You might also like