ICM 2010

The 22nd
International Conference
on Microelctronics

Advance Program
December 19-22, 2010

Sofitel Elgezirah, Cairo, Egypt

 ICM 2010 Welcome Message
Welcome to the 2010 IEEE/ICM International Conference on Microelectronics (ICM 2010). This year's conference marks the 22nd
anniversary of ICM, which is progressing at an excellent rate both in terms of quality and quantity. ICM 2010 will be held at The
Sofitel Cairo El Gezirah, Cairo. Sofitel Cairo El Gezirah is the luxury hotel of Cairo, is located on the Nile River, in the heart of the
city.

ICM 2010 offers a unique forum for researchers and practitioners from academia, industry and government to share their expertise
and research findings in all areas of microelectronics and its applications. This year's conference includes an outstanding technical
program, distinguished keynote speakers, and insightful tutorials. ICM2010's technical program consists of several parallel tracks
every day and it will last for four days including Sunday that is dedicated for tutorials. Each track consists of several sessions of top
quality papers. The topics covered in the program include analog and RF circuit design techniques, Digital Signal and data
processing, Wireless communication systems, Nonlinear circuits, Systems on Chip (SoCs), VLSI for signal and Image processing,
Simulation (process, device, circuit, logic, timing, functional), Layout Parallel embedded systems, Micro / Nanoelectronics, Device
characterization and modeling, Device physics and novel structures, Process technology, MEMS Devices among others.

We received this year a large number of high quality papers. Only high quality papers have been accepted with an acceptance ratio
is around 45%. This speaks a lot about the diligent work of the technical program committee chairs, track chairs, technical program
committee and reviewers. The accepted papers come from over 40 countries with representation from academia, industry, and
government.

Many individuals have contributed to the success of ICM 2010. Our sincere appreciations go to all authors including those whose
papers were not included in the program. Many thanks to our distinguished keynote speakers and tutorial instructors for their
valuable contribution to the conference. Special thanks to the technical program committee chairs, Prof. M. Alioto and Prof. M.
Elgamal. Many thanks go to the track chairs, technical program committee members and reviewers for their timely work and efforts.
We thank the excellent work by the Chair of the organizing committee; Prof. Nabil Sabry for taking care of the local arrangement.
Our honorary Chair, Prof. Medhat Haroun, Dean of the School of Sciences and Engineering at the American University in Cairo,
has supported us in every way possible. Thanks to Prof. M. Sawan and Prof. E. Alarcon for putting together an excellent tutorial
program. Special thanks go to the publication chair, Eng. Amr Abdelzaher, for his outstanding work and dedication.

Finally, we would like to thank all of our sponsors: Ministry of Communications and Information Technology, Mentor Graphics
Egypt, Vodafone Egypt, Silicon Vision, MEMS Vision, and the American University in Cairo.

On behalf of the 2010 IEEE International Conference on Microelectronics, ICM 2010, we welcome you in Egypt. Enjoy the program
and your stay.

Mohab Anis and Mohamed Elmasry

General Chairs, ICM 2010

Mohab Anis Mohammad Elmasry

ICM 2009 General Chairs

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 Conference Committees

Honorary Chairs

• Medhat Haroun, Dean of School of Sciences and Engineering, The American University in Cairo

General Chairs

• M. Anis, The American University in Cairo, Egypt

• M. Elmasry, University of Waterloo, Canada

Technical Program Committee Chairs

• M. Alioto, University of Siena, Italy

• M. Elgamal, McGill University, Canada

Organizing Committee Chair

• M. Sabry, Mansoura university, Egypt

Tutorials Chairs

• M. Sawan, EPM, Canada

• E. Alarcon, UPC, Spain

Publication Chair

• A. AbdelZaher, Cairo University, Egypt

Sponsorship Chair

• M. Anis, The American University in Cairo, Egypt

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 Technical Program Committee

• Karim Abd-Meraim, University of Sharjah, UAE

• B. Soudan, University of Sharjah, UAE
• Esam Abdelraheem, University of Windsor, Canada
• Mohamed Abid, National Engineering School of Sfax, Tunisia
• Zine-Eddine Abid, University of Western Ontario, Canada
• Hassan Aboushady, University of Paris VI, France
• Mohamed Abu-rahma, Qualcomm Corp.
• Mohammed Abuelma'ati, King Fahd University of Petroleum and Minerals, Saudi Arabia
• Massimo Alioto, University of Siena, Italy
• Wael Badawy, University of Calgary, Canada
• Sergio Callegari, University of Bologna, Italy
• Masud Chowdhury, University of Illinois at Chicago, USA
• Bernard Courtois, TIMA, France
• Mohamed Dessouky, Ain Shams University, Egypt
• Mourad El-Gamal, McGill University, Canada
• Ahmed Eltawil, University of California-Irvine, USA
• Mohamed Essaaidi, Abdelmalek Essaadi University, Morocco
• Wael Fikry, Ain Shams University, Egypt
• Zbigniew Galias, AGH-University of Science and Technology, Poland
• Fayez Gebali, University of Victoria, Canada
• Hani Ghali, Ain Shams University, Egypt
• Anas Hamoui, McGill University, Canada
• Hassan Hassan, University of Waterloo, Canada
• Mona Hella, Rensselaer Polytechnic Institute, USA
• Shiyan Hu, Michigan Technological University, USA
• Diaa Khalil, Ain Shams University, Egypt
• Nabil Khachab, Kuwait University, Kuwait
• Marie Meverve Louerat, LIP6, France
• Henry Leung, University of Calgary, Canada
• Mourad Loulou, LETI-Sfax, Tunisia
• Len MacEachern, Carlton University, Canada
• Abdalla Naem, National Semiconductor, USA
• Yoshifumi Nishio, Tokushima University, Japan
• Serdar Ozoguz, Istanbul Technical University, Turkey
• Mohamed-Nabil Sabry, Mansoura University, Egypt
• Khaled Salama, Rensselaer Polytechnic Institute, USA
• Ashraf Salem, Ain Shams University, Egypt
• Mohamed Sawan, Ecole Polytechnic de Montreal, Canada
• Sherif Sedky, AUC, Egypt
• Khaled Sharaf, Ain Shams University, Egypt
• Khaled Shehata, AAST, Egypt
• Wallace Tang, City University of Hong Kong, China
• Tetsushi Ueta, Tokushima University, Japan
• Mohamed Zahran, City University of New York, USA
• Shawki Areibi, University of Guelph, Canada
• Serag Habib, University of Cairo, Egyp

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 Track Chairs

Analog Circuits Chairs

Mohamed Dessouky, Mentor Graphics, Egypt

Frederic Nabki, University of Quebec at Montreal, Canada

Device Modeling and Characterization Chair

Hani Ragai, French University in Egypt

Wireless and RF Circuits and Systems Chair

Mona Hella, Rensselaer Polytechnic Institute, USA

Architectures & VLSI Systems Chair

Sergio Bampi, Federal University of Rio Grande do Sul, Brazil

CAD for VLSI Chair

Ricardo Reis, Federal University of Rio Grande do Sul, Brazil

Digital Circuits Chair

Masud Chowdhury, University of Illinois at Chicago, USA

MEMS and Emerging Devices Chair

Frederic Nabki, University of Quebec at Montreal, Canada

Nanoelectronics Chair

Volkan Kursun ,The Hong Kong University of Science and Technology, Hong Kong

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 Social Program: Banquet

Date: Tuesday December 21

Time: 18:45-22:30

Location: Beit ElSehemy, Old Cairo

Departure at 18:45 by bus

Return to Sofitel El Gezirah Hotel: 23:00 by bus

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Conference Center at Sofitel Elgezirah

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Conference Sponsors

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 ICM 2010 Program
Day Time

Sun 09:30-12:30 Tutorial 1 Tutorial 2 Tutorial 3

14:30-17:30 Tutorial 4 Tutorial 5 Tutorial 6

Mon 09:00-09:45 Opening Ceremony

09:45-10:45 Keynote address 1

Session 2: Leakage and

Session 1: Analog-to-Digital Energy Efficiency in High Session 3: Devices, Modeling
11:15-13:00
Converters Performance Integrated and Characterization
Circuits

Session 4: Improved Design

Session 5: Timing Circuits Session 6: System Design
14:45-16:30 Techniques for Arithmetic
and Optical Links Methodologies I
Circuits

Panel: Challenges of Nano

Electronics Industry Ecosystem
16:45-18:15 in the Arab Region

Tue 09:30-10:30 Keynote address 2

Session 7: Sensing Systems and Session 8: Multicore and Session 9: RF Design,

11:00-12:45
MEMS Embedded Systems Analysis and Techniques

Session 11: Advances in Session 12: Special Session

Session 10: Voltage Regulators Graphene and Carbon “Networks-on-Chip/System
14:30-16:15
and Analog Techniques Nanotube Device and Wire on-Chip Design, Optimization
Technologies and Validation”
Session 13: Special Session
Session 14: Modeling and Session 15: Special Session
“Networks-on-Chip/System-on-
16:30-18:15 Design with Emerging “Crypto-Biometric
Chip Design, Optimization and
Devices Hardware”
Validation”

Wed 09:30-10:30 Keynote address 3

Session 16: Analog Techniques Session 18: Advanced Memory

11:00-12:45 Session 17: CAD Tools
I Design
Session 20: Innovative
Session 19: Special Session Design and Analysis Session 21: VLSI Systems
14:30-16:15
“Processor Design” Techniques for DSM Design
Technology II
Session 22: System Design Session 23: Device Session 24: VLSI Systems and
16:30-18:15
Methodologies II Modeling Applications
18:15-18:30 Closing Remarks

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 ICM 2010 Keynote Speakers

Delivering 10x Design Improvements

Walden C. Rhines (Chief Executive Officer and Chairman of the Board of Directors,
Mentor Graphics)

Walden C. Rhines is Chairman and Chief Executive Officer of Mentor Graphics, a leader in
worldwide electronic design automation with revenue of $789 million in 2008. During his tenure at Mentor
Graphics, revenue has more than doubled, growth rate since 1999 has been number one among the Big 3
EDA companies and Mentor has grown the industry's number one market share solutions in physical
verification, design concept-through-functional verification and printed circuit board design. Prior to joining
Mentor Graphics, Rhines was Executive Vice President of Texas Instruments Semiconductor Group, sharing
responsibility for TI's Components Sector, and having direct responsibility for the entire semiconductor
business with more than $5 billion of revenue and over 30,000 people. During his 21 years at TI, Rhines
managed TI's thrust into digital signal processing and supervised that business from inception with the TMS
320 family of DSP's through growth to become the cornerstone of TI's semiconductor technology. He was
also responsible for development of the first TI speech synthesis devices (used in Speak & Spell) and is co-
inventor of the GaN blue-violet light emitting diode (now important for DVD players). He was President of
TI s Data Systems Group and held numerous other semiconductor executive management positions. Rhines
is currently in his fourth term as Chairman of the Electronic Design Automation Consortium. He is also a
board member of the Semiconductor Research Corporation, Lewis and Clark College and the Portland
Classic Wines Auction. He has previously served as chairman of the Semiconductor Technical Advisory
Committee of the Department of Commerce, as an executive committee member of the board of directors of
the Corporation for Open Systems and as a board member of the Computer and Business Equipment
Manufacturers' Association (CBEMA), SEMI-Sematech/SISA, Electronic Design Automation Consortium
(EDAC), University of Michigan National Advisory Council and Sematech. Dr. Rhines holds a Bachelor of
Science degree in metallurgical engineering from the University of Michigan, a Master of Science and Ph.D.
in materials science and engineering from Stanford University, a master of business administration from
Southern Methodist University and an Honorary Doctor of Technology degree from Nottingham Trent
University.

Delivering 10X Design Improvements

Today, the exponential rise in complexity has quickened its pace as the semiconductor industry
moves from adoption of 28 nm to 20 nm and below, enabling tens of billions of transistors per chip. Dr.
Wally Rhines will discuss how in the next five years, 10X improvements in design methodologies are
needed. He will provide a roadmap for the next wave of changes needed to successfully negotiate rising
complexity, highlighting where they will most likely occur and the impact it will have on the emerging
semiconductor industry in the Middle East.

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 ICM 2010 Keynote Speakers

Engineering Education for Enhanced Innovation

Adel Sedra (Dean of Faculty of Engineering, University of Waterloo)

Adel Sedra received a BSc degree from Cairo University, Egypt, in 1964, and MASc and PhD
degrees from the University of Toronto, Canada, in 1968 and 1969 respectively, all in Electrical
Engineering. Dr. Sedra joined the faculty of the University of Toronto in 1969, rising to the rank of
Professor in 1978. During 1986-1993, he served as Chair of the Department of Electrical Engineering (now
Electrical and Computer Engineering). On July 1, 1993 he assumed the position of Vice-President, Provost,
and Chief Academic Officer of the University of Toronto and served in this capacity for nine years, leading
the University through two major long-range planning cycles, in 1994 and 1999. On July 1, 2003, Prof.
Sedra joined the University of Waterloo as Dean of the Faculty of Engineering where he led the Vision 2010
academic planning process. Professor Sedra specializes in the area of microelectronics. He has co-authored
about 150 papers and three textbooks, including Microelectronic Circuits, which is now in its fifth edition
and in ten languages, with over one million copies in print. Dr. Sedra currently serves on the Research
Council of the Canadian Institute of Advanced Research (CIFAR), and has just completed thirteen years of
service as a delegate to Oxford University Press. Awards and honours include: FIEEE (1984), FCAE (1999),
FRSC (2003), Education Medal of the IEEE (1996), Award of Excellence of Ontario Professional Engineers
(2002), D.Sc. (Hon.) Queen=s University (2003), LLD (Honoris Causa) University of Toronto (2005), D.
Sc. (Honoris Causa) McGill University (2007).

Engineering Education for Enhanced Innovation

As nations deal with the economic challenges of the early twenty-first century, the need for engineers
remains as critical or even more so than it was over the second half of the twentieth century. Clearly,
advances in technology have changed the nature of the work of engineers. Some of what engineers used to
do fifty years ago, has been greatly simplified by the advances in computer-aided design and modeling and
simulation. As a result, the engineers of the future will be called upon to contribute at a higher level on the
innovation axis. They will have to deal with more complex problems that in many cases are
multidisciplinary, with some of the disciplines being outside what has been normally the domain of
engineering, e.g. the life sciences. While the need for engineers with a broader and deeper outlook and skill
sets has been increasing, the structure of the engineering curriculum has remained virtually unchanged. As
well, in some countries, notably the USA, the production of engineers per capita has been diminishing. This
does not bode well for the hoped for enhancements in productivity, standard of living, and quality of life in
general. This presentation will examine these issues in some detail and will propose some ideas for
educating the innovative engineer.

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 ICM 2010 Keynote Speakers

Millimeter Scale Sensor Node Design using Low Voltage Operation

David Blaauw (Professor, University of Michigan - Ann Arbor)

David Blaauw received the B.S. degree in physics and computer science from Duke University,
Durham, NC, in 1986, and the Ph.D. degree in computer science from the University of Illinois, Urbana, in
1991. Until August 2001, he worked for Motorola, Inc., Austin, TX, where he was the manager of the High
Performance Design Technology group. Since August 2001, he has been on the faculty at the University of
Michigan where he is a Professor. His work has focused on VLSI design with particular emphasis on ultra-
low-power and high-performance design. Dr. Blaauw was the Technical Program Chair and General Chair
for the International Symposium on Low Power Electronic and Design. He was also the Technical Program
Co-Chair of the ACM/IEEE Design Automation Conference and a member of the ISSCC Technical Program
Committee.

Millimeter Scale Sensor Node Design using Low Voltage Operation

Miniaturized sensor nodes are increasingly in demand for applications ranging from structural
monitoring (such as bridges and buildings) to implantable medical devices, such as intra-occular pressure
monitoring. In current systems, form factor is dominated by the size of the battery and/or the energy
harvesting unit, making energy consumption the fundamental barrier to miniaturization. We first present a
number of application areas that become accessible with mm-scale sensing. We then present an ultra-low
power sensor design, including a 30pW sensor processor, low power timers, memories, power management,
solar harvesting and communication that can operate on a sub-mm3 battery for months to years. The key to
our low power approach is to operate circuits at low supply voltages (300 - 400mV). We discuss the gains
and hurdles involved in 1mm3 designs and present our design of a 1mm3 sensor.

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 Special Sessions

Crypto-Biometric Hardware

Tuesday, December 21 16:30 - 18:15 (Room: Champs-Elyses 2)

Chair: Antonio J. Acosta, IMSE-CNM/University of Seville (Spain)

Networks-on-Chip/System-on-Chip Design, Optimization, and Validation

Tuesday, December 21 14:30 - 16:15 (Room: Opera 2)

Chair: Magdy A. El-Moursy, Mentor Graphics Corporation (Egypt)

Processor Design

Wednesday, December 22 14:30 - 16:15 (Room: Champs-Elyses 1)

Chair: Serag E. D. Habib, Cairo University (Egypt)

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 ICM 2010 Tutorials

Tutorial 1: Sunday December 19, 9:30 - 12:30

Embedded Memory Design in Nanometer Technologies

Mohamed H. Abu-Rahma (Qualcomm, USA)
Baker Mohammad (Qualcomm, USA)
With technology scaling, the requirements of higher density and lower power embedded SRAMs are
increasing exponentially. Nowadays, a large percentage of microprocessors and SoC die areas are occupied
by memories, and this percentage is expected to increase substantially in the future. This increase is driven
by the high demand for low-power mobile systems, which integrate a wide range of functionality such as
digital cameras, 3-D graphics, MP3 players, and other applications. However, technology scaling which
enables packing millions of transistors on the same die also brings many new design challenges due to the
increase in leakage and variability combined with requirement for lower supply voltage operation. This
tutorial is aimed at providing a comprehensive look at SRAM-based memory design challenges in
nanometer technologies (45nm and below). Attendees will see how state-of-the-art SRAMs are designed
starting from the bitcell design aspects and macro level, to the microprocessor architecture interactions and
requirements. The tutorial will also cover topics related SRAM design robustness and statistical design
methodologies which are of utmost importance in nanometer technologies.

Mohamed H. Abu-Rahma received the B.Sc. degree (with honors) in electronics and communication
engineering from Ain Shams University, Cairo, Egypt, the M.Sc. degree in electronics and communication
engineering from Cairo University, Egypt, and the Ph.D. degree in electrical engineering from the
University of Waterloo, ON, Canada. From 2001 to 2004, he was with Mentor Graphics, where he worked
on MOSFET compact models development and extraction. He joined Qualcomm Incorporated in 2005,
where he has been engaged in the research and development of low-power embedded SRAM and CMOS
circuits. He has authored and co-authored several technical papers in refereed international conferences and
journals. He holds 1 patent, with several patents filed (pending). His research interests include low-power
digital circuits, variation-tolerant memory design, and statistical design methodologies.

Baker Mohammad is a Senior staff Engineer/Manager at Qualcomm, Austin where he is engaged in

designing high performance, and low power DSP processor used for communication and multi-media
application. Prior to joining Qualcomm he worked on a wide range of micro-processors design at Intel
Corporation from high performance, server chips > 100Watt (IA-64) , to mobile embedded processor low
power sub 1 watt (xscale). He has over 15 years experience in processor design with emphasis on memory,
circuit and physical design. He earned his PhD from University of Texas at Austin in Electrical and
Computer Engineering. His research area is in low power high yield SRAM-based memory .He received his
M.S. degree from Arizona State University, Tempe , and BS degree from the University of New Mexico,
Albuquerque, both in electrical engineering.

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 ICM 2010 Tutorials

Tutorial 2: Sunday December 19, 9:30 - 12:30

TRENDS AND CHALLENGES IN THE DESIGN OF Sigma-Delta MODULATORS:

STATE-OF-THE-ART SURVEY AND APPLICATION TO SOFTWARE DEFINED
RADIO

Jose M. de la Rosa (Institute of Microelectronics of Seville, IMSE-CNM

(CSIC/University of Seville, Spain)
The road to future Software-Defined-Radio (SDR) mobile terminals will require System-on-Chip (SoC)
transceiver solutions, implemented using mainstream nanometer CMOS processes as the base technology
and embedding digitally-assisted adaptive analog front-ends. One of the key elements of these systems is the
Analog-to-Digital Converter (ADC), since increasingly more signal processing is moving from the analog to
the digital side, taking advantage thus, of programmability, firmware upgrading and technology down-
scaling. State-of-the-art multi-standard, multi-mode ADCs have been mainly implemented using Sigma-
Delta Modulators. Based on the combination of oversampling and advanced architectural and circuital
techniques to shape the quantization noise, Sigma-Delta ADCs achieve a high degree of flexibility as well as
robustness with respect to physical-level effects. However, the design of nanometer CMOS Sigma-Delta
ADCs involves a number of practical issues and trade-offs that must be taken into account in order to
optimize their performance in terms of power consumption, silicon area and time-to-market deployment.
This has motivated that, during the last few years, significant efforts and contributions have been made to
decrease the power budget of Sigma-Delta Modulators and to increase their range of applications in the
resolution-vs-bandwidth plane whereas keeping compatibility with low-voltage supply. This tutorial
presents a comprehensive description of Sigma-Delta Modulators, their basic operation, trends and
challenges at both architectural and circuital levels – going from system-level design considerations to
physical implementation, packaging and measurements – with emphasis on nanometer CMOS realization
and their application to the next generation of SDR mobile terminals.

Jose M. de la Rosa received the M.S. degree on Electronics Physics in 1993 and the Ph.D. degree in 2000,
both from the University of Seville, Spain. Since 1994, he has been working at the Institute of
Microelectronics of Seville (IMSE-CNM, CSIC), of the Spanish Microelectronics Center. He is also with
the Department of Electronics and Electromagnetism of the University of Seville, where he is currently an
Associate Professor. His main research interests are in the field of mixed-signal integrated circuits,
especially high-performance data converters including analysis, behavioral modeling and design automation
of such circuits. In this topic, Prof. de la Rosa has participated in a number of National and European R&D
projects and has co-authored 3 books and over 130 international papers, including journal and conference
papers and book chapters.

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 ICM 2010 Tutorials

Tutorial 3: Sunday December 19, 9:30 - 12:30

Power-Aware Testing and Test Strategies for Low-Power Devices

Patrick GIRARD (University of Montpellier, France)

Nicola NICOLICI (McMaster University, Canada)

Xiaoqing WEN (Kyushu Institute of Technology, Japan)

Managing the power consumption of circuits and systems is now considered as one of the most important
challenges for the semiconductor industry. Elaborate power management strategies, such as voltage scaling,
clock gating or power gating techniques, are used today to control the power dissipation during functional
operation. The usage of these strategies has various implications on manufacturing test, and power-aware
test is therefore increasingly becoming a major consideration during design-for-test and test preparation for
low-power devices. This tutorial provides the fundamental and advanced knowledge in this area. It is
organized into three main parts. The first one gives necessary background and discusses issues arising from
excessive power dissipation during manufacturing test. The second part provides comprehensive knowledge
of structural and algorithmic solutions that can be used to alleviate such problems. The last part surveys low-
power design techniques and shows how low-power circuits and systems can be tested safely without
affecting yield and reliability. Electronic Design Automation (EDA) solutions for testing low-power devices
are also covered in the last part of the tutorial.

Patrick GIRARD received a M.S. degree in Electrical Engineering and a Ph.D. degree in Microelectronics
from the University of Montpellier, France, in 1988 and 1992 respectively. He is currently Research
Director at CNRS (French National Center for Scientific Research), and Head of the Microelectronics
Department of the LIRMM (Laboratory of Informatics, Robotics and Microelectronics of Montpellier -
France). His research interests include all aspects of digital testing and memory testing, with emphasis on
critical constraints such as timing and power. From 2006 to 2010, Patrick Girard was Vice-Chair of the
European Test Technology Technical Council (ETTTC) of the IEEE Computer Society. He has served on
numerous conference committees including ACM/IEEE Design Automation Conference (DAC),
ACM/IEEE Design Automation and Test in Europe (DATE), IEEE International Test Conference (ITC),
IEEE International Conference on Computer Design (ICCD), IEEE VLSI Test Symposium (VTS), IEEE
European Test Symposium (ETS), IEEE Asian Test Symposium (ATS), and ACM/IEEE International
Symposium on Low Power Electronic Design (ISLPED). Patrick Girard is the founder and Editor-in-Chief
of the ASP Journal of Low Power Electronics (JOLPE). He is an Associate Editor of the IEEE Transactions
on VLSI Systems and the Journal of Electronic Testing – Theory and Applications (JETTA -Springer). From
2005 to 2009, he was an Associate Editor of the IEEE Transactions on Computers. He is a co-editor of the
book “Power-Aware Testing and Test Strategies for Low Power Devices”, Springer, 2009, and a co¬author
of the book “Advanced Test Methods for SRAMs – Effective Solutions for Dynamic Fault Detection in
Nanoscale Technologies”, Springer, 2009. Patrick Girard has been involved in several European research
projects (ESPRIT III ATSEC, EUREKA MEDEA, MEDEA+ ASSOCIATE, IST MARLOW, MEDEA+
NanoTEST, CATRENE TOETS) and has managed industrial research contracts with major companies like
Infineon Technologies, Atmel, STMicroelectronics, etc. He has supervised 22 PhD dissertations and has
published 6 books or book chapters, 34 journal papers, and more than 110 conference and symposium
papers on these fields. He received two Best Paper Awards (ETS 2004 and DDECS 2005). Patrick Girard is
a Senior Member of IEEE.

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 ICM 2010 Tutorials

Nicola NICOLICI is an Associate Professor in the Department of Electrical and Computer Engineering at
McMaster University, Canada. He received the Dipl. Ing. degree in Computer Engineering from the
“Politehnica” University of Timisoara, Romania (1997), and a Ph.D. in Electronics and Computer Science
from the University of Southampton, U.K. (2000). His research interests are in the area of computer-aided
design and test. He has authored over seventy research papers and one book in this area and received the
IEEE TTTC Beausang Award for the Best Student Paper at the International Test Conference (ITC 2000)
and the Best Paper Award at the IEEE/ACM Design Automation and Test in Europe Conference (DATE
2004). He served on the technical program committees for DATE, IEEE/ACM Design Automation
Conference (DAC), IEEE European Test Symposium (ETS), IEEE Defect and Fault Tolerance Symposium
(DFT), IEEE Asian Test Symposium (ATS), IEEE International Conference on Computer Design (ICCD),
IEEE/ACM International Symposium on Networks-on-Chip (NOCS), IEEE Symposium on Design and
Diagnostics of Electronic Circuits and Systems (DDECS), IEEE Workshop on Silicon Debug and Diagnosis
(SDD), and he served as the Co-Founder, Program Co-Chair and General Chair for the Diagnostic Services
in Network-on-Chips Workshop. He was the guest co-editor for a special issue on Silicon Debug and
Diagnosis (published by IETProceedings on Computers and Digital Techniques in November 2007) and a
special issue on Low Power Test (published by for the Journal of Electronic Testing – Theory and
Applications in August 2008). He currently serves on the Editorial Boards of JETTA, IET Computers and
Digital Techniques and Integration, the VLSI Journal. He is a member of the ACM SIGDA, the IET and the
IEEE Computer and Circuits and Systems Societies.

Xiaoqing WEN received a B.E. degree from Tsinghua University, Beijing, China, in 1986, a M.E. degree
from Hiroshima University, Hiroshima, Japan, in 1990, and a Ph.D degree from Osaka University, Osaka,
Japan, in 1993. From 1993 to 1997, he was a Lecturer at Akita University, Akita, Japan. He was a Visiting
Researcher at University of Wisconsin, Madison, U.S.A., from October 1995 to March 1996. He joined
SynTest Technologies, Inc., U.S.A., in 1998, and served as its CTO until 2003. In January 2004, he joined
the Kyushu Institute of Technology, Iizuka, Japan, where he is currently a Professor. He was the Program
Committee Co-Chair of the Sixteenth IEEE Asian Test Symposium and the Eighth IEEE Workshop on RTL
and High Level Testing. In addition, he served on the program committees of IEEE Asian Test Symposium
(ATS), IEEE/ACM Asian and South Pacific Design Automation Conference (ASP¬DAC), IEEE Int’l
Symposium on Electronic Design, Test, & Applications (DELTA), IEEE Int'l Conf. on Design & Test of
Integrated Systems in Nanoscale Technology (DTIS), IEEE Int'l Test Conference (ITC), IEEE Workshop on
RTL and High Level Testing (WRTLT), and IEEE Workshop on Defect-Based Testing (DBT). His research
interests include low-power test generation, high-quality test generation, test compression, fault diagnosis,
and testable design. He is the Co-Editor of the book “VLSI Test Principles and Architectures: Design for
Testability” (Elsevier, 2006), 32 journal papers, and 60 conference and symposium papers. He is a senior
member of the IEEE, a member of the IEICE, and a member of the REAJ.

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 ICM 2010 Tutorials

Tutorial 4: Sunday December 19, 14:30 - 17:30

Power Management Systems on Chip (SoC) for Mobile Applications

Gabriel A. Rincón-Mora (Georgia Institute of Technology, USA)
Emerging feature-dense mobile devices pose several design hurdles, from demanding high performance
and extended battery life in a single miniaturized system¬-on -¬chip (SoC) platform to supplying multiple
system components that demand vastly diverse and application¬-specific requirements. Maintaining
accuracy performance and power losses in check while biasing, managing, and regulating multiple loads in a
highly integrated environment is an inherently arduous undertaking, especially when considering sensitive
analog microelectronics share their common substrate with noisy switching supplies. As a result, in light of
the increasing proliferation of highly integrated supplies in portable consumer, biomedical, and
reconnaissance products, this tutorial introduces, illustrates, and explains how to understand, develop, and
use semiconductor devices to design power integrated circuits (ICs) and systems for mobile applications. To
that end, after briefly reviewing the requirements that portable systems impose on their constituent
subsystems, this seminar illustrates by way of examples how to design basic bias circuits, bandgap-¬voltage
references, low¬-dropout (LDO) regulators, switched¬-inductor dc¬-dc converters, and lithium-¬ion
chargers. The tutorial ultimately seeks to furnish the participant with a physical and intuitive view of
power¬-management circuits that transcends rigorous mathematical and algebraic formulations, empowering
him or her with the tools necessary to understand, analyze, and design power¬-supply ICs.

Gabriel A. Rincón-Mora received the B.S., M.S., and Ph.D. degrees in electrical engineering and worked
for Texas Instruments in 1994–2003, was appointed Adjunct Professor for Georgia Tech in 1999–2001, and
became a full-time faculty member at Georgia Tech in 2001. His scholarly products include 7 books, 1 book
chapter, over 125 scientific publications, 27 patents, over 26 commercial power management chip designs,
and over 42 international speaking engagements. He received the National Hispanic in Technology Award,
the Charles E. Perry Visionary Award, a Commendation Certificate from the Lieutenant Governor of
California, IEEE CASS MWSCAS’s Service Award, and Robins Air Force Base’s Orgullo Hispano and
Hispanic Heritage awards. He was inducted into Georgia Tech’s Council of Outstanding Young Engineering
Alumni, elected IEEE CASS’ Distinguished Lecturer for 2009–2010, elevated to IET Fellow, and featured
on the cover of Hispanic Business magazine as one of “The 100 Most Influential Hispanics,” La Fuente
(Dallas publication), and three times on Nuevo Impacto (Atlanta magazine). He is an Associate Editor for
IEEE’s TCAS II, Editorial Board Member for JOLPE, was General Chair for SRC’s Energy and Power
Workshop in 2009, Circuit Design Vice Chair for IEEE’s 2008 ICCDCS, Chairman of Atlanta’s joint IEEE
SSCS-CASS, IEEE’s CASS ASP Technical Committee member, Steering Committee Member for IEEE’s
MWSCAS, Technical Program Chair for IEEE’s 2007 MWSCAS-NEWCAS, and Technical Program Co-
Chair for IEEE’s 2006 MWSCAS.

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 ICM 2010 Tutorials

Tutorial 5: Sunday December 19, 14:30 - 17:30

BioMEMS: An Enabling Technology

Hisham Mohamed (Egyptian Nanotechnology Center, Egypt)

James N. Turner (Binghamton University, USA)

Recent progress in microfabrication technology, developed and used by the integrated circuits (ICs)
industry, is being applied to biomedical applications. It became a relatively new field of research known as
BioMEMS. Microfabricated devices have been used in a broad range of biomedical and biological
applications. In the last decade, microchips have been used in many biological applications such as in
microscale sensors for surgical instruments, monitoring physiological activities, in microfluidics
applications such as drug discovery and delivery, cell sorting, DNA amplification, and electrophoresis.
BioMEMS is a multi-disciplinary research field that requires the integration of knowledge and techniques
from many disciplines such as engineering, biology, physics, and/or chemistry to develop a device with
biological utility. Microfabricated devices are used to study and generate new insights into how biological
systems work. On the other hand, researchers learn from biology to create new micro-nanoscale devices to
better understand life processes at the nanoscale. BioMEMS is a challenging field due to the vastly diverse
array of materials and chemical systems important to biological applications. Thus new fabrication processes
must be developed for use with biologically relevant material systems while keeping the ability to
effectively address dimensions at the molecular scale. The first objective of this tutorial is to present an
overview of the available technology, its strengths and current limitations, and current and potential
applications with examples from the literature and the instructors’ laboratories. The second objective is to
introduce engineers and life scientists to basic terminologies and concepts to facilitate the initiation of joint,
multidisciplinary projects.

Hisham Mohamed received the B.S. degree in electrical engineering from Ain Shams University, Cairo,
Egypt, in 1993, and the M.S. and the Ph.D. degrees in biomedical engineering from the University of
Minnesota, Minneapolis, Minnesota, USA, in 1997 and 2000, respectively. He performed his postdoctoral
training at the Wadsworth, Center New York State Department of Health, Albany New York, USA. Dr.
Mohamed is currently a Senior Research Scientist at the Egyptian Nanotechnology Center (EGNC) and a
visiting Scientist at IBM, Watson Research Laboratories in Yorktown Heights, NY. His research interests
are in photovoltaic devices, applications of carbon based materials such as carbon nanotubes and graphene
for electronic devices, in the implementation of microelectromechanical systems (MEMS) for biomedical
applications and in the areas of rare cell fractionation, on-chip filtration, and rapid prototyping for
microfluidics and biochips. He has developed BioMEMS devices for cell separation and DNA isolation and
purification.
James N. Turner received a B.S. degree in engineering science and a Ph.D. degree in biophysics from the
State University of New York, Buffalo, New York, USA, in 1968 and 1973, respectively. He did National
Institutes of Health (NIH) and National Science Foundation (NSF) Postdoctoral Fellowships at the Roswell
Park Memorial Institute, Buffalo, New York. He Directed the Three-Dimensional Light Microscopy Facility
and the Nanobiotechnology Program at the Wadsworth Center, New York State Department of Health,
Albany, and was a Platform Leader and Executive Committee Member of the Nanobiotechnology Center, an
NSF-sponsored Science and Technology Center led by Cornell University, Ithaca, NY. He was also
Professor of Biomedical Engineering at Rensselaer Polytechnic Institute, Troy, NY, and Professor of
Biomedical Sciences, School of Public Health, University at Albany, Albany, NY. He is currently a
Research Scientist in the Small-Scale Systems Integration and Packaging Center of Binghamton University,
Binghamton, NY with responsibility for developing a program in biological applications for BioMEMs
especially those utilizing flexible electronics. He has served on numerous NIH advisory panels.

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 ICM 2010 Tutorials

Tutorial 6: Sunday December 19, 14:30 - 17:30

New Trends in Testing Analogue and RF Integrated Circuits: Is BIST an

Option?
José L. Huertas (University of Seville, Spain)
This tutorial aims to present a full picture of the existing and emerging techniques for testing integrated
circuits in which coexist analogue, mixed-signal and RF parts. These techniques are grouped into categories,
which prove to be valid for baseband and RF circuitry. Their potential usefulness for implementing BIST is
also studied in depth, determining metrics to qualify every category. This tutorial is organized into 5 main
Sections. The first one gives an introduction to the increasing importance of analogue and RF circuitry by
themselves and when embedded into complex integrated systems. Examples are given to motivate the
audience and to convince it on the need for offering complete solutions combining design and test as a
whole. Mainly based on relative cost figures, design and test efforts are compared and their evolution is
foreseen. As a consequence, the adaptation of BIST (Built-In-Self-Test) to non-digital circuits is presented
and its difficulty discussed. A target example, a complex SoC provided with wireless functionalities, is
introduced as a vehicle to understand problems and propose solutions along the tutorial. Second Section is
devoted to offer the attendees with an insight on the demanding problems arisen for the coexistence of
heterogeneous circuitry (digital, analogue, RF) in the same integrated system. Testing in this context is very
complex, but solutions are emerging to comply with the existing needs. External and embedded test
techniques are presented, identifying their benefits and pointing out the main issues to look for in every case.
In essence, the two main categories of these techniques are described, namely, specification-based and
functional-based test, working out in detail their benefits and penalties. For each of these two categories,
feasibility of BIST for circuits with non-digital components is discussed, qualifying the problematic for both
test application and test interpretation phases, and giving figures on the requirements to impose on accuracy,
linearity, frequency, etc. Third Section is focused on describing the available techniques for testing baseband
circuits as a typical example of how the application context must be taken in account when deciding on the
use of BIST. This Section is mainly targeting A/D converters since they are always needed and reflect the
significant aspects of testing mixed-signal integrated circuits. The main parameters to be tested are described
as well as the difficulty of performing the related measurements, making a distinction between classical
static and dynamic test metrics. Then, test techniques in use are reviewed under the scope of classifying
them into four main categories, determining how suitable everyone is for BIST. In summary, the focus is to
describe these techniques, discussing to what extent signal requirements could be relaxed for on-chip
generation and/or measurement. Emphasis is on the introduction of the so-called alternate test methods as
they offer interesting features by themselves and in connection to BIST. A fourth Section is centered on test
techniques for RF circuitry. This is considered in connection to the overall testing of a complete transceiver
and takes into account the categories introduced in Section 3, to prove that most RF techniques fall into one
of them. A main difference is the kind of parameter to be tested, which are also reviewed in this Section.
Loop-back, embedded sensors, defect-based, model-based and envelope test techniques are described and
their pros and cons discussed. Then, their potentiality in terms of providing simplified signatures at lower
frequency is studied as it is probably the more efficient way of testing simultaneously at RF and baseband
frequencies. Examples are extensively considered, trying to give FoM for any of them. Finally, some recent
BIST cases are also introduced. A final Section aims to provide with a general discussion on what is a reality
already, what is promising and what should be needed to come up with something practical, and what is
rather difficult to improve. Emphasis is put on combining together different test methods in complex chips
where digital, analogue and RF may coexist. Some additional considerations are also given about the
extension of some of the methods described in previous Sections to cope with integrated sensors as well.

20
 ICM 2010 Tutorials

José L. Huertas received the Licenciado en Física and the Doctor en Ciencias Físicas degrees from the
University of Sevilla, Sevilla, Spain, in 1969 and 1973, respectively. From1970 to 1971, he was with the
Philips International Institute, Eindhoven, The Netherlands, as a postgraduate student. Since 1971, he has
been with the Departamento de Electrónica y Electromagnetismo, Universidad de Sevilla, Sevilla, Spain,
where he is a full professor. He is presently the Director of the Instituto de Microelectrónica de Sevilla,
Centro Nacional de Microelectrónica, CSIC, Spain. Prof. Huertas has served as the general chair of the 1993
European Solid-State Circuits Conference, the 1966 Cellular Neural Networks Workshop, the 2003 Mixed-
signal Test Workshop, the 2007 DCIS Conference and the 2009 European Test Symposium, as well as the
program co-chair of the 2002 SBCCI. He was also the Honorary Chair of the ECCTED 2007 and is
presently serving as general co-chair of 2010 ESSCIRC/ESSDERC. He has co-authored seven books and
published more than 350 papers in international journals and conferences. His present interests are in the
fields of multi-valued logic, sequential machines, analog an nonlinear circuit design, and specially in the
area of design and test of mixed-signal integrated circuits. Dr. Huertas was an Associate Editor for IEEE
Transactions on Circuits and Systems and is part of the editorial board of several journals. Besides awards
given to best paper in conferences, he received the 1995 IEEE Guillemin-Cauer award, the 1995 Kelvin
prize from IEE, the 1998 Torres-Quevedo prize (Spanish National Award on Technological Research) and
the gold medal of the Garcia-Cabrerizo foundation in 2004. Prof. Huertas have given courses, tutorials and
invited speaker papers in many international conferences, being his main topic in the last ten years the topic
of the offered tutorial, i.e., testing non-digital integrated circuits and systems. Dr. Huertas is a fellow of the
IEEE.

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 ICM 2010 Technical Program

Detailed Program
Sunday, December 19, 2010

Registration (9:30-12:30, 14:30-17:30)

(9:30-12:30) Tutorial T1 “Embedded Memory Design in Nanometer Technologies”

(Room: Champs-Elyses 1)

(9:30-12:30) Tutorial T2 “Trends and Challenges in the Design Of Σ∆ Modulators: State-of-the-Art

Survey and Application to Software Defined Radio”

(Room: Champs-Elyses 2)

(9:30-12:30) Tutorial T3 “Power-Aware Testing and Test Strategies for Low-Power Devices”

(Room: Opera 2)

(14:30-17:30) Tutorial T4 “Power Management Systems on Chip (SoC) for Mobile Applications”

(Room: Opera 2)

(14:30-17:30) Tutorial T5 “BioMEMS: An Enabling Technology”

(Room: Champs-Elyses 1)

(14:30-17:30) Tutorial T6 “New Trends in Testing Analogue and RF Integrated Circuits: Is BIST an
Option?”

(Room: Champs-Elyses 2)

Monday, December 20, 2010

(8:00-9:00) Registration

(9:00-9:45) Opening Ceremony

Keynote 1 (9:45-10:45): “Delivering 10X Design Improvements”, Walden C. Rhines - Chief Executive
Officer and Chairman of the Board of Directors, Mentor Graphics

(Room: Opera 2)
(10:45-11:15) Coffee Break

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 ICM 2010 Technical Program

Session 1: Analog-to-Digital Converters (11:15-13:00)

(Room: Champs-Elyses 1)
Session Chair: Mohamed Dessouky (Mentor Graphics - Egypt)
Session co-Chair: Ahmed Nader (Cairo University - Egypt)

1) Least Mean Square calibration method for VCO non-linearity

Hariprasath Venkatram (Oregon State University - USA); Rajesh Inti (Oregon State University - USA); Un-
Ku Moon (Oregon State University - USA)
2) ENOB Calculation for ADCs with Input-Correlated Quantization Error Using a Sine-Wave
Test
Skyler Weaver (Oregon State University - USA); Benjamin Hershberg (Oregon State University -
USA); Un-Ku Moon (Oregon State University - USA)

3) Measurement of Continuous-Time Sigma Delta Modulators: Implications of Using

Spectrum Analyzer

Ahmed Ashry (Laboratoire d'informatique de Paris 6); Ahmed El-Shennawy (SiWare –

Egypt); Mohammad A. Elbadry (University of Minnesota – USA); Ayman Elsayed (SiWare –
Egypt); Hassan Aboushady (Laboratoire d'informatique de Paris 6)

4) An Energy Recovery Approach for a Charge Redistribution Successive Approximation

ADC

Howard Tang (Nanyang Technological University - Singapore); Liter Siek (Nanyang Technological
University - Singapore)

5) Two-Phase Correlated Level Shifting Switched-Capacitor Techniques

Amr Essam (Mentor Graphics – Egypt); Mohamed Dessouky (Mentor Graphics – Egypt)

6) Analog Digital Conversion Specifications for WiMAX

Jihene Mallek (ENIS, LETI - Tunisia); Hassene Mnif (University of Sfax - Tunisia); Mourad Loulou
(University of Sfax - Tunisia)

Session 2: Leakage and Energy Efficiency in High Performance Integrated Circuits (11:15-13:00)
(Room: Opera 2)
Session Chair: Faiz ul Hassan (University of Glasgow - UK)
Session co-Chair: Sarma Vrudhula (Arizona State University - USA)

1) Optimization of On-chip Communication Link Performance under Area, Power and

Variability Constraints

Faiz ul Hassan (University of Glasgow - UK); Wim Vanderbauwhede (University of Glasgow - United
Kingdom); Fernando Rodriguez-Salazar (University of Glasgow - United Kingdom)

2) Design of a robust, high performance standard cell threshold logic family for DSM
technology
Samuel Leshner (Arizona State University - USA); Krzysztof Berezowski (TIMA Laboratory -

23
 ICM 2010 Technical Program

France); Niranjan Kulkarni; Sarma Vrudhula (Arizona State University – USA)

3) Reducing the Leakage of Memory blocks Aggressively

Dalia A.F. El-Dib (University of Victoria - Canada); Heba A. Shawkey (Elecronic Research Institute -
Egypt); Zine-Eddine Abid (University of Western Ontario - Canada)

4) Physical Design Aware Selection of Energy-Efficient and Low-Energy Nanometer Flip-

Flops

Massimo Alioto (University of Siena - Italy and currently also with BWRC, UCBerkeley – USA); Elio
Consoli (University of Catania - Italy); Gaetano Palumbo (University of Catania - Italy)

5) A Transregional Model for Near-Threshold Circuits with Application to Minimum-Energy

Operation

David Harris (Harvey Mudd College - USA); Ben Keller (Harvey Mudd College - USA)

6) VSECURE: Active & Standby Subthreshold Leakage Current Reduction Technique

Vaibhav Neema (Devi Ahilya university - India); Sanjiv Tokekar (Devi Ahilya university - India)

Session 3: Devices, Modeling and Characterization (11:15-13:00)

(Room: Champs-Elyses 2)

Session Chair: Hisham Haddara (Si-Ware Systems - Egypt)

Session co-Chair: Wael Fikry (Ain Shams University - Egypt)

1) Compact Model for Short and Ultra thin Symmetric Double Gate

Ahmed Abo-Elhadeed (Mentor Graphics – Egypt)

2) Physical Parametric Analysis of 16nm N-Channel Carbon-Nanotube Transistors for

Manufacturability
Yanan Sun (HKUST - Hong Kong); Volkan Kursun (HKUST - Hong Kong)
3) Fabrication and Characterization of a Ferroelectric-Gate FET with a ITO/PZT/SRO/Pt
Stacked Structure

Tue Phan; Trinh Bui; Miyasako Takaaki; Shimoda Tatsuya (Japan Advanced Institute of Science and
Technology - Japan); Tokumitsu Eisuke (Tokyo Institute of Technology - Japan)

4) Improved Efficiency of CMOS Light Emitters in Punch Through with Field Oxide
Manipulation

Petrus Venter; Monuko du Plessis (University of Pretoria - South Africa); Marius Goosen (INSiAVA
(Pty) Ltd - South Africa);Hannetjie Nell; Alfons W Bogalecki (University of Pretoria - South Africa)

5) Magneto-thermopower properties in Spin Field-Effect Transistors

George S. Kliros (Hellenic Air-Force Academy - Greece)

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 ICM 2010 Technical Program

6) Unified Drain Current Model for Independently Driven Double Gate MOSFETs

Binit Syamal (Jadavpur University, India - India); Pradipta Dutta (KIIT University - India);
N Mohankumar (SKP Engineering College - India);Chandan K. Sarkar (Jadavpur University - India)

(13:00-14:45) Lunch

Session 4: Improved Design Techniques for Arithmetic Circuits (14:45-16:30)

(Room: Champs-Elyses 1)
Session Chair: Adly T. Fam (University at Buffalo - USA)
Session co-Chair: Noha Younis Ahmed (Cairo University - Egypt)

1) The Interlaced Carry-Arrest Adder

Adly T. Fam (University at Buffalo - USA)

2) Design and Evaluation of High-Speed Energy-Aware Carry Skip Adders

Marco Lanuzza; Fabio Frustaci; Raffaele De Rose (University of Calabria - Italy)

3) MOS Current Mode Logic Realization of Digital Arithmetic Circuits

Ahmed H. Madian (Egyptian atomic energy authority, NCRRT - Egypt); Yassmeen El-Hariry (Germany
University in Cairo – Egypt)

4) Nanometer Flip-Flops Design in the E-D Space

Massimo Alioto (University of Siena - Italy and currently also with BWRC, UCBerkeley – USA);
Elio Consoli; Gaetano Palumbo (University of Catania - Italy)

5) On the modulo 2n+1 subtract units for weighted operands

Costas Efstathiou; Ioannis Voyiatzis (Technological Education Institute of Athens - Greece)

Session 5: Timing Circuits and Optical Links (14:45-16:30)

(Room: Champs-Elyses 2)

Session Chair: Emad Hegazy (Ain Shams University - Egypt)

Session co-Chair: Ayman Ahmed (Si-Ware Systems - Egypt)

1) Power-Aware Design for High Data Rate Free Space Optical Receivers

Behrooz Nakhkoob; Mona Hella (RPI - USA)

2) An Integrated Optical Receiver for 2.5Gbit/s Using 4-PAM Signaling

Mohamed Atef (Vienna University of Technology - Austria); Robert Swoboda (A3PICs Electronics
Development GmbH - Austria); Horst Zimmermann (Vienna University of Technology - Austria)

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 ICM 2010 Technical Program

3) A 0.8-6.3 GHz Spread Spectrum Clock Generator for SerDes Transmitter Clocking

Rania Hassan Mekky (MEMS Vision - Egypt); Mohamed Dessouky (Mentor Graphics – Egypt)

4) A Technique for Robust Division Ratio Switching in Multi Modulus Dividers with Modulus
Extension

Mohamed Hussein Eissa; Mohammed El-Shennawy (Silicon Vision LLC - Egypt)

5) Modeling of Spread-Spectrum Clock Generation System using Simulink

Walaa Ayoub; Mohamed Dessouky (Mentor Graphics – Egypt); Khaled Sharaf (Ain Shams University -
Egypt)

6) ESD protection circuits with low triggering voltage, low leakage current and fast turn-
on

Yong-Seo Koo (DanKook University - Korea); Kwang-Yeob Lee; Hyun-Duck Lee; Tae-Ryoung
Park;Jae- Chang Kwak (Seokyeong University - Korea); Yil-Suk Yang (ETRI - Korea)

Session 6: System Design Methodologies I (14:45-16:30)

(Room: Opera 2)

Session Chair: Rafik Guindi (Nile University - Egypt)

Session co-Chair: Ahmed Elhossini (University of Guelph - Canada)

1) A Hardware/Software Co-design Architecture for Packet Classification

Omar F. Ahmed; Karanvir Chattha; Shawki Areibi (University of Guelph - Canada)
2) Accelerated Exploration of Cost-Performance Tradeoffs for Multi Objective VLSI designs

Reza Sedaghat; Anirban Sengupta (Ryerson University - Canada)

3) A Generic MP-SoC Design Methodology for the Fast Prototyping of Embedded Image
Processing

Alexis Landrault; Loïc Sieler; Jean-Pierre Derutin (University Blaise Pascal - France); Lionel DAMEZ
(LASMEA - France)

4) Behavioral Modeling of the Static Transfer Function of ADCs Using INL Measurement

Rafik Guindi (Nile University – Egypt); Nehal Saada (Mentor Graphics – Egypt)
5) Raster-Scanned Wave-Digital Filter Architectures for Multi-Beam 2D IIR Broadband
Beamforming
Arjuna Madanayake (University of Akron - USA); Leonard T. Bruton (University of Calgary -
Canada); Chamith Wijenayake (University of Moratuwa - Sri Lanka);Nilanka T. Rajapaksha
(University of Akron - USA)
6) Generalized Power Efficient Technique for Polyphase Comb Filter in Multi-Rate Digital
Receivers

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 ICM 2010 Technical Program

Noha Younis Ahmed (Cairo University - Egypt)

(16:30-16:45) Coffee Break

(16:45 – 18:15) Panel: Challenges of Nano Electronics Industry Ecosystem in the Arab Region

(Room: Opera 2)

Tuesday, December 21, 2010

Keynote 2 (9:30-10:30) “Engineering Education for Enhanced Innovation”, Adel Sedra - Dean of
Faculty of Engineering, University of Waterloo

(Room: Opera 2)

(10:30-11:00) Coffee Break

Session 7: Sensing Systems and MEMS (11:00-12:45)

(Room: Champs-Elyses 1)
Session Chair: Hani Ragai (French University in Egypt - Egypt)
Session co-Chair: Bassam El-Saadany (Si-Ware Systems - Egypt)

1) The Phase Noise of an Oscillator Employing a Dual MEMS Resonator Temperature

Compensation Scheme

Seyed Ali Gorji Zadeh; Mourad N. El-Gamal (McGill University - Canada); Frederic Nabki (Université
du Québec à Montréal - Canada)

2) A Temperature Compensated Architecture for Integrated, Low Power, Frequency

Domain Sensors

Karim Allidina; Tanmoy Saha; Mourad N. El-Gamal (McGill University - Canada)

3) Integrated Optical Light Directing Structures in CMOS to Improve Light Extraction

Efficiency

Alfons W Bogalecki; Monuko du Plessis; Petrus Venter (University of Pretoria - South Africa);Marius
Goosen (INSiAVA (Pty) Ltd - South Africa); Hannetjie Nell (University of Pretoria - South Africa)

4) Design of a Low-Cost MEMS Monolithically-Integrated Relative Humidity Sensor

Paul-Vahe Cicek; Tanmoy Saha (McGill University - Canada); Bichoy Waguih (Ain Shams University -
Egypt);Frederic Nabki (Université du Québec à Montréal - Canada); Mourad N. El-Gamal (McGill
University - Canada)

5) Blood Glucose Optical Bio-Implant: Preliminary Design Guidelines

Abdelaziz Trabelsi; Mounir Boukadoum; Christian Jesus B Fayomi (Université du Québec à Montréal -
Canada); El Mostapha Aboulhamid (University of Montreal – Canada)

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 ICM 2010 Technical Program

6) The Implementation of 2-Bit Decoders Using Single Electron Linear Threshold Gates
(LTGs)
Sameh Ebrahim Rehan (Mansoura University - Egypt)

Session 8: Multicore and Embedded Systems (11:00-12:45)

(Room: Champs-Elyses 2)

Session Chair: Amr Wassal (Nile University – Egypt)

Session co-Chair: TBD

1) Investigating Cache Parameters and Locking in Predictable and Low Power Embedded
Systems

Abu S Asaduzzaman (Wichita State University - USA); Fadi Sibai (UAE University - UAE)

2) Evaluation of the Impact of Miss Table and Victim Caches in Parallel Embedded
Systems

Abu S Asaduzzaman (Wichita State University - USA); Imad Mahgoub (Florida Atlantic University -
USA); Fadi Sibai (UAE University - UAE)

3) Adaptive Packet Sizing for OTAP of PSoC Based Interface Board in WSN

Ihab Adly; Hani Ragai; Adel Elhennawy (Ain Shams University - Egypt); Khaled Ali Shehata (Arab
Academy for Science and Technology - Egypt)

4) Thermal, Power, and Performance Shaping of Multicore Floorplans

Fadi Sibai (UAE University - UAE)

5) Parallel Programming and speed up evaluation of a NoC 2Ary-4Fly
Abir M'zah; Omar Hammami (Ecole Nationale Supérieure de Techniques Avancées - France)

Session 9: RF Design, Analysis and Techniques (11:00-12:45)

(Room: Opera 2)
Session Chair: Maged Ghoneima (Nile University - Egypt)
Session co-Chair: Mourad Loulou (Ecole Nationale d'Ingenieurs de Sfax - Tunisia)

1) LC-Oscillator featuring independent Gate biasing implemented in 32nm CMOS

technology

Davide Ponton (Infineon Technologies AG - Austria)

2) A Fast Automatic Tuning Algorithm for Voltage Controlled Oscillators

Mohammed El-Shennawy (Silicon Vision LLC - Egypt); Emad Hegazi (Ain Shams University - Egypt)

3) CMOS ring oscillators with enhanced frequency operation

28
 ICM 2010 Technical Program

Aimad El Mourabit (National School of Applied Sciences of Tangier LabTic - Morocco); Guo-Neng Lu
(University of Lyon - France); Ming Zhang (IEF, University Paris - France); Patrick Pittet
(University of Lyon - France); Birjali Youness; Fouad Lahjoumri (LabTic, National School of
applied sciences of Tangier - Morocco)

4) A Continuous Analysis of the Oscillation Amplitude in MOS LC-VCOs

Bassem Fahs (Université de Caen - France); Patrice Gamand (NXP Semiconductors -

France); Berland Corinne ( Lamips NXP-CRISMAT Caen France - France)

5) A 2nd Derivative Gaussian UWB Pulse Transmitter Design using a Cross Inductor

Luiz Moreira (Catholic University of Santos - Brazil); Wilhelmus Van Noije (University of São Paulo -
Brazil)

6) A novel High-Speed Multi-phase Oscillator Using Self-Timed Rings

Oussama Elissati (ST-Ericsson - France); Eslam Yahya (Banha University - Egypt); Sébastien Rieubon
(ST-Ericsson - France); Laurent Fesquet (TIMA - France)

(12:45-14:30) Lunch

Session 10: Voltage Regulators and Analog Techniques (14:30-16:15)

(Room: Champs-Elyses 1)

Session Chair: AbdelHalim Zekry (Ain Shams University - Egypt)

Session co-Chair: Ahmed Emira (Cairo University - Egypt)

1) A CMOS Low Drop Out Voltage Regulator

Paulo Crepaldi; Tales C Pimenta; Robson Moreno (Universidade Federal de Itajuba - Brazil)

2) Practical Design Considerations on Adaptive Controllers for PWM DC/DC Converters

Davide Della Giustina; Valentino Liberali (Università degli Studi di Milano - Italy)

3) An Ultra-Low Power Voltage Regulator for Wireless Sensor Nodes

Stefan Gruber; Hannes Reinisch; Hartwig Unterassinger (Graz University of Technology -

Austria); Martin Wiessflecker; Günter Hofer (Infineon Technologies Austria AG -
Austria); Wolfgang Pribyl (Graz University of Technology - Austria); Gerald Holweg (Senior
Manager - Austria)

4) New ± 0.75 V Low Voltage Low Power CMOS Current Conveyor

Hesham Hamed; El-Sayed Hasaneen; Ahmed Abolila (El-Minia University - Egypt)

5) Digitally Controlled Variable Gain-Amplifier Based on Current Conveyor with Opamp

and Inverters Only

Fathi Farag; Yaser Khalaf (Zagazig University - Egypt)

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 ICM 2010 Technical Program

6) Novel High Efficiency Low Ripple Charge Pump Using Variable Frequency Modulation

Chen Mingyang; Xiaobo Wu; Menglian Zhao (Zhejiang University - China)

Session 11: Advances in Graphene and Carbon Nanotube Device and Wire Technologies (14:30-16:15)

(Room: Champs-Elyses 2)
Session Chair: George Kliros (Hellenic Air-Force Academy - Greece)
Session co-Chair: TBD

1) Large Area CVD Monolayer Graphene for Nanoelectronics: Device Performance and
Analysis

Osama Nayfeh; Madan Dubey (United States Army Research Laboratory - USA)

2) Modeling of Carrier Density and Quantum Capacitance in Graphene Nanoribbon FETs

George S. Kliros (Hellenic Air-Force Academy - Greece)

3) Scaling Issues for p-i-n Carbon Nanotube FETs: A Computational Study

Salah El-DIn Gamal; Mahmoud Ossaimee (Ain Shams University - Egypt)

4) Modeling of Electronic Transport in Metallic Carbon Nanotube Interconnects

Ashok K Goel; Vidur Parkash (Michigan Tech University - USA)

5) Semiconductor Nanostructures in Crystalline Rare Earth Oxide for Nanoelectronic

Device Applications

Apurba Laha (Senior Research Scientist - Germany)

6) A Novel Partially Insulated Schottky Source/Drain MOSFET: Short Channel and self
heating effects

Ganesh Patil; Shafi Qureshi (Indian Institute of Technology Kanpur - India)

Session 12: Special Session “Networks-on-Chip/System-on-Chip Design, Optimization and Validation”

(14:30-16:15)

(Room: Opera 2)
Session Chair: Magdy A. El-Moursy (Mentor Graphics Corporation - Egypt)

1) Asynchronous Switching for Low-Power Octagon Network-On-Chip

Magdy A. El-Moursy (Mentor Graphics - Egypt); Heba A. Shawkey (Elecronic Research Institute -
Egypt)

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 ICM 2010 Technical Program

2) A Design Space Exploration Methodology for Allocating TPG to Multi-core System

Architectures

Hassan Youness (Minia University - Egypt); Mohamed Hassan; Ashraf M Salem (Mentor Graphics –
Egypt)

3) Ecosystems for the Development of Multi-Core and Many-Core SoC Models

Amr Wassal (Cairo University – Egypt); Moataz A Abdelfattah; Yehea Ismail (Nile Uuniversity – Egypt)

4) 3D/TSV Enabling Technologies for SOC/NOC: Modeling and Design Challenges

Khaled Mohamed (Mentor Graphics - Egypt); Alaa El Rouby (Cairo University – Egypt); Hani Ragai
(Ain Shams Univeristy – Egypt); Yehea Ismail (Nile University – Egypt)

5) SSMC: An On-Chip Source-Synchronous Multi-Cycle Interconnect Scheme

Maged Ghoneima (NVIDIA Corporation - USA); Yehea Ismail (Nile Univeristy - Egypt); Vivek
De; Muhammad Khellah (CRL, Intel Corporation - USA)

(16:15-16:30) Coffee Break

Session 13: Addressing Fault-Tolerance, Reliability and Robustness in Integrated Circuits (16:30-
18:15)

(Room: Opera 2)

Session Chair: Saeed Kharouf (American University of Beirut - Lebanon)

Session co-Chair: Ahmed H. Madian (NCRRT - Egypt)

1) Built-In-Current-Sensor for Testing Short and Open Faults in CMOS Digital Circuits

Rania Ahmed (Egypt); Ahmed H. Madian (Egyptian atomic energy authority - Egypt); Ahmed G.
Radwan; Ahmed M Soliman (Cairo University – Egypt)

2) An Analysis of SEU Robustness of C-Element Structures Implemented in Bulk CMOS

and SOI Technologies

Ziyad AL Tarawneh; Gordon Russell; Alex Yakovlev (Newcastle University - United Kingdom)

3) On the mathematical modeling of Memristors

Ahmed G. Radwan (Cairo University - Egypt); Mohammed Affan Zidan; Khaled N Salama (KAUST -
Saudi Arabia)

4) Time domain oscillating poles: Stability redefined in Memristor based Wien-oscillators

Abdul Talukdar (KAUST - Saudi Arabia); Ahmed G. Radwan (Cairo University – Egypt); Khaled N
Salama (KAUST - Saudi Arabia)

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 ICM 2010 Technical Program

Session 14: Modeling and Design with Emerging Devices (16:30-18:15)

(Room: Champs-Elyses 1)
Session Chair: Massimo Alioto (University of Siena - Italy and currently also with BWRC, UCBerkeley – USA)
Session co-Chair: TBD

1) Memristor based STDP Learning Network for position Detection

Pinaki Mazumder (University of Michigan - USA)

2) Low-Standby Current 4T FinFET Buffers: Analysis and Evaluation below 45 nm

Massimo Alioto (University of Siena - Italy and currently also with BWRC, UCBerkeley – USA); David
Esseni; Davide Baccarin (University of Udine - Italy)

3) Electron Mobility in Gate All Around Cylindrical Silicon Nanowires: A Monte Carlo Study

Salah El-DIn Gamal; Mahmoud Ossaimee (Ain Shams University - Egypt)

4) Partial-Coupled Mode Space for Quantum Transport Simulation in Nanoscale Double-

Gate MOSFETs

Mohammed El-Banna; Yasser Sabry (Ain Shams University - Egypt);Wael Fikry (Mentor Graphics -
Egypt); Omar Omar (Ain Shams University - Egypt)
5) A Single Electron ANN Majority Logic Gate (MLG)
Sameh Ebrahim Rehan (Mansoura University - Egypt)

Session 15: Special Session “Crypto-Biometric Hardware” (16:30-18:15)

(Room: Champs-Elyses 2)
Session Chair: Antonio J. Acosta (IMSE-CNM/University of Seville – Spain)

1) An Improved Differential Pulldown Network Logic Configuration for DPA Resistant

Circuits

Javier Castro; Pilar Parra; Antonio Acosta (University of Seville - Spain)

2) High Radix Implementation of Montgomery Multipliers with CSA

Gashaw Teshome; Carlos Jesús Jiménez; Manuel Valencia (University of Seville - Spain)
3) Hardware authentication based on PUFs and SHA-3 2nd round candidates
Susana Eiroa (National Center of Microelectronics - Spain); Iluminada Baturone (University of Seville
- Spain)

4) Microelectronics Implementation of Directional Image-based Fuzzy Templates for

Fingerprints

Iluminada Baturone; Rosario Arjona; Santiago Sánchez-Solano (University of Seville - Spain)

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 ICM 2010 Technical Program

Wednesday, December 22, 2010

Keynote 3 (9:30-10:30) “Millimeter Scale Sensor Node Design using Low Voltage Operation”, David
Blaauw - Professor, University of Michigan - Ann Arbor

(Room: Opera 1)

(10:30-11:00) Coffee Break

Session 16: Analog Techniques I (11:00-12:45)

(Room: Champs-Elyses 1)
Session Chair: Manuel Delgado Restituto (Instituto de Microelectrónica de Sevilla - Spain)
Session co-Chair: Amr Hafez (Cairo University - Egypt)

1) A Comparative Study of Low-Noise Amplifiers for Neural Applications

Jesus Ruiz-Amaya (University of Seville - Spain)

2) Design Considerations for Analog Blocks in Mixed-Signal CMOS ICs

Valentino Liberali; Gabriella Trucco (Università degli Studi di Milano - Italy)

3) Impact of Technology Shrink on Audio CODEC Performance

Amir Owzar (Stericsson - Switzerland)

4) Bult-In Current Sensor for Testing Current Feedback Operational Amplifier

Rania Ahmed (Egypt); Ahmed H. Madian (Egyptian atomic energy authority, NCRRT - Egypt); Ahmed
G. Radwan; Ahmed M Soliman (Cairo University - Egypt)

5) A Low-Voltage CMOS Bandgap Reference Circuit with Improved Power Supply Rejection

Ahmed Mohieldin (Cairo University - Egypt); Haidi Elbahr (Sysdsoft Inc. - Egypt); Emad Hegazi (Ain
Shams University - Egypt); Marwa Mostafa (Sysdsoft Inc. - Egypt)

Session 17: CAD Tools (11:00-12:45)

(Room: Champs-Elyses 2)

Session Chair: Mounir Boukadoum (Universite du Quebec a Montreal)

Session co-Chair: Shawki Areibi (University of Guelph)

1) SplitPro: A Tool to Overcome SystemC Scheduling Inefficiencies

Rafik Guindi (Nile University - Egypt); Youssef Naguib (Cairo University - Egypt)

2) Spicedim - A CAD Tool for Supporting Circuit Sizing of Analog CMOS Circuits

Daniel Batas; Horst Fiedler; Stefan Knaak (Technische Universitaet Dortmund - Germany)

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 ICM 2010 Technical Program

3) Rapid Exploration of Power-Delay Tradeoffs using Hybrid Priority Factor and Fuzzy
Search

Reza Sedaghat; Anirban Sengupta (Ryerson University - Canada)

4) Parallel TLM Simulation of MPSoC on SMP Workstations: Influence of Communication

Locality

Isaac Pessoa (Laboritoire d'informatique de Paris 6 - France)

5) A Hashing Mechanism for Rule-Based Decomposition in Double Patterning

Photolithography

Amr Wassal; Hoda Shagar; Yasmine Badr; Hoda Darwish; Yasmine Arafa (Cairo University –
Egypt)

Session 18: Advanced Memory Design (11:00-12:45)

(Room: Etoile)

Session Chair: Ahmed H. Madian (NCRRT – Egypt)

Session co-Chair: Khawar Sarfraz (LUMS – Pakistan)

1) Comparison of two SRAM matrix leakage reduction techniques in 45nm technology

Khawar Sarfraz (Lahore University of Management Sciences - Pakistan)

2) Process Variations in Sub-Threshold SRAM Cells in 65nm CMOS

Farshad Moradi; Dag Wisland; Yngvar Berg; Snorre Aunet; Tuan Vu Cao (University of Oslo -
Norway)

3) A Multi-Megarad, Radiation Hardened by Design 512 kbit SRAM in CMOS Technology

Cristiano Calligaro (RedCat Devices srl - Italy); Valentino Liberali; Alberto Stabile (Università degli
Studi di Milano - Italy); Marta Bagatin;Simone Gerardin; Alessandro Paccagnella (Università degli
Studi di Padova - Italy)

4) A 1.5 GHz Robust SRAM Array optimized for cell area

Saeed Kharouf; Lama Chatila; Mohammad M. Mansour; Ali Chehab (American University of Beirut -
Lebanon)

5) Effective screening for NBTI effect on SRAM-based Memory

Baker Mohammad; Percy Dadabhoy (Qualcomm Incorporated - USA)

6) On the Design of Low-Power Cache Memories for Homogeneous Multi-Core Processors

Abu S Asaduzzaman (Wichita State University - USA); Manira Rani (Florida Atlantic University -
USA); Fadi Sibai (UAE University - UAE)

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 ICM 2010 Technical Program

(12:45-14:30) Lunch

Session 19: Special Session “Processor Design” (14:30-16:15)

(Room: Champs-Elyses 1)
Session Chair: Serag E. D. Habib (Cairo University - Egypt)

1) CUSPARC IP Processor: Design, Characterization and Applications

Ezz El-Din O. Hussein; Shoukry I. Shams; Mohammed I Ali; Amr Suleiman; Khaled ElWazeer; Ehab A.
Sobhy; Ahmad Atef Ibrahim; Ahmed Gamal Ibrahim; Muhammad S Khairy; Mohamed F. Fouda; Al-
Hussein El-Shafie; Ahmed H. Hareedy; ElSayed A. Ahmed; Ahmed Ragab Zakaria; Khalid El-
Galaind; Amr El Sherief; Serag E. -D Habib (Cairo University – Egypt)

2) ASIC Implementation of Cairo University SPARC "CUSPARC" Embedded Processor

Amr Suleiman; Alhassan F. Khedr; Serag E. -D Habib (Cairo University – Egypt)

3) Decimal Floating Point for future processors

Hossam A. H. Fahmy; Tarek Eldeeb; Mahmoud Hassan; Yasmin Farouk; Ramy Eissa (Cairo
University , SilMinds, LLC - Egypt)

4) Scalability Investigation of Mat-Core Processor

Abdulmajid Al-Junaid (Assiut university - Egypt); Mostafa Soliman (South Valley University -
Egypt)

Session 20: Innovative Design and Analysis Techniques for DSM Technology II (14:30-16:15)

(Room: Champs-Elyses 2)
Session Chair: Otmane Ait Mohamed (Concordia University - Canada)
Session co-Chair: Mohammed Alshaikh (Newcastle University - UK)

1) Implementation of a Colorimetric Algorithm for Portable Blood Gas Analysis

Jaideep Chandran (Victoria University - Australia); Alex Stojcevski (Swinburne University of

Technology - Australia); Aladin Zayegh; Thinh Nguyen (Victoria University - Australia)

2) A Synchronizer Design Based on Wagging

Mohammed Alshaikh; David Kinniment; Alex Yakovlev (Newcastle University - United Kingdom)

3) An Automated SAT Encoding-Verification Approach for Efficient Model Checking

Khaza Anuarul Hoque; Otmane Mohamed (Concordia University - Canada); Sa'ed Abed (The
Hashemite University - Jordan); Mounir Boukadoum (Université du Québec à Montréal - Canada)

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 ICM 2010 Technical Program

4) Hardware Implementation of DES Using Pipelining Concept with Time-Variable Key

Karim Moussa Ali; Hesham Hamed (ElMinia University - Egypt)

5) A Novel N-bit SAR Implementation for All-Digital DLL Circuits

Al-Hussein El-Shafie; Serag E. -D Habib (Cairo University – Egypt)

6) Towards Design of a Bridge to Enable High Speed Image Sensors for Random Access

Tareq Hasan Khan; Khan A Wahid (University of Saskatchewan - Canada)

Session 21: VLSI Systems Design (14:30-16:15)

(Room: Etoile)

Session Chair: Amr Wassal (Nile University – Egypt)

Session co-Chair: TBD

1) Systolic-Array based regularized QR-Decomposition for IEEE 802.11n Compliant Soft-

MMSE Detection

Christian Senning; Andreas Burg (ETH Zurich - Switzerland)

2) Implementation of optimized Triple-Mode Digital Down Converter for WCDMA,

CDMA2000 and GSM of SDR

Emad Samuel Malki (Russian University - Egypt); Khaled Ali Shehata (Arab Academy for Science and
Technology - Egypt)

3) A Novel SAR Fast-Locking DPLL: Behavioral Modeling and Simulations Using VHDL-AMS

Mahmoud Wagdy; Anurag Nannaka (California State university,Long Beach - USA)

4) A New Datapath-oriented Tree-based FPGA Architecture

Umer Farooq (Laboritoire d'informatique de Paris 6 - France)

5) Experimental Implementation of 2ODPA attacks on AES design with flash-based FPGA

Technology

Najeh Masmoudi Kamoun (High school of telecom in Tunis SUP'COM - Tunisia); Lilian Bossuet
(University of Bordeaux - France); Adel Ghazel (SUPCOM - Tunisia)

(16:15-16:30) Coffee Break

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 ICM 2010 Technical Program

Session 22: System Design Methodologies II (16:30-18:15)

(Room: Champs-Elyses 1)
Session Chair: Ahmed Elhossini (University of Guelph - Canada)
Session co-Chair: Reza Sedaghat (Ryerson University - Canada)

1) An Efficient Scheduling Methodology for Heterogeneous Multi-core Processor Syste

Ahmed Elhossini; John Huissman; Basil Debowski;Shawki Areibi; Robert D. Dony (University of Guelph -
Canada)
2) Towards an automated framework for task scheduling

Martin Dubois; Mounir Boukadoum (Université du Québec à Montréal - Canada)

3) SystemC-AMS Modeling of a PCR-CE Lab-on-Chip for Multithreaded DNA analysis

Amr Habib (Laboratoire d'informatique de Paris 6 - France); Francois Pecheux (University of Pierre
and Marie Curie - France); Marie-Minerve Louerat (Laboratoire d'informatique de Paris 6 -
France)

4) Multi-objective Network-on-Chip Synthesis with Transaction Level Simulation

Xinyu Li; Omar Hammami (ENSTA ParisTech - France)

5) Voltage-Mode Balanced-Outputs Quadrature Oscillator Using FB-VDBAs
Josef Bajer; Dalibor Biolek; Viera Biolkova; Zdenek Kolka (Brno University of Technology - Czech Republic)

Session 23: Device Modeling (16:30-18:15)

(Room: Champs-Elyses 2)
Session Chair: Salah Gamal (Ain Shams University - Egypt)
Session co-Chair: Pravin N Kondekar (Indian Institute of Information Technology - India)

1) Analytical Modeling and Simulation of High Voltage Super-junction Drift layer for Power
MOSFET

Pravin Kondekar (PDPM IIIT DM Jabalpur - India)

2) A Modified PSPICE Model for the Power PIN Diode

Ahmed Shaker; Abdelhaliem Zekry (Ain Shams University - Egypt)

3) Parametric Reduction of Jacobian Matrix for Fault Analysis

Zdenek Kolka; Dalibor Biolek; Viera Biolkova; Zdenek Kincl (Brno University of Technology -
Czech Republic)

4) An Accurate Large-signal SPICE Model For Resonant Tunneling Diode

Sherif Fathi Nafea (Suez Canal University - Egypt); Ahmed Dessouki (Egypt)

5) Modeling of GaN MESFETs at High Temperature

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 ICM 2010 Technical Program

B. N. Shashikala (Visvesvaraya Technological University - India); B. S. Nagabhushana ( Info Tech Pvt.

Ltd. - India)

Session 24: VLSI Systems and Applications (16:30-18:15)

(Room: Etoile)

Session Chair: TBD

Session co-Chair: TBD

1) Scanned-Array Audio Beamforming using 2nd- and 3rd-Order 2D IIR Beam Filters on
FPGA

Arjuna Madanayake (University of Akron - USA); Leonard T. Bruton (University of Calgary -

Canada); Ranga Rodrigo; Nuwan Ganganath; Prabhath Ilangakoon; Gayan Attanayake; Thilina
Yapa Bandara (University of Moratuwa - Sri Lanka)

2) A Reconfigurable Architecture for Real Time Vision Systems on FPGA

Ahmed Elhossini; Medhat Moussa (University of Guelph - Canada)

3) Pipelined Architecture for Discrete Wavelet Transform Implementation on FPGA

Mohammed Bahoura; Ezzadi Hassan (University of Quebec at Rimouski - Canada)

4) Hardware Realization of DC Embedding Video Watermarking Technique based on FPGA

Ahmed H. Madian (Egyptian atomic energy authority, NCRRT - Egypt); Wessam Elaraby; Mahmoud
Ashour; Abdel M. Wahdan (Radiation Engineering Dept. - Egypt)

5) OpenCV compatible real time processor for background foreground identification

Mariangela Genovese; Ettore Napoli; Nicola Petra (University of Naples "Federico II" - Italy)

6) Optimization of Recursive Sorting Algorithms for Implementation in Hardware

Dmitri Mihhailov (Tallinn University of Technology - Estonia); Valery Sklyarov; Iouliia Skliarova
(University of Aveiro - Portugal); Alexander Sudnitson (Tallinn University of Technology - Estonia)

(18:15-18:30) Closing Remarks

38