ESP32

Technical Reference Manual

Version 4.1
Espressif Systems
Copyright © 2019

www.espressif.com
About This Manual
The ESP32 Technical Reference Manual is addressed to application developers. The manual provides detailed
and complete information on how to use the ESP32 memory and peripherals.

For pin definition, electrical characteristics and package information, please see ESP32 Datasheet.

Document Updates
Please always refer to the latest version on https://www.espressif.com/en/support/download/documents.

Revision History
For any changes to this document over time, please refer to the last page.

Related Resources
Additional documentation and other resources about ESP32 can be accessed here: ESP32 Resources.

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Disclaimer and Copyright Notice

Information in this document, including URL references, is subject to change without notice. THIS DOCUMENT IS
PROVIDED AS IS WITH NO WARRANTIES WHATSOEVER, INCLUDING ANY WARRANTY OF MERCHANTABIL-
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Copyright © 2019 Espressif Inc. All rights reserved.
Contents

1 System and Memory 22

1.1 Introduction 22
1.2 Features 22
1.3 Functional Description 24
1.3.1 Address Mapping 24
1.3.2 Embedded Memory 24
1.3.2.1 Internal ROM 0 25
1.3.2.2 Internal ROM 1 25
1.3.2.3 Internal SRAM 0 26
1.3.2.4 Internal SRAM 1 26
1.3.2.5 Internal SRAM 2 27
1.3.2.6 DMA 27
1.3.2.7 RTC FAST Memory 27
1.3.2.8 RTC SLOW Memory 27
1.3.3 External Memory 27
1.3.4 Cache 28
1.3.5 Peripherals 29
1.3.5.1 Asymmetric PID Controller Peripheral 30
1.3.5.2 Non-Contiguous Peripheral Memory Ranges 30
1.3.5.3 Memory Speed 31

2 Interrupt Matrix 32
2.1 Overview 32
2.2 Features 32
2.3 Functional Description 32
2.3.1 Peripheral Interrupt Source 32
2.3.2 CPU Interrupt 35
2.3.3 Allocate Peripheral Interrupt Sources to Peripheral Interrupt on CPU 35
2.3.4 CPU NMI Interrupt Mask 36
2.3.5 Query Current Interrupt Status of Peripheral Interrupt Source 36

3 Reset and Clock 37

3.1 System Reset 37
3.1.1 Introduction 37
3.1.2 Reset Source 37
3.2 System Clock 38
3.2.1 Introduction 38
3.2.2 Clock Source 39
3.2.3 CPU Clock 39
3.2.4 Peripheral Clock 40
3.2.4.1 APB_CLK Source 40
3.2.4.2 REF_TICK Source 41
3.2.4.3 LEDC_SCLK Source 41
 3.2.4.4 APLL_SCLK Source 41
3.2.4.5 PLL_D2_CLK Source 41
3.2.4.6 Clock Source Considerations 42
3.2.5 Wi-Fi BT Clock 42
3.2.6 RTC Clock 42
3.2.7 Audio PLL 42

4 IO_MUX and GPIO Matrix 44

4.1 Overview 44
4.2 Peripheral Input via GPIO Matrix 45
4.2.1 Summary 45
4.2.2 Functional Description 45
4.2.3 Simple GPIO Input 46
4.3 Peripheral Output via GPIO Matrix 46
4.3.1 Summary 46
4.3.2 Functional Description 47
4.3.3 Simple GPIO Output 48
4.4 Direct I/O via IO_MUX 48
4.4.1 Summary 48
4.4.2 Functional Description 48
4.5 RTC IO_MUX for Low Power and Analog I/O 49
4.5.1 Summary 49
4.5.2 Functional Description 49
4.6 Light-sleep Mode Pin Functions 49
4.7 Pad Hold Feature 49
4.8 I/O Pad Power Supplies 50
4.8.1 VDD_SDIO Power Domain 51
4.9 Peripheral Signal List 51
4.10 IO_MUX Pad List 56
4.11 RTC_MUX Pin List 57
4.12 Register Summary 58
4.13 Registers 62

5 DPort Register 85
5.1 Introduction 85
5.2 Features 85
5.3 Functional Description 85
5.3.1 System and Memory Register 85
5.3.2 Reset and Clock Registers 85
5.3.3 Interrupt Matrix Register 86
5.3.4 DMA Registers 90
5.3.5 PID/MPU/MMU Registers 90
5.3.6 APP_CPU Controller Registers 93
5.3.7 Peripheral Clock Gating and Reset 93
5.4 Register Summary 96
5.5 Registers 102
6 DMA Controller 116
6.1 Overview 116
6.2 Features 116
6.3 Functional Description 116
6.3.1 DMA Engine Architecture 116
6.3.2 Linked List 117
6.4 UART DMA (UDMA) 118
6.5 SPI DMA Interface 119
6.6 I2S DMA Interface 120

7 SPI 121
7.1 Overview 121
7.2 SPI Features 122
7.3 GP-SPI 122
7.3.1 GP-SPI Four-line Full-duplex Communication 123
7.3.2 GP-SPI Four-line Half-duplex Communication 123
7.3.3 GP-SPI Three-line Half-duplex Communication 124
7.3.4 GP-SPI Data Buffer 124
7.4 GP-SPI Clock Control 125
7.4.1 GP-SPI Clock Polarity (CPOL) and Clock Phase (CPHA) 125
7.4.2 GP-SPI Timing 126
7.5 Parallel QSPI 127
7.5.1 Communication Format of Parallel QSPI 128
7.6 GP-SPI Interrupt Hardware 128
7.6.1 SPI Interrupts 128
7.6.2 DMA Interrupts 129
7.7 Register Summary 129
7.8 Registers 132

8 SDIO Slave 155

8.1 Overview 155
8.2 Features 155
8.3 Functional Description 155
8.3.1 SDIO Slave Block Diagram 155
8.3.2 Sending and Receiving Data on SDIO Bus 156
8.3.3 Register Access 156
8.3.4 DMA 157
8.3.5 Packet-Sending/-Receiving Procedure 158
8.3.5.1 Sending Packets to SDIO Host 158
8.3.5.2 Receiving Packets from SDIO Host 159
8.3.6 SDIO Bus Timing 160
8.3.7 Interrupt 161
8.3.7.1 Host Interrupt 161
8.3.7.2 Slave Interrupt 161
8.4 Register Summary 162
8.5 SLC Registers 164
8.6 SLC Host Registers 172
8.7 HINF Registers 186

9 SD/MMC Host Controller 187

9.1 Overview 187
9.2 Features 187
9.3 SD/MMC External Interface Signals 187
9.4 Functional Description 188
9.4.1 SD/MMC Host Controller Architecture 188
9.4.1.1 BIU 189
9.4.1.2 CIU 189
9.4.2 Command Path 190
9.4.3 Data Path 190
9.4.3.1 Data Transmit Operation 190
9.4.3.2 Data Receive Operation 191
9.5 Software Restrictions for Proper CIU Operation 191
9.6 RAM for Receiving and Sending Data 193
9.6.1 Transmit RAM Module 193
9.6.2 Receive RAM Module 193
9.7 Descriptor Chain 193
9.8 The Structure of a Linked List 194
9.9 Initialization 196
9.9.1 DMAC Initialization 196
9.9.2 DMAC Transmission Initialization 196
9.9.3 DMAC Reception Initialization 197
9.10 Clock Phase Selection 197
9.11 Interrupt 198
9.12 Register Summary 198
9.13 Registers 200

10 Ethernet MAC 218

10.1 Overview 218
10.2 EMAC_CORE 221
10.2.1 Transmit Operation 221
10.2.1.1 Transmit Flow Control 221
10.2.1.2 Retransmission During a Collision 222
10.2.2 Receive Operation 222
10.2.2.1 Reception Protocol 222
10.2.2.2 Receive Frame Controller 223
10.2.2.3 Receive Flow Control 223
10.2.2.4 Reception of Multiple Frames 224
10.2.2.5 Error Handling 224
10.2.2.6 Receive Status Word 224
10.3 MAC Interrupt Controller 224
10.4 MAC Address Filtering 225
10.4.1 Unicast Destination Address Filtering 225
 10.4.2 Multicast Destination Address Filtering 225
10.4.3 Broadcast Address Filtering 225
10.4.4 Unicast Source Address Filtering 225
10.4.5 Inverse Filtering Operation 226
10.4.6 Good Transmitted Frames and Received Frames 227
10.5 EMAC_MTL (MAC Transaction Layer) 228
10.6 PHY Interface 228
10.6.1 MII (Media Independent Interface) 228
10.6.1.1 Interface Signals Between MII and PHY 228
10.6.1.2 MII Clock 229
10.6.2 RMII (Reduced Media-Independent Interface) 230
10.6.2.1 RMII Interface Signal Description 230
10.6.2.2 RMII Clock 231
10.6.3 Station Management Agent (SMA) Interface 231
10.7 Ethernet DMA Features 231
10.8 Linked List Descriptors 232
10.8.1 Transmit Descriptors 232
10.8.2 Receive Descriptors 238
10.9 Register Summary 243
10.10Registers 245

11 I²C Controller 283

11.1 Overview 283
11.2 Features 283
11.3 Functional Description 283
11.3.1 Introduction 283
11.3.2 Architecture 284
11.3.3 I²C Bus Timing 285
11.3.4 I²C cmd Structure 285
11.3.5 I²C Master Writes to Slave 286
11.3.6 Master Reads from Slave 290
11.3.7 Interrupts 292
11.4 Register Summary 293
11.5 Registers 295

12 I²S 306
12.1 Overview 306
12.2 Features 307
12.3 The Clock of I²S Module 308
12.4 I²S Mode 309
12.4.1 Supported Audio Standards 309
12.4.1.1 Philips Standard 309
12.4.1.2 MSB Alignment Standard 310
12.4.1.3 PCM Standard 310
12.4.2 Module Reset 310
12.4.3 FIFO Operation 310
 12.4.4 Sending Data 311
12.4.5 Receiving Data 312
12.4.6 I²S Master/Slave Mode 314
12.4.7 I²S PDM 314
12.5 LCD Mode 317
12.5.1 LCD Master Transmitting Mode 317
12.5.2 Camera Slave Receiving Mode 318
12.5.3 ADC/DAC mode 319
12.6 I²S Interrupts 320
12.6.1 FIFO Interrupts 320
12.6.2 DMA Interrupts 320
12.7 Register Summary 320
12.8 Registers 323

13 UART Controllers 341

13.1 Overview 341
13.2 UART Features 341
13.3 Functional Description 341
13.3.1 Introduction 341
13.3.2 UART Architecture 342
13.3.3 UART RAM 343
13.3.4 Baud Rate Detection 344
13.3.5 UART Data Frame 344
13.3.6 Flow Control 345
13.3.6.1 Hardware Flow Control 345
13.3.6.2 Software Flow Control 346
13.3.7 UART DMA 346
13.3.8 UART Interrupts 346
13.3.9 UHCI Interrupts 347
13.4 Register Summary 348
13.4.1 UART Registers 348
13.4.2 UHCI Registers 349
13.5 Registers 351

14 LED_PWM 383
14.1 Introduction 383
14.2 Functional Description 383
14.2.1 Architecture 383
14.2.2 Timers 383
14.2.3 Channels 385
14.2.4 Interrupts 386
14.3 Register Summary 386
14.4 Registers 389

15 Remote Control Peripheral 399

15.1 Introduction 399
15.2 Functional Description 399
15.2.1 RMT Architecture 399
15.2.2 RMT RAM 400
15.2.3 Clock 400
15.2.4 Transmitter 401
15.2.5 Receiver 401
15.2.6 Interrupts 401
15.3 Register Summary 401
15.4 Registers 403

16 MCPWM 408
16.1 Introduction 408
16.2 Features 408
16.3 Submodules 410
16.3.1 Overview 410
16.3.1.1 Prescaler Submodule 410
16.3.1.2 Timer Submodule 410
16.3.1.3 Operator Submodule 411
16.3.1.4 Fault Detection Submodule 413
16.3.1.5 Capture Submodule 413
16.3.2 PWM Timer Submodule 413
16.3.2.1 Configurations of the PWM Timer Submodule 413
16.3.2.2 PWM Timer’s Working Modes and Timing Event Generation 414
16.3.2.3 PWM Timer Shadow Register 418
16.3.2.4 PWM Timer Synchronization and Phase Locking 418
16.3.3 PWM Operator Submodule 418
16.3.3.1 PWM Generator Submodule 419
16.3.3.2 Dead Time Generator Submodule 429
16.3.3.3 PWM Carrier Submodule 432
16.3.3.4 Fault Handler Submodule 435
16.3.4 Capture Submodule 437
16.3.4.1 Introduction 437
16.3.4.2 Capture Timer 437
16.3.4.3 Capture Channel 437
16.4 Register Summary 438
16.5 Registers 440

17 PULSE_CNT 487
17.1 Overview 487
17.2 Functional Description 487
17.2.1 Architecture 487
17.2.2 Counter Channel Inputs 488
17.2.3 Watchpoints 488
17.2.4 Examples 489
17.2.5 Interrupts 489
17.3 Register Summary 490
17.4 Registers 491

18 64-bit Timers 495

18.1 Introduction 495
18.2 Functional Description 495
18.2.1 16-bit Prescaler 495
18.2.2 64-bit Time-base Counter 495
18.2.3 Alarm Generation 496
18.2.4 MWDT 496
18.2.5 Interrupts 496
18.3 Register Summary 496
18.4 Registers 498

19 Watchdog Timers 505

19.1 Introduction 505
19.2 Features 505
19.3 Functional Description 505
19.3.1 Clock 505
19.3.1.1 Operating Procedure 506
19.3.1.2 Write Protection 506
19.3.1.3 Flash Boot Protection 506
19.3.1.4 Registers 507

20 eFuse Controller 508

20.1 Introduction 508
20.2 Features 508
20.3 Functional Description 508
20.3.1 Structure 508
20.3.1.1 System Parameter efuse_wr_disable 510
20.3.1.2 System Parameter efuse_rd_disable 510
20.3.1.3 System Parameter coding_scheme 511
20.3.1.4 BLK3_part_reserve 511
20.3.2 Programming of System Parameters 512
20.3.3 Software Reading of System Parameters 514
20.3.4 The Use of System Parameters by Hardware Modules 516
20.3.5 Interrupts 516
20.4 Register Summary 516
20.5 Registers 519

21 AES Accelerator 530

21.1 Introduction 530
21.2 Features 530
21.3 Functional Description 530
21.3.1 AES Algorithm Operations 530
21.3.2 Key, Plaintext and Ciphertext 530
21.3.3 Endianness 531
 21.3.4 Encryption and Decryption Operations 533
21.3.5 Speed 533
21.4 Register Summary 533
21.5 Registers 535

22 SHA Accelerator 537

22.1 Introduction 537
22.2 Features 537
22.3 Functional Description 537
22.3.1 Padding and Parsing the Message 537
22.3.2 Message Digest 538
22.3.3 Hash Operation 538
22.3.4 Speed 538
22.4 Register Summary 539
22.5 Registers 541

23 RSA Accelerator 547

23.1 Introduction 547
23.2 Features 547
23.3 Functional Description 547
23.3.1 Initialization 547
23.3.2 Large Number Modular Exponentiation 547
23.3.3 Large Number Modular Multiplication 549
23.3.4 Large Number Multiplication 549
23.4 Register Summary 550
23.5 Registers 551

24 Random Number Generator 553

24.1 Introduction 553
24.2 Feature 553
24.3 Functional Description 553
24.4 Register Summary 553
24.5 Register 553

25 Flash Encryption/Decryption 554

25.1 Overview 554
25.2 Features 554
25.3 Functional Description 554
25.3.1 Key Generator 555
25.3.2 Flash Encryption Block 555
25.3.3 Flash Decryption Block 556
25.4 Register Summary 556
25.5 Register 558

26 PID/MPU/MMU 559
26.1 Introduction 559
26.2 Features 559
26.3 Functional Description 559
26.3.1 PID Controller 559
26.3.2 MPU/MMU 560
26.3.2.1 Embedded Memory 560
26.3.2.2 External Memory 567
26.3.2.3 Peripheral 573

27 PID Controller 575

27.1 Overview 575
27.2 Features 575
27.3 Functional Description 575
27.3.1 Interrupt Identification 576
27.3.2 Information Recording 576
27.3.3 Proactive Process Switching 578
27.4 Register Summary 580
27.5 Registers 581

28 On-Chip Sensors and Analog Signal Processing 585

28.1 Introduction 585
28.2 Capacitive Touch Sensor 585
28.2.1 Introduction 585
28.2.2 Features 585
28.2.3 Available GPIOs 586
28.2.4 Functional Description 586
28.2.5 Touch FSM 587
28.3 SAR ADC 588
28.3.1 Introduction 588
28.3.2 Features 589
28.3.3 Outline of Function 589
28.3.4 RTC SAR ADC Controllers 591
28.3.5 DIG SAR ADC Controllers 592
28.4 Hall Sensor 594
28.4.1 Introduction 594
28.4.2 Features 594
28.4.3 Functional Description 595
28.5 DAC 595
28.5.1 Introduction 595
28.5.2 Features 595
28.5.3 Structure 596
28.5.4 Cosine Waveform Generator 596
28.5.5 DMA support 597
28.6 Register Summary 598
28.6.1 Sensors 598
28.6.2 Advanced Peripheral Bus 598
28.6.3 RTC I/O 599
28.7 Registers 600
28.7.1 Sensors 600
28.7.2 Advanced Peripheral Bus 610
28.7.3 RTC I/O 613

29 ULP Co-processor 614

29.1 Introduction 614
29.2 Features 614
29.3 Functional Description 615
29.4 Instruction Set 615
29.4.1 ALU - Perform Arithmetic/Logic Operations 616
29.4.1.1 Operations Among Registers 616
29.4.1.2 Operations with Immediate Value 617
29.4.1.3 Operations with Stage Count Register 617
29.4.2 ST – Store Data in Memory 618
29.4.3 LD – Load Data from Memory 618
29.4.4 JUMP – Jump to an Absolute Address 619
29.4.5 JUMPR – Jump to a Relative Offset (Conditional upon R0) 619
29.4.6 JUMPS – Jump to a Relative Address (Conditional upon Stage Count Register) 620
29.4.7 HALT – End the Program 620
29.4.8 WAKE – Wake up the Chip 620
29.4.9 Sleep – Set the ULP Timer’s Wake-up Period 621
29.4.10 WAIT – Wait for a Number of Cycles 621
29.4.11 ADC – Take Measurement with ADC 621
29.4.12 I2C_RD/I2C_WR – Read/Write I²C 622
29.4.13 REG_RD – Read from Peripheral Register 623
29.4.14 REG_WR – Write to Peripheral Register 623
29.5 ULP Program Execution 624
29.6 RTC_I2C Controller 625
29.6.1 Configuring RTC_I2C 626
29.6.2 Using RTC_I2C 626
29.6.2.1 I2C_RD - Read a Single Byte 626
29.6.2.2 I2C_WR - Write a Single Byte 627
29.6.2.3 Detecting Error Conditions 627
29.6.2.4 Connecting I²C Signals 628
29.7 Register Summary 628
29.7.1 SENS_ULP Address Space 628
29.7.2 RTC_I2C Address Space 628
29.8 Registers 630
29.8.1 SENS_ULP Address Space 630
29.8.2 RTC_I2C Address Space 632

30 Low-Power Management 638

30.1 Introduction 638
30.2 Features 638
30.3 Functional Description 639
 30.3.1 Overview 639
30.3.2 Digital Core Voltage Regulator 639
30.3.3 Low-Power Voltage Regulator 639
30.3.4 Flash Voltage Regulator 640
30.3.5 Brownout Detector 641
30.3.6 RTC Module 642
30.3.7 Low-Power Clocks 643
30.3.8 Power-Gating Implementation 645
30.3.9 Predefined Power Modes 646
30.3.10 Wakeup Source 647
30.3.11 RTC Timer 648
30.3.12 RTC Boot 648
30.4 Register Summary 650
30.5 Registers 653

Revision History 678

List of Tables
1 Address Mapping 24
2 Embedded Memory Address Mapping 25
3 Module with DMA 27
4 External Memory Address Mapping 28
5 Cache memory mode 28
6 Peripheral Address Mapping 29
7 PRO_CPU, APP_CPU Interrupt Configuration 33
8 CPU Interrupts 35
9 PRO_CPU and APP_CPU Reset Reason Values 37
10 CPU_CLK Source 39
11 CPU_CLK Derivation 40
12 Peripheral Clock Usage 40
13 APB_CLK Derivation 41
14 REF_TICK Derivation 41
15 LEDC_SCLK Derivation 41
16 IO_MUX Light-sleep Pin Function Registers 49
17 GPIO Matrix Peripheral Signals 51
18 IO_MUX Pad Summary 56
19 RTC_MUX Pin Summary 57
25 Mapping Between SPI Bus Signals and Pin Function Signals 121
26 Command Definitions Supported by GP-SPI Slave in Half-duplex Mode 123
27 Clock Polarity and Phase, and Corresponding SPI Register Values for SPI Master 125
28 Clock Polarity and Phase, and Corresponding SPI Register Values for SPI Slave 125
33 SD/MMC Signal Description 188
34 DES0 194
35 DES1 195
36 DES2 195
37 DES3 195
39 Destination Address Filtering 226
40 Source Address Filtering 227
41 Transmit Descriptor 0 (TDES0) 232
42 Transmit Descriptor 1 (TDES1) 236
43 Transmit Descriptor 2 (TDES2) 236
44 Transmit Descriptor 3 (TDES3) 236
45 Transmit Descriptor 6 (TDES6) 236
46 Transmit Descriptor 7 (TDES7) 237
47 Receive Descriptor 0 (RDES0) 238
48 Receive Descriptor 1 (RDES1) 240
49 Receive Descriptor 2 (RDES2) 241
50 Receive Descriptor 3 (RDES3) 241
51 Receive Descriptor 4 (RDES4) 241
52 Receive Descriptor 6 (RDES6) 243
53 Receive Descriptor 7 (RDES7) 243
55 SCL Frequency Configuration 285
57 I²S Signal Bus Description 307
58 Register Configuration 311
59 Send Channel Mode 312
60 Modes of Writing Received Data into FIFO and the Corresponding Register Configuration 313
61 The Register Configuration to Which the Four Modes Correspond 314
62 Upsampling Rate Configuration 315
63 Down-sampling Configuration 317
69 Configuration Parameters of the Operator Submodule 412
70 Timing Events Used in PWM Generator 420
71 Timing Events Priority When PWM Timer Increments 420
72 Timing Events Priority when PWM Timer Decrements 421
73 Dead Time Generator Switches Control Registers 430
74 Typical Dead Time Generator Operating Modes 431
79 System Parameters 508
80 BLOCK1/2/3 Encoding 511
81 Program Registers 512
82 Timing Configuration 514
83 Software Read Registers 515
85 Operation Mode 530
86 AES Text Endianness 531
87 AES-128 Key Endianness 532
88 AES-192 Key Endianness 532
89 AES-256 Key Endianness 532
95 MPU and MMU Structure for Internal Memory 560
96 MPU for RTC FAST Memory 561
97 MPU for RTC SLOW Memory 561
98 Page Mode of MMU for the Remaining 128 KB of Internal SRAM0 and SRAM2 562
99 Page Boundaries for SRAM0 MMU 563
100 Page Boundaries for SRAM2 MMU 564
101 DPORT_DMMU_TABLEn_REG & DPORT_IMMU_TABLEn_REG 565
102 MPU for DMA 566
103 Virtual Address for External Memory 568
104 MMU Entry Numbers for PRO_CPU 568
105 MMU Entry Numbers for APP_CPU 568
106 MMU Entry Numbers for PRO_CPU (Special Mode) 569
107 MMU Entry Numbers for APP_CPU (Special Mode) 569
108 Virtual Address Mode for External SRAM 570
109 Virtual Address for External SRAM ( Normal Mode ) 571
110 Virtual Address for External SRAM ( Low-High Mode ) 571
111 Virtual Address for External SRAM ( Even-Odd Mode ) 571
112 MMU Entry Numbers for External RAM 572
113 MPU for Peripheral 573
114 DPORT_AHBLITE_MPU_TABLE_X_REG 574
115 Interrupt Vector Entry Address 576
116 Configuration of PIDCTRL_LEVEL_REG 576
117 Configuration of PIDCTRL_FROM_n_REG 577
119 ESP32 Capacitive Sensing Touch Pads 586
120 Inputs of SAR ADC module 590
121 ESP32 SAR ADC Controllers 591
122 Fields of the Pattern Table Register 593
123 Fields of Type I DMA Data Format 594
124 Fields of Type II DMA Data Format 594
127 ALU Operations Among Registers 616
128 ALU Operations with Immediate Value 617
129 ALU Operations with Stage Count Register 618
131 Input Signals Measured Using the ADC Instruction 622
135 RTC Power Domains 645
136 Wake-up Source 648
List of Figures
1 System Structure 23
2 System Address Mapping 23
3 Cache Block Diagram 28
4 Interrupt Matrix Structure 32
5 System Reset 37
6 System Clock 38
7 IO_MUX, RTC IO_MUX and GPIO Matrix Overview 44
8 Peripheral Input via IO_MUX, GPIO Matrix 45
9 Output via GPIO Matrix 47
10 ESP32 I/O Pad Power Sources (QFN 6*6, Top View) 50
11 ESP32 I/O Pad Power Sources (QFN 5*5, Top View) 51
12 DMA Engine Architecture 116
13 Linked List Structure 117
14 Data Transfer in UDMA Mode 118
15 SPI DMA 119
16 SPI Architecture 121
17 SPI Master and Slave Full-duplex/Half-duplex Communication 122
18 SPI Data Buffer 124
19 GP-SPI ������ 127
20 Parallel QSPI 127
21 Communication Format of Parallel QSPI 128
22 SDIO Slave Block Diagram 155
23 SDIO Bus Packet Transmission 156
24 CMD53 Content 156
25 SDIO Slave DMA Linked List Structure 157
26 SDIO Slave Linked List 157
27 Packet Sending Procedure (Initiated by Slave) 158
28 Packet Receiving Procedure (Initiated by Host) 159
29 Loading Receiving Buffer 160
30 Sampling Timing Diagram 160
31 Output Timing Diagram 161
32 SD/MMC Controller Topology 187
33 SD/MMC Controller External Interface Signals 188
34 SDIO Host Block Diagram 189
35 Command Path State Machine 190
36 Data Transmit State Machine 191
37 Data Receive State Machine 191
38 Descriptor Chain 193
39 The Structure of a Linked List 194
40 Clock Phase Selection 198
41 Ethernet MAC Functionality Overview 218
42 Ethernet Block Diagram 220
43 MII Interface 228
44 MII Clock 230
45 RMII Interface 230
46 RMII Clock 231
47 Transmit Descriptor 232
48 Receive Descriptor 238
49 IC Master Architecture 284
50 IC Slave Architecture 284
51 IC Sequence Chart 285
52 Structure of The IC Command Register 286
53 IC Master Writes to Slave with 7-bit Address 287
54 IC Master Writes to Slave with 10-bit Address 288
55 IC Master Writes to addrM in RAM of Slave with 7-bit Address 289
56 Master Writes to Slave with 7-bit Address in Three Segments 289
57 Master Reads from Slave with 7-bit Address 290
58 Master Reads from Slave with 10-bit Address 291
59 Master Reads N Bytes of Data from addrM in Slave with 7-bit Address 291
60 Master Reads from Slave with 7-bit Address in Three Segments 292
61 I2S System Block Diagram 306
62 I²S Clock 308
63 Philips Standard 309
64 MSB Alignment Standard 310
65 PCM Standard 310
66 Tx FIFO Data Mode 311
67 The First Stage of Receiving Data 313
68 Modes of Writing Received Data into FIFO 313
69 PDM Transmitting Module 315
70 PDM Sends Signal 315
71 PDM Receives Signal 316
72 PDM Receive Module 316
73 LCD Master Transmitting Mode 317
74 LCD Master Transmitting Data Frame, Form 1 317
75 LCD Master Transmitting Data Frame, Form 2 318
76 Camera Slave Receiving Mode 318
77 ADC Interface of I2S0 319
78 DAC Interface of I²S 319
79 Data Input by I²S DAC Interface 319
80 UART Basic Structure 342
81 UART Shared RAM 343
82 UART Data Frame Structure 344
83 AT_CMD Character Format 344
84 Hardware Flow Control 345
85 LED_PWM Architecture 383
86 LED_PWM High-speed Channel Diagram 384
87 LED_PWM Divider 384
88 LED PWM Output Signal Diagram 385
89 Output Signal Diagram of Fading Duty Cycle 385
90 RMT Architecture 399
91 Data Structure 400
92 MCPWM Module Overview 408
93 Prescaler Submodule 410
94 Timer Submodule 410
95 Operator Submodule 411
96 Fault Detection Submodule 413
97 Capture Submodule 413
98 Count-Up Mode Waveform 414
99 Count-Down Mode Waveforms 415
100 Count-Up-Down Mode Waveforms, Count-Down at Synchronization Event 415
101 Count-Up-Down Mode Waveforms, Count-Up at Synchronization Event 415
102 UTEP and UTEZ Generation in Count-Up Mode 416
103 DTEP and DTEZ Generation in Count-Down Mode 417
104 DTEP and UTEZ Generation in Count-Up-Down Mode 417
105 Submodules Inside the PWM Operator 419
106 Symmetrical Waveform in Count-Up-Down Mode 422
107 Count-Up, Single Edge Asymmetric Waveform, with Independent Modulation on PWMxA and PWMxB
— Active High 423
108 Count-Up, Pulse Placement Asymmetric Waveform with Independent Modulation on PWMxA 424
109 Count-Up-Down, Dual Edge Symmetric Waveform, with Independent Modulation on PWMxA and
PWMxB — Active High 425
110 Count-Up-Down, Dual Edge Symmetric Waveform, with Independent Modulation on PWMxA and
PWMxB — Complementary 426
111 Example of an NCI Software-Force Event on PWMxA 427
112 Example of a CNTU Software-Force Event on PWMxB 428
113 Options for Setting up the Dead Time Generator Submodule 430
114 Active High Complementary (AHC) Dead Time Waveforms 431
115 Active Low Complementary (ALC) Dead Time Waveforms 432
116 Active High (AH) Dead Time Waveforms 432
117 Active Low (AL) Dead Time Waveforms 433
118 Example of Waveforms Showing PWM Carrier Action 434
119 Example of the First Pulse and the Subsequent Sustaining Pulses of the PWM Carrier Submodule 435
120 Possible Duty Cycle Settings for Sustaining Pulses in the PWM Carrier Submodule 435
121 PULSE_CNT Architecture 487
122 PULSE_CNT Upcounting Diagram 489
123 PULSE_CNT Downcounting Diagram 489
124 Flash Encryption/Decryption Module Architecture 554
125 MMU Access Example 562
126 Interrupt Nesting 578
127 Touch Sensor 585
128 Touch Sensor Structure 586
129 Touch Sensor Operating Flow 587
130 Touch FSM Structure 588
131 SAR ADC Depiction 589
132 SAR ADC Outline of Function 590
133 RTC SAR ADC Outline of Function 592
134 Diagram of DIG SAR ADC Controllers 593
135 Hall Sensor 595
136 Diagram of DAC Function 596
137 Cosine Waveform (CW) Generator 597
138 ULP Co-processor Diagram 614
139 The ULP Co-processor Instruction Format 615
140 Instruction Type — ALU for Operations Among Registers 616
141 Instruction Type — ALU for Operations with Immediate Value 617
142 Instruction Type — ALU for Operations with Stage Count Register 617
143 Instruction Type — ST 618
144 Instruction Type — LD 618
145 Instruction Type — JUMP 619
146 Instruction Type — JUMPR 619
147 Instruction Type — JUMP 620
148 Instruction Type — HALT 620
149 Instruction Type — WAKE 621
150 Instruction Type — SLEEP 621
151 Instruction Type — WAIT 621
152 Instruction Type — ADC 621
153 Instruction Type — I²C 622
154 Instruction Type — REG_RD 623
155 Instruction Type — REG_WR 623
156 Control of ULP Program Execution 624
157 Sample of a ULP Operation Sequence 625
158 I²C Read Operation 627
159 I²C Write Operation 627
160 ESP32 Power Control 638
161 Digital Core Voltage Regulator 639
162 Low-Power Voltage Regulator 640
163 Flash Voltage Regulator 641
164 Brownout Detector 641
165 RTC Structure 643
166 RTC Low-Power Clocks 644
167 Digital Low-Power Clocks 644
168 RTC States 645
169 Power Modes 647
170 ESP32 Boot Flow 650
1. System and Memory

1. System and Memory

1.1 Introduction
The ESP32 is a dual-core system with two Harvard Architecture Xtensa LX6 CPUs. All embedded memory,
external memory and peripherals are located on the data bus and/or the instruction bus of these CPUs.

With some minor exceptions (see below), the address mapping of two CPUs is symmetric, meaning that they use
the same addresses to access the same memory. Multiple peripherals in the system can access embedded
memory via DMA.

The two CPUs are named “PRO_CPU” and “APP_CPU” (for “protocol” and “application”), however, for most
purposes the two CPUs are interchangeable.

1.2 Features
• Address Space

– Symmetric address mapping

– 4 GB (32-bit) address space for both data bus and instruction bus

– 1296 KB embedded memory address space

– 19704 KB external memory address space

– 512 KB peripheral address space

– Some embedded and external memory regions can be accessed by either data bus or instruction bus

– 328 KB DMA address space

• Embedded Memory

– 448 KB Internal ROM

– 520 KB Internal SRAM

– 8 KB RTC FAST Memory

– 8 KB RTC SLOW Memory

• External Memory
Off-chip SPI memory can be mapped into the available address space as external memory. Parts of the
embedded memory can be used as transparent cache for this external memory.

– Supports up to 16 MB off-Chip SPI Flash.

– Supports up to 8 MB off-Chip SPI SRAM.

• Peripherals

– 41 peripherals

• DMA

– 13 modules are capable of DMA operation

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1. System and Memory

The block diagram in Figure 1 illustrates the system structure, and the block diagram in Figure 2 illustrates the
address map structure.

Figure 1: System Structure

Figure 2: System Address Mapping

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1. System and Memory

1.3 Functional Description

1.3.1 Address Mapping
Each of the two Harvard Architecture Xtensa LX6 CPUs has 4 GB (32-bit) address space. Address spaces are
symmetric between the two CPUs.

Addresses below 0x4000_0000 are serviced using the data bus. Addresses in the range 0x4000_0000 ~
0x4FFF_FFFF are serviced using the instruction bus. Finally, addresses over and including 0x5000_0000 are
shared by the data and instruction bus.

The data bus and instruction bus are both little-endian: for example, byte addresses 0x0, 0x1, 0x2, 0x3 access
the least significant, second least significant, second most significant, and the most significant bytes of the 32-bit
word stored at the 0x0 address, respectively. The CPU can access data bus addresses via aligned or non-aligned
byte, half-word and word read-and-write operations. The CPU can read and write data through the instruction
bus, but only in a word aligned manner; non-word-aligned access will cause a CPU exception.

Each CPU can directly access embedded memory through both the data bus and the instruction bus, external
memory which is mapped into the address space (via transparent caching & MMU), and peripherals. Table 1
illustrates address ranges that can be accessed by each CPU’s data bus and instruction bus.

Some embedded memories and some external memories can be accessed via the data bus or the instruction
bus. In these cases, the same memory is available to either of the CPUs at two address ranges.

Table 1: Address Mapping

Boundary Address
Bus Type Size Target
Low Address High Address
0x0000_0000 0x3F3F_FFFF Reserved
Data 0x3F40_0000 0x3F7F_FFFF 4 MB External Memory
Data 0x3F80_0000 0x3FBF_FFFF 4 MB External Memory
0x3FC0_0000 0x3FEF_FFFF 3 MB Reserved
Data 0x3FF0_0000 0x3FF7_FFFF 512 KB Peripheral
Data 0x3FF8_0000 0x3FFF_FFFF 512 KB Embedded Memory
Instruction 0x4000_0000 0x400C_1FFF 776 KB Embedded Memory
Instruction 0x400C_2000 0x40BF_FFFF 11512 KB External Memory
0x40C0_0000 0x4FFF_FFFF 244 MB Reserved
Data / Instruction 0x5000_0000 0x5000_1FFF 8 KB Embedded Memory
0x5000_2000 0xFFFF_FFFF Reserved

1.3.2 Embedded Memory

The Embedded Memory consists of four segments: internal ROM (448 KB), internal SRAM (520 KB), RTC FAST
memory (8 KB) and RTC SLOW memory (8 KB).

The 448 KB internal ROM is divided into two parts: Internal ROM 0 (384 KB) and Internal ROM 1 (64 KB). The
520 KB internal SRAM is divided into three parts: Internal SRAM 0 (192 KB), Internal SRAM 1 (128 KB), and
Internal SRAM 2 (200 KB). RTC FAST Memory and RTC SLOW Memory are both implemented as SRAM.

Table 2 lists all embedded memories and their address ranges on the data and instruction buses.

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1. System and Memory

Table 2: Embedded Memory Address Mapping

Boundary Address
Bus Type Size Target Comment
Low Address High Address
Data 0x3FF8_0000 0x3FF8_1FFF 8 KB RTC FAST Memory PRO_CPU Only
0x3FF8_2000 0x3FF8_FFFF 56 KB Reserved -
Data 0x3FF9_0000 0x3FF9_FFFF 64 KB Internal ROM 1 -
0x3FFA_0000 0x3FFA_DFFF 56 KB Reserved -
Data 0x3FFA_E000 0x3FFD_FFFF 200 KB Internal SRAM 2 DMA
Data 0x3FFE_0000 0x3FFF_FFFF 128 KB Internal SRAM 1 DMA
Boundary Address
Bus Type Size Target Comment
Low Address High Address
Instruction 0x4000_0000 0x4000_7FFF 32 KB Internal ROM 0 Remap
Instruction 0x4000_8000 0x4005_FFFF 352 KB Internal ROM 0 -
0x4006_0000 0x4006_FFFF 64 KB Reserved -
Instruction 0x4007_0000 0x4007_FFFF 64 KB Internal SRAM 0 Cache
Instruction 0x4008_0000 0x4009_FFFF 128 KB Internal SRAM 0 -
Instruction 0x400A_0000 0x400A_FFFF 64 KB Internal SRAM 1 -
Instruction 0x400B_0000 0x400B_7FFF 32 KB Internal SRAM 1 Remap
Instruction 0x400B_8000 0x400B_FFFF 32 KB Internal SRAM 1 -
Instruction 0x400C_0000 0x400C_1FFF 8 KB RTC FAST Memory PRO_CPU Only
Boundary Address
Bus Type Size Target Comment
Low Address High Address
Data Instruc-
0x5000_0000 0x5000_1FFF 8 KB RTC SLOW Memory -
tion

1.3.2.1 Internal ROM 0

The capacity of Internal ROM 0 is 384 KB. It is accessible by both CPUs through the address range
0x4000_0000 ~ 0x4005_FFFF, which is on the instruction bus.

The address range of the first 32 KB of the ROM 0 (0x4000_0000 ~ 0x4000_7FFF) can be remapped in order to
access a part of Internal SRAM 1 that normally resides in a memory range of 0x400B_0000 ~ 0x400B_7FFF.
While remapping, the 32 KB SRAM cannot be accessed by an address range of 0x400B_0000 ~ 0x400B_7FFF
any more, but it can still be accessible through the data bus (0x3FFE_8000 ~ 0x3FFE_FFFF). This can be done
on a per-CPU basis: setting bit 0 of register DPORT_PRO_BOOT_REMAP_CTRL_REG or
DPORT_APP_BOOT_REMAP_CTRL_REG will remap SRAM for the PRO_CPU and APP_CPU,
respectively.

1.3.2.2 Internal ROM 1

The capacity of Internal ROM 1 is 64 KB. It can be read by either CPU at an address range 0x3FF9_0000 ~
0x3FF9_FFFF of the data bus.

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1. System and Memory

1.3.2.3 Internal SRAM 0

The capacity of Internal SRAM 0 is 192 KB. Hardware can be configured to use the first 64 KB to cache external
memory access. When not used as cache, the first 64 KB can be read and written by either CPU at addresses
0x4007_0000 ~ 0x4007_FFFF of the instruction bus. The remaining 128 KB can always be read and written by
either CPU at addresses 0x4008_0000 ~ 0x4009_FFFF of instruction bus.

1.3.2.4 Internal SRAM 1

The capacity of Internal SRAM 1 is 128 KB. Either CPU can read and write this memory at addresses
0x3FFE_0000 ~ 0x3FFF_FFFF of the data bus, and also at addresses 0x400A_0000 ~ 0x400B_FFFF of the
instruction bus.

The address range accessed via the instruction bus is in reverse order (word-wise) compared to access via the
data bus. That is to say, address
0x3FFE_0000 and 0x400B_FFFC access the same word
0x3FFE_0004 and 0x400B_FFF8 access the same word
0x3FFE_0008 and 0x400B_FFF4 access the same word
……
0x3FFF_FFF4 and 0x400A_0008 access the same word
0x3FFF_FFF8 and 0x400A_0004 access the same word
0x3FFF_FFFC and 0x400A_0000 access the same word

The data bus and instruction bus of the CPU are still both little-endian, so the byte order of individual words is not
reversed between address spaces. For example, address
0x3FFE_0000 accesses the least significant byte in the word accessed by 0x400B_FFFC.
0x3FFE_0001 accesses the second least significant byte in the word accessed by 0x400B_FFFC.
0x3FFE_0002 accesses the second most significant byte in the word accessed by 0x400B_FFFC.
0x3FFE_0003 accesses the most significant byte in the word accessed by 0x400B_FFFC.
0x3FFE_0004 accesses the least significant byte in the word accessed by 0x400B_FFF8.
0x3FFE_0005 accesses the second least significant byte in the word accessed by 0x400B_FFF8.
0x3FFE_0006 accesses the second most significant byte in the word accessed by 0x400B_FFF8.
0x3FFE_0007 accesses the most significant byte in the word accessed by 0x400B_FFF8.
……
0x3FFF_FFF8 accesses the least significant byte in the word accessed by 0x400A_0004.
0x3FFF_FFF9 accesses the second least significant byte in the word accessed by 0x400A_0004.
0x3FFF_FFFA accesses the second most significant byte in the word accessed by 0x400A_0004.
0x3FFF_FFFB accesses the most significant byte in the word accessed by 0x400A_0004.
0x3FFF_FFFC accesses the least significant byte in the word accessed by 0x400A_0000.
0x3FFF_FFFD accesses the second most significant byte in the word accessed by 0x400A_0000.
0x3FFF_FFFE accesses the second most significant byte in the word accessed by 0x400A_0000.
0x3FFF_FFFF accesses the most significant byte in the word accessed by 0x400A_0000.

Part of this memory can be remapped onto the ROM 0 address space. See Internal Rom 0 for more
information.

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1. System and Memory

1.3.2.5 Internal SRAM 2

The capacity of Internal SRAM 2 is 200 KB. It can be read and written by either CPU at addresses 0x3FFA_E000
~ 0x3FFD_FFFF on the data bus.

1.3.2.6 DMA

DMA uses the same addressing as the CPU data bus to read and write Internal SRAM 1 and Internal SRAM 2.
This means DMA uses an address range of 0x3FFE_0000 ~ 0x3FFF_FFFF to read and write Internal SRAM 1 and
an address range of 0x3FFA_E000 ~ 0x3FFD_FFFF to read and write Internal SRAM 2.

In the ESP32, 13 peripherals are equipped with DMA. Table 3 lists these peripherals.

Table 3: Module with DMA

UART0 UART1 UART2

SPI1 SPI2 SPI3
I2S0 I2S1
SDIO Slave SDMMC
EMAC
BT WIFI

1.3.2.7 RTC FAST Memory

RTC FAST Memory is 8 KB of SRAM. It can be read and written by PRO_CPU only at an address range of
0x3FF8_0000 ~ 0x3FF8_1FFF on the data bus or at an address range of 0x400C_0000 ~ 0x400C_1FFF on the
instruction bus. Unlike most other memory regions, RTC FAST memory cannot be accessed by the
APP_CPU.

The two address ranges of PRO_CPU access RTC FAST Memory in the same order, so, for example, addresses
0x3FF8_0000 and 0x400C_0000 access the same word. On the APP_CPU, these address ranges do not
provide access to RTC FAST Memory or any other memory location.

1.3.2.8 RTC SLOW Memory

RTC SLOW Memory is 8 KB of SRAM which can be read and written by either CPU at an address range of
0x5000_0000 ~ 0x5000_1FFF. This address range is shared by both the data bus and the instruction bus.

1.3.3 External Memory

The ESP32 can access external SPI flash and SPI SRAM as external memory. Table 4 provides a list of external
memories that can be accessed by either CPU at a range of addresses on the data and instruction buses. When
a CPU accesses external memory through the Cache and MMU, the cache will map the CPU’s address to an
external physical memory address (in the external memory’s address space), according to the MMU settings. Due
to this address mapping, the ESP32 can address up to 16 MB External Flash and 8 MB External SRAM.

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1. System and Memory

Table 4: External Memory Address Mapping

Boundary Address
Bus Type Size Target Comment
Low Address High Address
Data 0x3F40_0000 0x3F7F_FFFF 4 MB External Flash Read
Data 0x3F80_0000 0x3FBF_FFFF 4 MB External SRAM Read and Write
Boundary Address
Bus Type Size Target Comment
Low Address High Address
Instruction 0x400C_2000 0x40BF_FFFF 11512 KB External Flash Read

1.3.4 Cache
As shown in Figure 3, each of the two CPUs in ESP32 has 32 KB of cache for accessing external storage. PRO
CPU uses bit PRO_CACHE_ENABLE in register DPORT_PRO_CACHE_CTRL_REG to enable the Cache, while
APP CPU uses bit APP_CACHE_ENABLE in register DPORT_APP_CACHE_CTRL_REG to enable the same
function.

Figure 3: Cache Block Diagram

ESP32 uses a two-way set-associative cache. When the Cache function is to be used either by PRO CPU or
APP CPU, bit CACHE_MUX_MODE[1:0] in register DPORT_CACHE_MUX_MODE_REG can be set to select
POOL0 or POOL1 in the Internal SRAM0 as the cache memory. When both PRO CPU and APP CPU use the
Cache function, POOL0 and POOL1 in the Internal SRAM0 will be used simultaneously as the cache memory,
while they can also be used by the instruction bus. This is depicted in table 5 below.

Table 5: Cache memory mode

CACHE_MUX_MODE POOL0 POOL1

0 PRO CPU APP CPU
1 PRO CPU/APP CPU -
2 - PRO CPU/APP CPU
3 APP CPU PRO CPU

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1. System and Memory

As described in table 5, when bit CACHE_MUX_MODE is set to 1 or 2, PRO CPU and APP CPU cannot enable
the Cache function at the same time. When the Cache function is enabled, POOL0 or POOL1 can only be used
as the cache memory, and cannot be used by the instruction bus as well.

ESP32 Cache supports the Flush function. It is worth noting that when the Flush function is used, the data
written in the cache will be disposed rather than being rewritten into the External SRAM. To enable the Flush
function, first clear bit x_CACHE_FLUSH_ENA in register DPORT_x_CACHE_CTRL_REG, then set this bit to 1.
Afterwards, the system hardware will set bit x_CACHE_FLUSH_DONE to 1, where x can be ”PRO” or ”APP”,
indicating that the cache flush operation has been completed.

For more information about the address mapping of ESP32 Cache, please refer to Embedded Memory and
External Memory.

1.3.5 Peripherals
The ESP32 has 41 peripherals. Table 6 specifically describes the peripherals and their respective address
ranges. Nearly all peripheral modules can be accessed by either CPU at the same address with just a single
exception; this being the PID Controller.

Table 6: Peripheral Address Mapping

Boundary Address
Bus Type Size Target Comment
Low Address High Address
Data 0x3FF0_0000 0x3FF0_0FFF 4 KB DPort Register
Data 0x3FF0_1000 0x3FF0_1FFF 4 KB AES Accelerator
Data 0x3FF0_2000 0x3FF0_2FFF 4 KB RSA Accelerator
Data 0x3FF0_3000 0x3FF0_3FFF 4 KB SHA Accelerator
Data 0x3FF0_4000 0x3FF0_4FFF 4 KB Secure Boot
0x3FF0_5000 0x3FF0_FFFF 44 KB Reserved
Data 0x3FF1_0000 0x3FF1_3FFF 16 KB Cache MMU Table
0x3FF1_4000 0x3FF1_EFFF 44 KB Reserved
Data 0x3FF1_F000 0x3FF1_FFFF 4 KB PID Controller Per-CPU peripheral
0x3FF2_0000 0x3FF3_FFFF 128 KB Reserved
Data 0x3FF4_0000 0x3FF4_0FFF 4 KB UART0
0x3FF4_1000 0x3FF4_1FFF 4 KB Reserved
Data 0x3FF4_2000 0x3FF4_2FFF 4 KB SPI1
Data 0x3FF4_3000 0x3FF4_3FFF 4 KB SPI0
Data 0x3FF4_4000 0x3FF4_4FFF 4 KB GPIO
0x3FF4_5000 0x3FF4_7FFF 12 KB Reserved
Data 0x3FF4_8000 0x3FF4_8FFF 4 KB RTC
Data 0x3FF4_9000 0x3FF4_9FFF 4 KB IO MUX
0x3FF4_A000 0x3FF4_AFFF 4 KB Reserved
Data 0x3FF4_B000 0x3FF4_BFFF 4 KB SDIO Slave One of three parts
Data 0x3FF4_C000 0x3FF4_CFFF 4 KB UDMA1
0x3FF4_D000 0x3FF4_EFFF 8 KB Reserved
Data 0x3FF4_F000 0x3FF4_FFFF 4 KB I2S0
Data 0x3FF5_0000 0x3FF5_0FFF 4 KB UART1

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1. System and Memory

Boundary Address
Bus Type Size Target Comment
Low Address High Address
0x3FF5_1000 0x3FF5_2FFF 8 KB Reserved
Data 0x3FF5_3000 0x3FF5_3FFF 4 KB I2C0
Data 0x3FF5_4000 0x3FF5_4FFF 4 KB UDMA0
Data 0x3FF5_5000 0x3FF5_5FFF 4 KB SDIO Slave One of three parts
Data 0x3FF5_6000 0x3FF5_6FFF 4 KB RMT
Data 0x3FF5_7000 0x3FF5_7FFF 4 KB PCNT
Data 0x3FF5_8000 0x3FF5_8FFF 4 KB SDIO Slave One of three parts
Data 0x3FF5_9000 0x3FF5_9FFF 4 KB LED PWM
Data 0x3FF5_A000 0x3FF5_AFFF 4 KB Efuse Controller
Data 0x3FF5_B000 0x3FF5_BFFF 4 KB Flash Encryption
0x3FF5_C000 0x3FF5_DFFF 8 KB Reserved
Data 0x3FF5_E000 0x3FF5_EFFF 4 KB PWM0
Data 0x3FF5_F000 0x3FF5_FFFF 4 KB TIMG0
Data 0x3FF6_0000 0x3FF6_0FFF 4 KB TIMG1
0x3FF6_1000 0x3FF6_3FFF 12 KB Reserved
Data 0x3FF6_4000 0x3FF6_4FFF 4 KB SPI2
Data 0x3FF6_5000 0x3FF6_5FFF 4 KB SPI3
Data 0x3FF6_6000 0x3FF6_6FFF 4 KB SYSCON
Data 0x3FF6_7000 0x3FF6_7FFF 4 KB I2C1
Data 0x3FF6_8000 0x3FF6_8FFF 4 KB SDMMC
Data 0x3FF6_9000 0x3FF6_AFFF 8 KB EMAC
0x3FF6_B000 0x3FF6_BFFF 4 KB Reserved
Data 0x3FF6_C000 0x3FF6_CFFF 4 KB PWM1
Data 0x3FF6_D000 0x3FF6_DFFF 4 KB I2S1
Data 0x3FF6_E000 0x3FF6_EFFF 4 KB UART2
Data 0x3FF6_F000 0x3FF6_FFFF 4 KB PWM2
Data 0x3FF7_0000 0x3FF7_0FFF 4 KB PWM3
0x3FF7_1000 0x3FF7_4FFF 16 KB Reserved
Data 0x3FF7_5000 0x3FF7_5FFF 4 KB RNG
0x3FF7_6000 0x3FF7_FFFF 40 KB Reserved

1.3.5.1 Asymmetric PID Controller Peripheral

There are two PID Controllers in the system. They serve the PRO_CPU and the APP_CPU, respectively. The
PRO_CPU and the APP_CPU can only access their own PID Controller and not that of their counterpart.
Each CPU uses the same memory range 0x3FF1_F000 ~ 3FF1_FFFF to access its own PID Controller.

1.3.5.2 Non-Contiguous Peripheral Memory Ranges

The SDIO Slave peripheral consists of three parts and the two CPUs use non-contiguous addresses to access
these. The three parts are accessed at the address ranges 0x3FF4_B000 ~ 3FF4_BFFF, 0x3FF5_5000 ~

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1. System and Memory

3FF5_5FFF and 0x3FF5_8000 ~ 3FF5_8FFF of each CPU’s data bus. Similarly to other peripherals, access to
this peripheral is identical for both CPUs.

1.3.5.3 Memory Speed

The ROM as well as the SRAM are both clocked from CPU_CLK and can be accessed by the CPU in a single
cycle. The RTC FAST memory is clocked from the APB_CLOCK and the RTC SLOW memory from the
FAST_CLOCK, so access to these memories may be slower. DMA uses the APB_CLK to access memory.

Internally, the SRAM is organized in 32K-sized banks. Each CPU and DMA channel can simultaneously access
the SRAM at full speed, provided they access addresses in different memory banks.

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2. Interrupt Matrix

2. Interrupt Matrix

2.1 Overview
The Interrupt Matrix embedded in the ESP32 independently allocates peripheral interrupt sources to the two
CPUs’ peripheral interrupts. This configuration is made to be highly flexible in order to meet many different needs.

2.2 Features
• Accepts 71 peripheral interrupt sources as input.

• Generates 26 peripheral interrupt sources per CPU as output (52 total).

• CPU NMI Interrupt Mask.

• Queries current interrupt status of peripheral interrupt sources.

The structure of the Interrupt Matrix is shown in Figure 4.

Figure 4: Interrupt Matrix Structure

2.3 Functional Description

2.3.1 Peripheral Interrupt Source
ESP32 has 71 peripheral interrupt sources in total. All peripheral interrupt sources are listed in table 7. 67 of 71
ESP32 peripheral interrupt sources can be allocated to either CPU.

The four remaining peripheral interrupt sources are CPU-specific, two per CPU. GPIO_INTERRUPT_PRO and
GPIO_INTERRUPT_PRO_NMI can only be allocated to PRO_CPU. GPIO_INTERRUPT_APP and
GPIO_INTERRUPT_APP_NMI can only be allocated to APP_CPU. As a result, PRO_CPU and APP_CPU each
have 69 peripheral interrupt sources.

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 Table 7: PRO_CPU, APP_CPU Interrupt Configuration
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2. Interrupt Matrix
PRO_CPU APP_CPU
Peripheral Interrupt Source
Peripheral Interrupt Peripheral Interrupt
Status Register Status Register
Configuration Register No. Name No. Configuration Register
Bit Name Name Bit
PRO_MAC_INTR_MAP_REG 0 0 MAC_INTR 0 0 APP_MAC_INTR_MAP_REG
PRO_MAC_NMI_MAP_REG 1 1 MAC_NMI 1 1 APP_MAC_NMI_MAP_REG
PRO_BB_INT_MAP_REG 2 2 BB_INT 2 2 APP_BB_INT_MAP_REG
PRO_BT_MAC_INT_MAP_REG 3 3 BT_MAC_INT 3 3 APP_BT_MAC_INT_MAP_REG
PRO_BT_BB_INT_MAP_REG 4 4 BT_BB_INT 4 4 APP_BT_BB_INT_MAP_REG
PRO_BT_BB_NMI_MAP_REG 5 5 BT_BB_NMI 5 5 APP_BT_BB_NMI_MAP_REG
PRO_RWBT_IRQ_MAP_REG 6 6 RWBT_IRQ 6 6 APP_RWBT_IRQ_MAP_REG
PRO_BT_BB_NMI_MAP_REG 5 5 BT_BB_NMI 5 5 APP_BT_BB_NMI_MAP_REG
PRO_RWBT_IRQ_MAP_REG 6 6 RWBT_IRQ 6 6 APP_RWBT_IRQ_MAP_REG
PRO_RWBLE_IRQ_MAP_REG 7 7 RWBLE_IRQ 7 7 APP_RWBLE_IRQ_MAP_REG
PRO_RWBT_NMI_MAP_REG 8 8 RWBT_NMI 8 8 APP_RWBT_NMI_MAP_REG
PRO_RWBLE_NMI_MAP_REG 9 9 RWBLE_NMI 9 9 APP_RWBLE_NMI_MAP_REG
PRO_SLC0_INTR_MAP_REG 10 10 SLC0_INTR 10 10 APP_SLC0_INTR_MAP_REG
PRO_SLC1_INTR_MAP_REG 11 11 SLC1_INTR 11 11 APP_SLC1_INTR_MAP_REG
PRO_UHCI0_INTR_MAP_REG 12 12 UHCI0_INTR 12 12 APP_UHCI0_INTR_MAP_REG
PRO_UHCI1_INTR_MAP_REG 13 13 UHCI1_INTR 13 13 APP_UHCI1_INTR_MAP_REG
PRO_INTR_STATUS_REG_0 APP_INTR_STATUS_REG_0
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PRO_TG_T0_LEVEL_INT_MAP_REG 14 14 TG_T0_LEVEL_INT 14 14 APP_TG_T0_LEVEL_INT_MAP_REG

PRO_TG_T1_LEVEL_INT_MAP_REG 15 15 TG_T1_LEVEL_INT 15 15 APP_TG_T1_LEVEL_INT_MAP_REG
PRO_TG_WDT_LEVEL_INT_MAP_REG 16 16 TG_WDT_LEVEL_INT 16 16 APP_TG_WDT_LEVEL_INT_MAP_REG
PRO_TG_LACT_LEVEL_INT_MAP_REG 17 17 TG_LACT_LEVEL_INT 17 17 APP_TG_LACT_LEVEL_INT_MAP_REG
PRO_TG1_T0_LEVEL_INT_MAP_REG 18 18 TG1_T0_LEVEL_INT 18 18 APP_TG1_T0_LEVEL_INT_MAP_REG
PRO_TG1_T1_LEVEL_INT_MAP_REG 19 19 TG1_T1_LEVEL_INT 19 19 APP_TG1_T1_LEVEL_INT_MAP_REG
PRO_TG1_WDT_LEVEL_INT_MAP_REG 20 20 TG1_WDT_LEVEL_INT 20 20 APP_TG1_WDT_LEVEL_INT_MAP_REG
PRO_TG1_LACT_LEVEL_INT_MAP_REG 21 21 TG1_LACT_LEVEL_INT 21 21 APP_TG1_LACT_LEVEL_INT_MAP_REG
33

PRO_GPIO_INTERRUPT_PRO_MAP_REG 22 22 GPIO_INTERRUPT_PRO GPIO_INTERRUPT_APP 22 22 APP_GPIO_INTERRUPT_APP_MAP_REG

PRO_GPIO_INTERRUPT_PRO_NMI_MAP_REG 23 23 GPIO_INTERRUPT_PRO_NMI GPIO_INTERRUPT_APP_NMI 23 23 APP_GPIO_INTERRUPT_APP_NMI_MAP_REG
PRO_CPU_INTR_FROM_CPU_0_MAP_REG 24 24 CPU_INTR_FROM_CPU_0 24 24 APP_CPU_INTR_FROM_CPU_0_MAP_REG
PRO_CPU_INTR_FROM_CPU_1_MAP_REG 25 25 CPU_INTR_FROM_CPU_1 25 25 APP_CPU_INTR_FROM_CPU_1_MAP_REG
PRO_CPU_INTR_FROM_CPU_2_MAP_REG 26 26 CPU_INTR_FROM_CPU_2 26 26 APP_CPU_INTR_FROM_CPU_2_MAP_REG
PRO_CPU_INTR_FROM_CPU_3_MAP_REG 27 27 CPU_INTR_FROM_CPU_3 27 27 APP_CPU_INTR_FROM_CPU_3_MAP_REG
PRO_SPI_INTR_0_MAP_REG 28 28 SPI_INTR_0 28 28 APP_SPI_INTR_0_MAP_REG
PRO_SPI_INTR_1_MAP_REG 29 29 SPI_INTR_1 29 29 APP_SPI_INTR_1_MAP_REG
PRO_SPI_INTR_2_MAP_REG 30 30 SPI_INTR_2 30 30 APP_SPI_INTR_2_MAP_REG
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PRO_SPI_INTR_3_MAP_REG 31 31 SPI_INTR_3 31 31 APP_SPI_INTR_3_MAP_REG

PRO_I2S0_INT_MAP_REG 0 32 I2S0_INT 32 0 APP_I2S0_INT_MAP_REG
PRO_I2S1_INT_MAP_REG 1 33 I2S1_INT 33 1 APP_I2S1_INT_MAP_REG
PRO_UART_INTR_MAP_REG 2 34 UART_INTR 34 2 APP_UART_INTR_MAP_REG
PRO_UART1_INTR_MAP_REG 3 35 UART1_INTR 35 3 APP_UART1_INTR_MAP_REG
PRO_UART2_INTR_MAP_REG 4 36 UART2_INTR 36 4 APP_UART2_INTR_MAP_REG
PRO_SDIO_HOST_INTERRUPT_MAP_REG 5 37 SDIO_HOST_INTERRUPT 37 5 APP_SDIO_HOST_INTERRUPT_MAP_REG
PRO_EMAC_INT_MAP_REG 6 38 EMAC_INT 38 6 APP_EMAC_INT_MAP_REG
PRO_PWM0_INTR_MAP_REG 7 39 PWM0_INTR 39 7 APP_PWM0_INTR_MAP_REG
PRO_PWM1_INTR_MAP_REG 8 40 PWM1_INTR 40 8 APP_PWM1_INTR_MAP_REG
PRO_PWM2_INTR_MAP_REG 9 41 PWM2_INTR 41 9 APP_PWM2_INTR_MAP_REG
PRO_PWM3_INTR_MAP_REG 10 PRO_INTR_STATUS_REG_1 42 PWM3_INTR 42 APP_INTR_STATUS_REG_1 10 APP_PWM3_INTR_MAP_REG
PRO_LEDC_INT_MAP_REG 11 43 LEDC_INT 43 11 APP_LEDC_INT_MAP_REG
PRO_EFUSE_INT_MAP_REG 12 44 EFUSE_INT 44 12 APP_EFUSE_INT_MAP_REG
PRO_CAN_INT_MAP_REG 13 45 CAN_INT 45 13 APP_CAN_INT_MAP_REG
PRO_RTC_CORE_INTR_MAP_REG 14 46 RTC_CORE_INTR 46 14 APP_RTC_CORE_INTR_MAP_REG
PRO_RMT_INTR_MAP_REG 15 47 RMT_INTR 47 15 APP_RMT_INTR_MAP_REG
PRO_PCNT_INTR_MAP_REG 16 48 PCNT_INTR 48 16 APP_PCNT_INTR_MAP_REG
PRO_I2C_EXT0_INTR_MAP_REG 17 49 I2C_EXT0_INTR 49 17 APP_I2C_EXT0_INTR_MAP_REG
PRO_I2C_EXT1_INTR_MAP_REG 18 50 I2C_EXT1_INTR 50 18 APP_I2C_EXT1_INTR_MAP_REG
PRO_RSA_INTR_MAP_REG 19 51 RSA_INTR 51 19 APP_RSA_INTR_MAP_REG
PRO_SPI1_DMA_INT_MAP_REG 20 52 SPI1_DMA_INT 52 20 APP_SPI1_DMA_INT_MAP_REG
 Espressif Systems

PRO_CPU APP_CPU

2. Interrupt Matrix
Peripheral Interrupt Source
Peripheral Interrupt Peripheral Interrupt
Status Register Status Register
Configuration Register No. Name No. Configuration Register
Bit Name Name Bit
PRO_SPI2_DMA_INT_MAP_REG 21 53 SPI2_DMA_INT 53 21 APP_SPI2_DMA_INT_MAP_REG
PRO_SPI3_DMA_INT_MAP_REG 22 54 SPI3_DMA_INT 54 22 APP_SPI3_DMA_INT_MAP_REG
PRO_WDG_INT_MAP_REG 23 55 WDG_INT 55 23 APP_WDG_INT_MAP_REG
PRO_TIMER_INT1_MAP_REG 24 56 TIMER_INT1 56 24 APP_TIMER_INT1_MAP_REG
PRO_TIMER_INT2_MAP_REG 25 57 TIMER_INT2 57 25 APP_TIMER_INT2_MAP_REG
PRO_TG_T0_EDGE_INT_MAP_REG 26 PRO_INTR_STATUS_REG_1 58 TG_T0_EDGE_INT 58 APP_INTR_STATUS_REG_1 26 APP_TG_T0_EDGE_INT_MAP_REG
PRO_TG_T1_EDGE_INT_MAP_REG 27 59 TG_T1_EDGE_INT 59 27 APP_TG_T1_EDGE_INT_MAP_REG
PRO_TG_WDT_EDGE_INT_MAP_REG 28 60 TG_WDT_EDGE_INT 60 28 APP_TG_WDT_EDGE_INT_MAP_REG
PRO_TG_LACT_EDGE_INT_MAP_REG 29 61 TG_LACT_EDGE_INT 61 29 APP_TG_LACT_EDGE_INT_MAP_REG
PRO_TG1_T0_EDGE_INT_MAP_REG 30 62 TG1_T0_EDGE_INT 62 30 APP_TG1_T0_EDGE_INT_MAP_REG
PRO_TG1_T1_EDGE_INT_MAP_REG 31 63 TG1_T1_EDGE_INT 63 31 APP_TG1_T1_EDGE_INT_MAP_REG
PRO_TG1_WDT_EDGE_INT_MAP_REG 0 64 TG1_WDT_EDGE_INT 64 0 APP_TG1_WDT_EDGE_INT_MAP_REG
PRO_TG1_LACT_EDGE_INT_MAP_REG 1 65 TG1_LACT_EDGE_INT 65 1 APP_TG1_LACT_EDGE_INT_MAP_REG
PRO_MMU_IA_INT_MAP_REG 2 PRO_INTR_STATUS_REG_2 66 MMU_IA_INT 66 APP_INTR_STATUS_REG_2 2 APP_MMU_IA_INT_MAP_REG
PRO_MPU_IA_INT_MAP_REG 3 67 MPU_IA_INT 67 3 APP_MPU_IA_INT_MAP_REG
PRO_CACHE_IA_INT_MAP_REG 4 68 CACHE_IA_INT 68 4 APP_CACHE_IA_INT_MAP_REG
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2. Interrupt Matrix

2.3.2 CPU Interrupt

Both of the two CPUs (PRO and APP) have 32 interrupts each, of which 26 are peripheral interrupts. All
interrupts in a CPU are listed in Table 8.

Table 8: CPU Interrupts

No. Category Type Priority Level

0 Peripheral Level-Triggered 1
1 Peripheral Level-Triggered 1
2 Peripheral Level-Triggered 1
3 Peripheral Level-Triggered 1
4 Peripheral Level-Triggered 1
5 Peripheral Level-Triggered 1
6 Internal Timer.0 1
7 Internal Software 1
8 Peripheral Level-Triggered 1
9 Peripheral Level-Triggered 1
10 Peripheral Edge-Triggered 1
11 Internal Profiling 3
12 Peripheral Level-Triggered 1
13 Peripheral Level-Triggered 1
14 Peripheral NMI NMI
15 Internal Timer.1 3
16 Internal Timer.2 5
17 Peripheral Level-Triggered 1
18 Peripheral Level-Triggered 1
19 Peripheral Level-Triggered 2
20 Peripheral Level-Triggered 2
21 Peripheral Level-Triggered 2
22 Peripheral Edge-Triggered 3
23 Peripheral Level-Triggered 3
24 Peripheral Level-Triggered 4
25 Peripheral Level-Triggered 4
26 Peripheral Level-Triggered 5
27 Peripheral Level-Triggered 3
28 Peripheral Edge-Triggered 4
29 Internal Software 3
30 Peripheral Edge-Triggered 4
31 Peripheral Level-Triggered 5

2.3.3 Allocate Peripheral Interrupt Sources to Peripheral Interrupt on CPU

In this section:

• Source_X stands for any particular peripheral interrupt source.

• PRO_X_MAP_REG (or APP_X_MAP_REG) stands for any particular peripheral interrupt configuration

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2. Interrupt Matrix

register of the PRO_CPU (or APP_CPU). The peripheral interrupt configuration register corresponds to the
peripheral interrupt source Source_X. In Table 7 the registers listed under “PRO_CPU (APP_CPU) -
Peripheral Interrupt Configuration Register” correspond to the peripheral interrupt sources listed in
“Peripheral Interrupt Source - Name”.

• Interrupt_P stands for CPU peripheral interrupt, numbered as Num_P. Num_P can take the ranges 0 ~ 5, 8
~ 10, 12 ~ 14, 17 ~ 28, 30 ~ 31.

• Interrupt_I stands for the CPU internal interrupt numbered as Num_I. Num_I can take values 6, 7, 11, 15,
16, 29.

Using this terminology, the possible operations of the Interrupt Matrix controller can be described as
follows:

• Allocate peripheral interrupt source Source_X to CPU (PRO_CPU or APP_CPU)

Set PRO_X_MAP_REG�or APP_X_MAP_REG�to Num_P. Num_P can be any CPU peripheral interrupt
number. CPU interrupts can be shared between multiple peripherals (see below).

• Disable peripheral interrupt source Source_X for CPU (PRO_CPU or APP_CPU)

Set PRO_X_MAP_REG�or APP_X _MAP_REG�for peripheral interrupt source to any Num_I. The specific
choice of internal interrupt number does not change behaviour, as none of the interrupt numbered as
Num_I is connected to either CPU.

• Allocate multiple peripheral sources Source_Xn ORed to PRO_CPU (APP_CPU) peripheral interrupt
Set multiple PRO_Xn_MAP_REG (APP_Xn_MAP_REG) to the same Num_P. Any of these peripheral
interrupts will trigger CPU Interrupt_P.

2.3.4 CPU NMI Interrupt Mask

The Interrupt Matrix temporarily masks all peripheral interrupt sources allocated to PRO_CPU’s ( or APP_CPU’s )
NMI interrupt, if it receives the signal PRO_CPU NMI Interrupt Mask ( or APP_CPU NMI Interrupt Mask ) from the
peripheral PID Controller, respectively.

2.3.5 Query Current Interrupt Status of Peripheral Interrupt Source

The current interrupt status of a peripheral interrupt source can be read via the bit value in
PRO_INTR_STATUS_REG_n (APP_INTR_STATUS_REG_n), as shown in the mapping in Table 7.

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3. Reset and Clock

3.1 System Reset

3.1.1 Introduction
The ESP32 has three reset levels: CPU reset, Core reset, and System reset. None of these reset levels clear the
RAM. Figure 5 shows the subsystems included in each reset level.

Figure 5: System Reset

• CPU reset: Only resets the registers of one or both of the CPU cores.

• Core reset: Resets all the digital registers, including CPU cores, external GPIO and digital GPIO. The RTC is
not reset.

• System reset: Resets all the registers on the chip, including those of the RTC.

3.1.2 Reset Source

While most of the time the APP_CPU and PRO_CPU will be reset simultaneously, some reset sources are able to
reset only one of the two cores. The reset reason for each core can be looked up individually: the PRO_CPU
reset reason will be stored in RTC_CNTL_RESET_CAUSE_PROCPU, the reset reason for the APP_CPU in
RTC_CNTL_RESET_CAUSE_APPCPU. Table 9 shows the possible reset reason values that can be read from
these registers.

Table 9: PRO_CPU and APP_CPU Reset Reason Values

PRO APP Source Reset Type Note

0x01 0x01 Chip Power On Reset System Reset -
0x10 0x10 RWDT System Reset System Reset See WDT Chapter.
0x0F 0x0F Brown Out Reset System Reset See Power Management Chapter.
0x03 0x03 Software System Reset Core Reset Configure RTC_CNTL_SW_SYS_RST register.
0x05 0x05 Deep Sleep Reset Core Reset See Power Management Chapter.

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3. Reset and Clock

PRO APP APP Source Reset Type Note

0x07 0x07 MWDT0 Global Reset Core Reset See WDT Chapter.
0x08 0x08 MWDT1 Global Reset Core Reset See WDT Chapter.
0x09 0x09 RWDT Core Reset Core Reset See WDT Chapter.
0x0B - MWDT0 CPU Reset CPU Reset See WDT Chapter.
0x0C - Software CPU Reset CPU Reset Configure RTC_CNTL_SW_APPCPU_RST register.
- 0x0B MWDT1 CPU Reset CPU Reset See WDT Chapter.
- 0x0C Software CPU Reset CPU Reset Configure RTC_CNTL_SW_APPCPU_RST register.
0x0D 0x0D RWDT CPU Reset CPU Reset See WDT Chapter.
Indicates that the PRO CPU has indepen-
- 0xE PRO CPU Reset CPU Reset dently reset the APP CPU by configuring the
DPORT_APPCPU_RESETTING register.

3.2 System Clock

3.2.1 Introduction
The ESP32 integrates multiple clock sources for the CPU cores, the peripherals and the RTC. These clocks can
be configured to meet different requirements. Figure 6 shows the system clock structure.

Figure 6: System Clock

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3.2.2 Clock Source

The ESP32 can use an external crystal oscillator, an internal PLL or an oscillating circuit as a clock source.
Specifically, the clock sources available are:

• High Speed Clocks

– PLL_CLK is an internal PLL clock with a frequency of 320 MHz.

– XTL_CLK is a clock signal generated using an external crystal with a frequency range of 2 ~ 40 MHz.

• Low Power Clocks

– XTL32K_CLK is a clock generated using an external crystal with a frequency of 32 KHz.

– RTC8M_CLK is an internal clock with a default frequency of 8 MHz. This frequency is adjustable.

– RTC8M_D256_CLK is divided from RTC8M_CLK 256. Its frequency is (RTC8M_CLK / 256). With the
default RTC8M_CLK frequency of 8 MHz, this clock runs at 31.250 KHz.

– RTC_CLK is an internal low power clock with a default frequency of 150 KHz. This frequency is
adjustable.

• Audio Clock

– APLL_CLK is an internal Audio PLL clock with a frequency range of 16 ~ 128 MHz.

3.2.3 CPU Clock

As Figure 6 shows, CPU_CLK is the master clock for both CPU cores. CPU_CLK clock can be as high as 160
MHz when the CPU is in high performance mode. Alternatively, the CPU can run at lower frequencies to reduce
power consumption.

The CPU_CLK clock source is determined by the RTC_CNTL_SOC_CLK_SEL register. PLL_CLK, APLL_CLK,
RTC8M_CLK and XTL_CLK can be set as the CPU_CLK source; see Table 10 and 11.

Table 10: CPU_CLK Source

RTC_CNTL_SOC_CLK_SEL Value Clock Source

0 XTL_CLK
1 PLL_CLK
2 RTC8M_CLK
3 APLL_CLK

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Table 11: CPU_CLK Derivation

Clock Source SEL* CPU Clock

CPU_CLK = XTL_CLK / (APB_CTRL_PRE_DIV_CNT+1)
0 / XTL_CLK -
APB_CTRL_PRE_DIV_CNT range is 0 ~ 1023. Default is 0.
CPU_CLK = PLL_CLK / 4
1 / PLL_CLK 0
CPU_CLK frequency is 80 MHz
CPU_CLK = PLL_CLK / 2
1 / PLL_CLK 1
CPU_CLK frequency is 160 MHz
CPU_CLK = RTC8M_CLK / (APB_CTRL_PRE_DIV_CNT+1)
2 / RTC8M_CLK -
APB_CTRL_PRE_DIV_CNT range is 0 ~ 1023. Default is 0.
3 / APLL_CLK 0 CPU_CLK = APLL_CLK / 4
3 / APLL_CLK 1 CPU_CLK = APLL_CLK / 2
*SEL: DPORT_CPUPERIOD _SEL value

3.2.4 Peripheral Clock

Peripheral clocks include APB_CLK, REF_TICK, LEDC_SCLK, APLL_CLK and PLL_D2_CLK.
Table 12 shows which clocks can be used by which peripherals.

Table 12: Peripheral Clock Usage

Peripherals APB_CLK REF_TICK LEDC_SCLK APLL_CLK PLL_D2_CLK

EMAC Y N N Y N
TIMG Y N N N N
I2S Y N N Y Y
UART Y Y N N N
RMT Y Y N N N
LED PWM Y Y Y N N
PWM Y N N N N
I2C Y N N N N
SPI Y N N N N
PCNT Y N N N N
Efuse Controller Y N N N N
SDIO Slave Y N N N N
SDMMC Y N N N N

3.2.4.1 APB_CLK Source

The APB_CLK is derived from CPU_CLK as detailed in Table 13. The division factor depends on the CPU_CLK
source.

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3. Reset and Clock

Table 13: APB_CLK Derivation

CPU_CLK Source APB_CLK

PLL_CLK PLL_CLK / 4
APLL_CLK CPU_CLK / 2
XTAL_CLK CPU_CLK
RTC8M_CLK CPU_CLK

3.2.4.2 REF_TICK Source

REF_TICK is derived from APB_CLK via a divider. The divider value used depends on the APB_CLK source,
which in turn depends on the CPU_CLK source.

By configuring correct divider values for each APB_CLK source, the user can ensure that the REF_TICK
frequency does not change when CPU_CLK changes source, causing the APB_CLK frequency to change.

Clock divider registers are shown in Table 14.

Table 14: REF_TICK Derivation

CPU_CLK & APB_CLK Source Clock Divider Register

PLL_CLK APB_CTRL_PLL_TICK_NUM
XTAL_CLK APB_CTRL_XTAL_TICK_NUM
APLL_CLK APB_CTRL_APLL_TICK_NUM
RTC8M_CLK APB_CTRL_CK8M_TICK_NUM

3.2.4.3 LEDC_SCLK Source

The LEDC_SCLK clock source is selected by the LEDC_APB_CLK_SEL register, as shown in Table 15.

Table 15: LEDC_SCLK Derivation

LEDC_APB_CLK_SEL Value LEDC_SCLK Source

0 RTC8M_CLK
1 APB_CLK

3.2.4.4 APLL_SCLK Source

The APLL_CLK is sourced from PLL_CLK, with its output frequency configured using the APLL configuration
registers.

3.2.4.5 PLL_D2_CLK Source

PLL_D2_CLK is half the PLL_CLK frequency.

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3.2.4.6 Clock Source Considerations

Most peripherals will operate using the APB_CLK frequency as a reference. When this frequency changes, the
peripherals will need to update their clock configuration to operate at the same frequency after the change.
Peripherals accessing REF_TICK can continue operating normally when switching clock sources, without
changing clock source. Please see Table 12 for details.

The LED PWM module can use RTC8M_CLK as a clock source when APB_CLK is disabled. In other words,
when the system is in low-power consumption mode (see Power Management Chapter), normal peripherals will
be halted (APB_CLK is turned off), but the LED PWM can work normally via RTC8M_CLK.

3.2.5 Wi-Fi BT Clock

Wi-Fi and BT can only operate if APB_CLK uses PLL_CLK as its clock source. Suspending PLL_CLK requires
Wi-Fi and BT to both have entered low-power consumption mode first.

For LOW_POWER_CLK, one of RTC_CLK, SLOW_CLK, RTC8M_CLK or XTL_CLK can be selected as the
low-power consumption mode clock source for Wi-Fi and BT.

3.2.6 RTC Clock

The clock sources of SLOW_CLK and FAST_CLK are low-frequency clocks. The RTC module can operate when
most other clocks are stopped.

SLOW_CLK is used to clock the Power Management module. It can be sourced from RTC_CLK, XTL32K_CLK
or RTC8M_D256_CLK

FAST_CLK is used to clock the On-chip Sensor module. It can be sourced from a divided XTL_CLK or from
RTC8M_CLK.

3.2.7 Audio PLL

The operation of audio and other time-critical data-transfer applications requires highly-configurable, low-jitter,
and accurate clock sources. The clock sources derived from system clocks that serve digital peripherals may
carry jitter and, therefore, they do not support a high-precision clock frequency setting.

Providing an integrated precision clock source can minimize system cost. To this end, ESP32 integrates an audio
PLL intended for I2S peripherals. More details on how to clock the I2S module, using an APLL clock, can be
found in Chapter I2S. The Audio PLL formula is as follows:

fxtal (sdm2 + sdm1

28
+ sdm0
216
+ 4)
fout =
2(odiv + 2)

The parameters of this formula are defined below:

• fxtal : the frequency of the crystal oscillator, usually 40 MHz;

• sdm0: the value is 0 ~ 255;

• sdm1: the value is 0 ~ 255;

• sdm2: the value is 0 ~ 63;

• odiv: the value is 0 ~ 31;

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3. Reset and Clock

The operating frequency range of the numerator is 350 MHz ~ 500 MHz:

sdm1 sdm0
350M Hz < fxtal (sdm2 + + 16 + 4) < 500M Hz
28 2

Please note that sdm1 and sdm0 are not available on revision0 of ESP32. Please consult the silicon revision in
ECO and Workarounds for Bugs in ESP32 for further details.

Audio PLL can be manually enabled or disabled via registers RTC_CNTL_PLLA_FORCE_PU and
RTC_CNTL_PLLA_FORCE_PD, respectively. Disabling it takes priority over enabling it. When
RTC_CNTL_PLLA_FORCE_PU and RTC_CNTL_PLLA_FORCE_PD are 0, PLL will follow the state of the system,
i.e., when the system enters sleep mode, PLL will be disabled automatically; when the system wakes up, PLL will
be enabled automatically.

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4. IO_MUX and GPIO Matrix

4. IO_MUX and GPIO Matrix

4.1 Overview
The ESP32 chip features 34 physical GPIO pads. Each pad can be used as a general-purpose I/O, or be
connected to an internal peripheral signal. The IO_MUX, RTC IO_MUX and the GPIO matrix are responsible for
routing signals from the peripherals to GPIO pads. Together these systems provide highly configurable I/O.

Note that the I/O GPIO pads are 0-19, 21-23, 25-27, 32-39, while the output GPIOs are 0-19, 21-23, 25-27,
32-33. GPIO pads 34-39 are input-only.

This chapter describes the signal selection and connection between the digital pads (FUN_SEL, IE, OE, WPU,
WDU, etc.), 162 peripheral input and 176 output signals (control signals: SIG_IN_SEL, SIG_OUT_SEL, IE, OE,
etc.), fast peripheral input/output signals (control signals: IE, OE, etc.), and RTC IO_MUX.

Figure 7: IO_MUX, RTC IO_MUX and GPIO Matrix Overview

1. The IO_MUX contains one register per GPIO pad. Each pad can be configured to perform a ”GPIO” function
(when connected to the GPIO Matrix) or a direct function (bypassing the GPIO Matrix). Some high-speed
digital functions (Ethernet, SDIO, SPI, JTAG, UART) can bypass the GPIO Matrix for better high-frequency
digital performance. In this case, the IO_MUX is used to connect these pads directly to the peripheral.)

See Section 4.10 for a list of IO_MUX functions for each I/O pad.

2. The GPIO Matrix is a full-switching matrix between the peripheral input/output signals and the pads.

• For input to the chip: Each of the 162 internal peripheral inputs can select any GPIO pad as the input
source.

• For output from the chip: The output signal of each of the 34 GPIO pads can be from one of the 176
peripheral output signals.

See Section 4.9 for a list of GPIO Matrix peripheral signals.

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4. IO_MUX and GPIO Matrix

3. RTC IO_MUX is used to connect GPIO pads to their low-power and analog functions. Only a subset of
GPIO pads have these optional ”RTC” functions.

See Section 4.11 for a list of RTC IO_MUX functions.

4.2 Peripheral Input via GPIO Matrix

4.2.1 Summary
To receive a peripheral input signal via the GPIO Matrix, the GPIO Matrix is configured to source the peripheral
signal’s input index (0-18, 23-36, 39-58, 61-90, 95-124, 140-155, 164-181, 190-195, 198-206) from one of the
34 GPIOs (0-19, 21-23, 25-27, 32-39).

The input signal is read from the GPIO pad through the IO_MUX. The IO_MUX must be configured to set the
chosen pad to ”GPIO” function. This causes the GPIO pad input signal to be routed into the GPIO Matrix, which
in turn routes it to the selected peripheral input.

4.2.2 Functional Description

Figure 8 shows the logic for input selection via GPIO Matrix.

In GPIO matrix In IO MUX

GPIO_FUNCy_IN_SEL

MCU_SEL
GPIO0_in
0
GPIO1_in GPIO_SIGxx_IN_SEL
1
GPIO2_in
2
GPIO3_in 0 (FUNC)
3
0 1 (FUNC) I/O Pad X
GPIOX_in GPIO X in 2 (GPIO)
Peripheral Signal Y X 1 (GPIO)

GPIO39_in
39

FUN_IE = 1
Constant 0 input
(0x30)48
Constant 1 input
(0x38)56

Figure 8: Peripheral Input via IO_MUX, GPIO Matrix

To read GPIO pad X into peripheral signal Y, follow the steps below:

1. Configure the GPIO_FUNCy_IN_SEL_CFG register corresponding to peripheral signal Y in the GPIO Matrix:

• Set the GPIO_FUNCx_IN_SEL field in this register, corresponding to the GPIO pad X to read from.
Clear all other fields corresponding to other GPIO pads.

2. Configure the GPIO_FUNCx_OUT_SEL_CFG register and clear the GPIO_ENABLE_DATA[x] field

corresponding to GPIO pad X in the GPIO Matrix:

• Set the GPIO_FUNCx_OEN_SEL bit in the GPIO_FUNCx_OUT_SEL_CFG register to force the pin’s
output state to be determined always by the GPIO_ENABLE_DATA[x] field.

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• The GPIO_ENABLE_DATA[x] field is a bit in either GPIO_ENABLE_REG (GPIOs 0-31) or

GPIO_ENABLE1_REG (GPIOs 32-39). Clear this bit to disable the output driver for the GPIO pad.

3. Configure the IO_MUX to select the GPIO Matrix. Set the IO_MUX_x_REG register corresponding to GPIO
pad X as follows:

• Set the function field (MCU_SEL) to the IO_MUX function corresponding to GPIO X (this is Function
#3—numeric value 2—for all pins).

• Enable the input by setting the FUN_IE bit.

• Set or clear the FUN_WPU and FUN_WPD bits, as desired, to enable/disable internal
pull-up/pull-down resistors.

Notes:

• One input pad can be connected to multiple input_signals.

• The input signal can be inverted with GPIO_FUNCx_IN_INV_SEL.

• It is possible to have a peripheral read a constantly low or constantly high input value without connecting
this input to a pad. This can be done by selecting a special GPIO_FUNCy_IN_SEL input, instead of a GPIO
number:

– When GPIO_FUNCx_IN_SEL is 0x30, input_signal_x is always 0.

– When GPIO_FUNCx_IN_SEL is 0x38, input_signal_x is always 1.

For example, to connect RMT peripheral channel 0 input signal (RMT_SIG_IN0_IDX, signal index 83) to GPIO 15,
please follow the steps below. Note that GPIO 15 is also named the MTDO pin:

1. Set the GPIO_FUNC83_IN_SEL_CFG register field GPIO_FUNC83_IN_SEL value to 15.

2. As this is an input-only signal, set GPIO_FUNC15_OEN_SEL bit in GPIO_FUNC15_OUT_SEL_CFG_REG.

3. Clear bit 15 of GPIO_ENABLE_REG (field GPIO_ENABLE_DATA[15]).

4. Set the IO_MUX_GPIO15 register MCU_SEL field to 2 (GPIO function) and also set the FUN_IE bit (input
mode).

4.2.3 Simple GPIO Input

The GPIO_IN_REG/GPIO_IN1_REG register holds the input values of each GPIO pad.

The input value of any GPIO pin can be read at any time without configuring the GPIO Matrix for a particular
peripheral signal. However, it is necessary to enable the input in the IO_MUX by setting the FUN_IE bit in the
IO_MUX_x_REG register corresponding to pad X, as mentioned in Section 4.2.2.

4.3 Peripheral Output via GPIO Matrix

4.3.1 Summary
To output a signal from a peripheral via the GPIO Matrix, the GPIO Matrix is configured to route the peripheral
output signal (0-18, 23-37, 61-121, 140-125, 224-228) to one of the 28 GPIOs (0-19, 21-23, 25-27,
32-33).

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The output signal is routed from the peripheral into the GPIO Matrix. It is then routed into the IO_MUX, which is
configured to set the chosen pad to ”GPIO” function. This causes the output GPIO signal to be connected to the
pad.

Note:
The peripheral output signals 224 to 228 can be configured to be routed in from one GPIO and output directly from another
GPIO.

4.3.2 Functional Description

One of the 176 output signals can be selected to go through the GPIO matrix into the IO_MUX and then to a pad.
Figure 9 illustrates the configuration.

In GPIO matrix In IO MUX

GPIO_FUNCx_OUT_SEL

signal0_out 0 MCU_SEL
signal1_out 1
signal2_out 2
signal3_out 3

0 (FUNC)
1 (FUNC)
GPIO X out I/O Pad x
2 (GPIO)
GPIOx_out
signal228_out 228

FUN_OE = 1
GPIO_OUT_DATA bit x 256 (0x100)
256sdfsdfasdfgas

Figure 9: Output via GPIO Matrix

To output peripheral signal Y to particular GPIO pad X, follow these steps:

1. Configure the GPIO_FUNCx_OUT_SEL_CFG register and GPIO_ENABLE_DATA[x] field corresponding to

GPIO X in the GPIO Matrix:

• Set the GPIO_FUNCx_OUT_SEL field in GPIO_FUNCx_OUT_SEL_CFG to the numeric index (Y) of

desired peripheral output signal Y.

• If the signal should always be enabled as an output, set the GPIO_FUNCx_OEN_SEL bit in the
GPIO_FUNCx_OUT_SEL_CFG register and the GPIO_ENABLE_DATA[x] field in the
GPIO_ENABLE_REG register corresponding to GPIO pad X. To have the output enable signal decided
by internal logic, clear the GPIO_FUNCx_OEN_SEL bit instead.

• The GPIO_ENABLE_DATA[x] field is a bit in either GPIO_ENABLE_REG (GPIOs 0-31) or

GPIO_ENABLE1_REG (GPIOs 32-39). Clear this bit to disable the output driver for the GPIO pad.

2. For an open drain output, set the GPIO_PINx_PAD_DRIVER bit in the GPIO_PINx register corresponding to
GPIO pad X. For push/pull mode (default), clear this bit.

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3. Configure the IO_MUX to select the GPIO Matrix. Set the IO_MUX_x_REG register corresponding to GPIO
pad X as follows:

• Set the function field (MCU_SEL) to the IO_MUX function corresponding to GPIO X (this is Function
#3—numeric value 2—for all pins).

• Set the FUN_DRV field to the desired value for output strength (0-3). The higher the drive strength, the
more current can be sourced/sunk from the pin.

• If using open drain mode, set/clear the FUN_WPU and FUN_WPD bits to enable/disable the internal
pull-up/down resistors.

Notes:

• The output signal from a single peripheral can be sent to multiple pads simultaneously.

• Only the 28 GPIOs can be used as outputs.

• The output signal can be inverted by setting the GPIO_FUNCx_OUT_INV_SEL bit.

4.3.3 Simple GPIO Output

The GPIO Matrix can also be used for simple GPIO output – setting a bit in the GPIO_OUT_DATA register will
write to the corresponding GPIO pad.

To configure a pad as simple GPIO output, the GPIO Matrix GPIO_FUNCx_OUT_SEL register is configured with a
special peripheral index value (0x100).

4.4 Direct I/O via IO_MUX

4.4.1 Summary
Some high speed digital functions (Ethernet, SDIO, SPI, JTAG, UART) can bypass the GPIO Matrix for better
high-frequency digital performance. In this case, the IO_MUX is used to connect these pads directly to the
peripheral.

Selecting this option is less flexible than using the GPIO Matrix, as the IO_MUX register for each GPIO pad can
only select from a limited number of functions. However, better high-frequency digital performance will be
maintained.

4.4.2 Functional Description

Two registers must be configured in order to bypass the GPIO Matrix for peripheral I/O:

1. IO_MUX for the GPIO pad must be set to the required pad function. (Please refer to section 4.10 for a list of
pad functions.)

2. For inputs, the SIG_IN_SEL register must be set to route the input directly to the peripheral.

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4.5 RTC IO_MUX for Low Power and Analog I/O

4.5.1 Summary
18 GPIO pads have low power capabilities (RTC domain) and analog functions which are handled by the RTC
subsystem of ESP32. The IO_MUX and GPIO Matrix are not used for these functions; rather, the RTC_MUX is
used to redirect the I/O to the RTC subsystem.

When configured as RTC GPIOs, the output pads can still retain the output level value when the chip is in
Deep-sleep mode, and the input pads can wake up the chip from Deep-sleep.

Section 4.11 has a list of RTC_MUX pins and their functions.

4.5.2 Functional Description

Each pad with analog and RTC functions is controlled by the RTC_IO_TOUCH_PADx_TO_GPIO bit in the
RTC_GPIO_PINx register. By default this bit is set to 1, routing all I/O via the IO_MUX subsystem as described in
earlier subsections.

If the RTC_IO_TOUCH_PADx_TO_GPIO bit is cleared, then I/O to and from that pad is routed to the RTC
subsystem. In this mode, the RTC_GPIO_PINx register is used for digital I/O and the analog features of the pad
are also available. See Section 4.11 for a list of RTC pin functions.

See 4.11 for a table mapping GPIO pads to their RTC equivalent pins and analog functions. Note that the
RTC_IO_PINx registers use the RTC GPIO pin numbering, not the GPIO pad numbering.

4.6 Light-sleep Mode Pin Functions

Pins can have different functions when the ESP32 is in Light-sleep mode. If the SLP_SEL bit in the IO_MUX
register for a GPIO pad is set to 1, a different set of registers is used to control the pad when the ESP32 is in
Light-sleep mode:

Table 16: IO_MUX Light-sleep Pin Function Registers

Normal Execution Light-sleep Mode

IO_MUX Function
OR SLP_SEL = 0 AND SLP_SEL = 1
Output Drive Strength FUN_DRV MCU_DRV
Pullup Resistor FUN_WPU MCU_WPU
Pulldown Resistor FUN_WPD MCU_WPD
Output Enable (From GPIO Matrix _OEN field) MCU_OE

If SLP_SEL is set to 0, the pin functions remain the same in both normal execution and Light-sleep mode.

4.7 Pad Hold Feature

Each IO pad (including the RTC pads) has an individual hold function controlled by a RTC register. When the pad
is set to hold, the state is latched at that moment and will not change no matter how the internal signals change
or how the IO_MUX configuration or GPIO configuration is modified. Users can use the hold function for the pads

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to retain the pad state through a core reset and system reset triggered by watchdog time-out or Deep-sleep
events.

Note:

• For digital pads, to maintain the pad’s input/output status in Deep-sleep mode, you can set
REG_DG_PAD_FORCE_UNHOLD to 0 before powering down.
For RTC pads, the input and output values are controlled by the corresponding bits of register
RTC_CNTL_HOLD_FORCE_REG, and you can set it to 1 to hold the value or set it to 0 to unhold the value.

• For digital pads, to disable the hold function after the chip is woken up, you can set REG_DG_PAD_FORCE_UNHOLD
to 1. To maintain the hold function of the pad, you can change the corresponding bit in the register by setting
RTC_CNTL_HOLD_FORCE_REG to 1.

4.8 I/O Pad Power Supplies

Figure 10 and 11 show the IO pad power supplies.
VDD3P3_CPU
GPIO21

GPIO22

GPIO19
XTAL_N
XTAL_P

U0RXD
U0TXD
VDDA

VDDA
CAP1

CAP2
48

47

46

45

44

43

42

41

40

39

38

37

VDDA 1 36 GPIO23

LNA_IN 2 35 GPIO18

VDD3P3 3 34 GPIO5

VDD3P3 4 33 SD_DATA_1

SENSOR_VP 5 32 SD_DATA_0

SENSOR_CAPP 6 ESP32 31 SD_CLK

SENSOR_CAPN 7 49 GND 30 SD_CMD

SENSOR_VN 8 29 SD_DATA_3

CHIP_PU 9 28 SD_DATA_2

VDET_1 10 27 GPIO17

VDET_2 11 26 VDD_SDIO

32K_XP 12 25 GPIO16
13

14

15

16

17

18

19

20

21

22

23

24

Analog pads
32K_XN

GPIO25

GPIO26

GPIO27

MTMS

MTDI

VDD3P3_RTC

MTCK

MTDO

GPIO2

GPIO0

GPIO4

Pads powered by VDD3P3_CPU

Pads powered by VDD_SDIO

Pads powered by VDD3P3_RTC

Figure 10: ESP32 I/O Pad Power Sources (QFN 6*6, Top View)

• Pads marked blue are RTC pads that have their individual analog function and can also act as normal
digital IO pads. For details, please see Section 4.11.

• Pads marked yellow and green have digital functions only.

• Pads marked green can be powered externally or internally via VDD_SDIO (see below).

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GPIO21

GPIO22
XTAL_N
XTAL_P

U0RXD
U0TXD
VDDA

VDDA
CAP1

CAP2
48

47

46

45

44

43

42

41

40

39
VDDA 1 38 GPIO19

LNA_IN 2 37 VDD3P3_CPU

VDD3P3 3 36 GPIO23

VDD3P3 4 35 GPIO18

SENSOR_VP 5 34 GPIO5

SENSOR_CAPP 6 33 SD_DATA_1

SENSOR_CAPN 7 32 SD_DATA_0
ESP32
49 GND
SENSOR_VN 8 31 SD_CLK

CHIP_PU 9 30 SD_CMD

VDET_1 10 29 SD_DATA_3

VDET_2 11 28 SD_DATA_2

32K_XP 12 27 GPIO17

32K_XN 13 26 VDD_SDIO

GPIO25 14 25 GPIO16
15

16

17

18

19

20

21

22

23

24
Analog pads
GPIO26

GPIO27

MTMS

MTDI

VDD3P3_RTC

MTCK

MTDO

GPIO2

GPIO0

GPIO4 Pads powered by VDD3P3_CPU

Pads powered by VDD_SDIO

Pads powered by VDD3P3_RTC

Figure 11: ESP32 I/O Pad Power Sources (QFN 5*5, Top View)

4.8.1 VDD_SDIO Power Domain

VDD_SDIO can source or sink current, allowing this power domain to be powered externally or internally. To
power VDD_SDIO externally, apply the same power supply of VDD3P3_RTC to the VDD_SDIO pad.

Without an external power supply, the internal regulator will supply VDD_SDIO. The VDD_SDIO voltage can be
configured to be either 1.8V or the same as VDD3P3_RTC, depending on the state of the MTDI pad at reset – a
high level configures 1.8V and a low level configures the voltage to be the same as VDD3P3_RTC. Setting the
efuse bit determines the default voltage of the VDD_SDIO. In addition, software can change the voltage of the
VDD_SDIO by configuring register bits.

4.9 Peripheral Signal List

Table 17 contains a list of Peripheral Input/Output signals used by the GPIO Matrix:

Table 17: GPIO Matrix Peripheral Signals

Signal Input Signal Output Signal Direct I/O in IO_MUX

0 SPICLK_in SPICLK_out YES
1 SPIQ_in SPIQ_out YES
2 SPID_in SPID_out YES
3 SPIHD_in SPIHD_out YES
4 SPIWP_in SPIWP_out YES

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Signal Input Signal Output Signal Direct I/O in IO_MUX

5 SPICS0_in SPICS0_out YES
6 SPICS1_in SPICS1_out -
7 SPICS2_in SPICS2_out -
8 HSPICLK_in HSPICLK_out YES
9 HSPIQ_in HSPIQ_out YES
10 HSPID_in HSPID_out YES
11 HSPICS0_in HSPICS0_out YES
12 HSPIHD_in HSPIHD_out YES
13 HSPIWP_in HSPIWP_out YES
14 U0RXD_in U0TXD_out YES
15 U0CTS_in U0RTS_out YES
16 U0DSR_in U0DTR_out -
17 U1RXD_in U1TXD_out YES
18 U1CTS_in U1RTS_out YES
23 I2S0O_BCK_in I2S0O_BCK_out -
24 I2S1O_BCK_in I2S1O_BCK_out -
25 I2S0O_WS_in I2S0O_WS_out -
26 I2S1O_WS_in I2S1O_WS_out -
27 I2S0I_BCK_in I2S0I_BCK_out -
28 I2S0I_WS_in I2S0I_WS_out -
29 I2CEXT0_SCL_in I2CEXT0_SCL_out -
30 I2CEXT0_SDA_in I2CEXT0_SDA_out -
31 pwm0_sync0_in sdio_tohost_int_out -
32 pwm0_sync1_in pwm0_out0a -
33 pwm0_sync2_in pwm0_out0b -
34 pwm0_f0_in pwm0_out1a -
35 pwm0_f1_in pwm0_out1b -
36 pwm0_f2_in pwm0_out2a -
37 - pwm0_out2b -
39 pcnt_sig_ch0_in0 - -
40 pcnt_sig_ch1_in0 - -
41 pcnt_ctrl_ch0_in0 - -
42 pcnt_ctrl_ch1_in0 - -
43 pcnt_sig_ch0_in1 - -
44 pcnt_sig_ch1_in1 - -
45 pcnt_ctrl_ch0_in1 - -
46 pcnt_ctrl_ch1_in1 - -
47 pcnt_sig_ch0_in2 - -
48 pcnt_sig_ch1_in2 - -
49 pcnt_ctrl_ch0_in2 - -
50 pcnt_ctrl_ch1_in2 - -
51 pcnt_sig_ch0_in3 - -
52 pcnt_sig_ch1_in3 - -

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Signal Input Signal Output Signal Direct I/O in IO_MUX

53 pcnt_ctrl_ch0_in3 - -
54 pcnt_ctrl_ch1_in3 - -
55 pcnt_sig_ch0_in4 - -
56 pcnt_sig_ch1_in4 - -
57 pcnt_ctrl_ch0_in4 - -
58 pcnt_ctrl_ch1_in4 - -
61 HSPICS1_in HSPICS1_out -
62 HSPICS2_in HSPICS2_out -
63 VSPICLK_in VSPICLK_out_mux YES
64 VSPIQ_in VSPIQ_out YES
65 VSPID_in VSPID_out YES
66 VSPIHD_in VSPIHD_out YES
67 VSPIWP_in VSPIWP_out YES
68 VSPICS0_in VSPICS0_out YES
69 VSPICS1_in VSPICS1_out -
70 VSPICS2_in VSPICS2_out -
71 pcnt_sig_ch0_in5 ledc_hs_sig_out0 -
72 pcnt_sig_ch1_in5 ledc_hs_sig_out1 -
73 pcnt_ctrl_ch0_in5 ledc_hs_sig_out2 -
74 pcnt_ctrl_ch1_in5 ledc_hs_sig_out3 -
75 pcnt_sig_ch0_in6 ledc_hs_sig_out4 -
76 pcnt_sig_ch1_in6 ledc_hs_sig_out5 -
77 pcnt_ctrl_ch0_in6 ledc_hs_sig_out6 -
78 pcnt_ctrl_ch1_in6 ledc_hs_sig_out7 -
79 pcnt_sig_ch0_in7 ledc_ls_sig_out0 -
80 pcnt_sig_ch1_in7 ledc_ls_sig_out1 -
81 pcnt_ctrl_ch0_in7 ledc_ls_sig_out2 -
82 pcnt_ctrl_ch1_in7 ledc_ls_sig_out3 -
83 rmt_sig_in0 ledc_ls_sig_out4 -
84 rmt_sig_in1 ledc_ls_sig_out5 -
85 rmt_sig_in2 ledc_ls_sig_out6 -
86 rmt_sig_in3 ledc_ls_sig_out7 -
87 rmt_sig_in4 rmt_sig_out0 -
88 rmt_sig_in5 rmt_sig_out1 -
89 rmt_sig_in6 rmt_sig_out2 -
90 rmt_sig_in7 rmt_sig_out3 -
91 - rmt_sig_out4 -
92 - rmt_sig_out5 -
93 - rmt_sig_out6 -
94 - rmt_sig_out7 -
95 I2CEXT1_SCL_in I2CEXT1_SCL_out -
96 I2CEXT1_SDA_in I2CEXT1_SDA_out -
97 host_card_detect_n_1 host_ccmd_od_pullup_en_n -

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Signal Input Signal Output Signal Direct I/O in IO_MUX

98 host_card_detect_n_2 host_rst_n_1 -
99 host_card_write_prt_1 host_rst_n_2 -
100 host_card_write_prt_2 gpio_sd0_out -
101 host_card_int_n_1 gpio_sd1_out -
102 host_card_int_n_2 gpio_sd2_out -
103 pwm1_sync0_in gpio_sd3_out -
104 pwm1_sync1_in gpio_sd4_out -
105 pwm1_sync2_in gpio_sd5_out -
106 pwm1_f0_in gpio_sd6_out -
107 pwm1_f1_in gpio_sd7_out -
108 pwm1_f2_in pwm1_out0a -
109 pwm0_cap0_in pwm1_out0b -
110 pwm0_cap1_in pwm1_out1a -
111 pwm0_cap2_in pwm1_out1b -
112 pwm1_cap0_in pwm1_out2a -
113 pwm1_cap1_in pwm1_out2b -
114 pwm1_cap2_in pwm2_out1h -
115 pwm2_flta pwm2_out1l -
116 pwm2_fltb pwm2_out2h -
117 pwm2_cap1_in pwm2_out2l -
118 pwm2_cap2_in pwm2_out3h -
119 pwm2_cap3_in pwm2_out3l -
120 pwm3_flta pwm2_out4h -
121 pwm3_fltb pwm2_out4l -
122 pwm3_cap1_in - -
123 pwm3_cap2_in - -
124 pwm3_cap3_in - -
140 I2S0I_DATA_in0 I2S0O_DATA_out0 -
141 I2S0I_DATA_in1 I2S0O_DATA_out1 -
142 I2S0I_DATA_in2 I2S0O_DATA_out2 -
143 I2S0I_DATA_in3 I2S0O_DATA_out3 -
144 I2S0I_DATA_in4 I2S0O_DATA_out4 -
145 I2S0I_DATA_in5 I2S0O_DATA_out5 -
146 I2S0I_DATA_in6 I2S0O_DATA_out6 -
147 I2S0I_DATA_in7 I2S0O_DATA_out7 -
148 I2S0I_DATA_in8 I2S0O_DATA_out8 -
149 I2S0I_DATA_in9 I2S0O_DATA_out9 -
150 I2S0I_DATA_in10 I2S0O_DATA_out10 -
151 I2S0I_DATA_in11 I2S0O_DATA_out11 -
152 I2S0I_DATA_in12 I2S0O_DATA_out12 -
153 I2S0I_DATA_in13 I2S0O_DATA_out13 -
154 I2S0I_DATA_in14 I2S0O_DATA_out14 -
155 I2S0I_DATA_in15 I2S0O_DATA_out15 -

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Signal Input Signal Output Signal Direct I/O in IO_MUX

156 - I2S0O_DATA_out16 -
157 - I2S0O_DATA_out17 -
158 - I2S0O_DATA_out18 -
159 - I2S0O_DATA_out19 -
160 - I2S0O_DATA_out20 -
161 - I2S0O_DATA_out21 -
162 - I2S0O_DATA_out22 -
163 - I2S0O_DATA_out23 -
164 I2S1I_BCK_in I2S1I_BCK_out -
165 I2S1I_WS_in I2S1I_WS_out -
166 I2S1I_DATA_in0 I2S1O_DATA_out0 -
167 I2S1I_DATA_in1 I2S1O_DATA_out1 -
168 I2S1I_DATA_in2 I2S1O_DATA_out2 -
169 I2S1I_DATA_in3 I2S1O_DATA_out3 -
170 I2S1I_DATA_in4 I2S1O_DATA_out4 -
171 I2S1I_DATA_in5 I2S1O_DATA_out5 -
172 I2S1I_DATA_in6 I2S1O_DATA_out6 -
173 I2S1I_DATA_in7 I2S1O_DATA_out7 -
174 I2S1I_DATA_in8 I2S1O_DATA_out8 -
175 I2S1I_DATA_in9 I2S1O_DATA_out9 -
176 I2S1I_DATA_in10 I2S1O_DATA_out10 -
177 I2S1I_DATA_in11 I2S1O_DATA_out11 -
178 I2S1I_DATA_in12 I2S1O_DATA_out12 -
179 I2S1I_DATA_in13 I2S1O_DATA_out13 -
180 I2S1I_DATA_in14 I2S1O_DATA_out14 -
181 I2S1I_DATA_in15 I2S1O_DATA_out15 -
182 - I2S1O_DATA_out16 -
183 - I2S1O_DATA_out17 -
184 - I2S1O_DATA_out18 -
185 - I2S1O_DATA_out19 -
186 - I2S1O_DATA_out20 -
187 - I2S1O_DATA_out21 -
188 - I2S1O_DATA_out22 -
189 - I2S1O_DATA_out23 -
190 I2S0I_H_SYNC pwm3_out1h -
191 I2S0I_V_SYNC pwm3_out1l -
192 I2S0I_H_ENABLE pwm3_out2h -
193 I2S1I_H_SYNC pwm3_out2l -
194 I2S1I_V_SYNC pwm3_out3h -
195 I2S1I_H_ENABLE pwm3_out3l -
196 - pwm3_out4h -
197 - pwm3_out4l -
198 U2RXD_in U2TXD_out YES

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Signal Input Signal Output Signal Direct I/O in IO_MUX

199 U2CTS_in U2RTS_out YES
200 emac_mdc_i emac_mdc_o -
201 emac_mdi_i emac_mdo_o -
202 emac_crs_i emac_crs_o -
203 emac_col_i emac_col_o -
204 pcmfsync_in bt_audio0_irq -
205 pcmclk_in bt_audio1_irq -
206 pcmdin bt_audio2_irq -
207 - ble_audio0_irq -
208 - ble_audio1_irq -
209 - ble_audio2_irq -
210 - pcmfsync_out -
211 - pcmclk_out -
212 - pcmdout -
213 - ble_audio_sync0_p -
214 - ble_audio_sync1_p -
215 - ble_audio_sync2_p -
224 - sig_in_func224 -
225 - sig_in_func225 -
226 - sig_in_func226 -
227 - sig_in_func227 -
228 - sig_in_func228 -

Direct I/O in IO_MUX ”YES” means that this signal is also available directly via IO_MUX. To apply the GPIO
Matrix to these signals, their corresponding SIG_IN_SEL register must be cleared.

4.10 IO_MUX Pad List

Table 18 shows the IO_MUX functions for each I/O pad:

Table 18: IO_MUX Pad Summary

GPIO Pad Name Function 1 Function 2 Function 3 Function 4 Function 5 Function 6 Reset Notes
0 GPIO0 GPIO0 CLK_OUT1 GPIO0 - - EMAC_TX_CLK 3 R
1 U0TXD U0TXD CLK_OUT3 GPIO1 - - EMAC_RXD2 3 -
2 GPIO2 GPIO2 HSPIWP GPIO2 HS2_DATA0 SD_DATA0 - 2 R
3 U0RXD U0RXD CLK_OUT2 GPIO3 - - - 3 -
4 GPIO4 GPIO4 HSPIHD GPIO4 HS2_DATA1 SD_DATA1 EMAC_TX_ER 2 R
5 GPIO5 GPIO5 VSPICS0 GPIO5 HS1_DATA6 - EMAC_RX_CLK 3 -
6 SD_CLK SD_CLK SPICLK GPIO6 HS1_CLK U1CTS - 3 -
7 SD_DATA_0 SD_DATA0 SPIQ GPIO7 HS1_DATA0 U2RTS - 3 -
8 SD_DATA_1 SD_DATA1 SPID GPIO8 HS1_DATA1 U2CTS - 3 -
9 SD_DATA_2 SD_DATA2 SPIHD GPIO9 HS1_DATA2 U1RXD - 3 -
10 SD_DATA_3 SD_DATA3 SPIWP GPIO10 HS1_DATA3 U1TXD - 3 -
11 SD_CMD SD_CMD SPICS0 GPIO11 HS1_CMD U1RTS - 3 -
12 MTDI MTDI HSPIQ GPIO12 HS2_DATA2 SD_DATA2 EMAC_TXD3 2 R
13 MTCK MTCK HSPID GPIO13 HS2_DATA3 SD_DATA3 EMAC_RX_ER 1 R
14 MTMS MTMS HSPICLK GPIO14 HS2_CLK SD_CLK EMAC_TXD2 1 R

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GPIO Pad Name Function 1 Function 2 Function 3 Function 4 Function 5 Function 6 Reset Notes
15 MTDO MTDO HSPICS0 GPIO15 HS2_CMD SD_CMD EMAC_RXD3 3 R
16 GPIO16 GPIO16 - GPIO16 HS1_DATA4 U2RXD EMAC_CLK_OUT 1 -
17 GPIO17 GPIO17 - GPIO17 HS1_DATA5 U2TXD EMAC_CLK_180 1 -
18 GPIO18 GPIO18 VSPICLK GPIO18 HS1_DATA7 - - 1 -
19 GPIO19 GPIO19 VSPIQ GPIO19 U0CTS - EMAC_TXD0 1 -
21 GPIO21 GPIO21 VSPIHD GPIO21 - - EMAC_TX_EN 1 -
22 GPIO22 GPIO22 VSPIWP GPIO22 U0RTS - EMAC_TXD1 1 -
23 GPIO23 GPIO23 VSPID GPIO23 HS1_STROBE - - 1 -
25 GPIO25 GPIO25 - GPIO25 - - EMAC_RXD0 0 R
26 GPIO26 GPIO26 - GPIO26 - - EMAC_RXD1 0 R
27 GPIO27 GPIO27 - GPIO27 - - EMAC_RX_DV 1 R
32 32K_XP GPIO32 - GPIO32 - - - 0 R
33 32K_XN GPIO33 - GPIO33 - - - 0 R
34 VDET_1 GPIO34 - GPIO34 - - - 0 R, I
35 VDET_2 GPIO35 - GPIO35 - - - 0 R, I
36 SENSOR_VP GPIO36 - GPIO36 - - - 0 R, I
37 SENSOR_CAPP GPIO37 - GPIO37 - - - 0 R, I
38 SENSOR_CAPN GPIO38 - GPIO38 - - - 0 R, I
39 SENSOR_VN GPIO39 - GPIO39 - - - 0 R, I

Reset Configurations

”Reset” column shows each pad’s default configurations after reset:

• 0 - IE=0 (input disabled).

• 1 - IE=1 (input enabled).

• 2 - IE=1, WPD=1 (input enabled, pulldown resistor).

• 3 - IE=1, WPU=1 (input enabled, pullup resistor).

Notes

• R - Pad has RTC/analog functions via RTC_MUX.

• I - Pad can only be configured as input GPIO.

Please refer to the ESP32 Pin Lists in ESP32 Datasheet for more details.

4.11 RTC_MUX Pin List

Table 19 shows the RTC pins and how they correspond to GPIO pads:

Table 19: RTC_MUX Pin Summary

Analog Function RTC Function

RTC GPIO Num GPIO Num Pad Name Function 1 Function 2
1 2 3
(FUN_SEL = 0) (FUN_SEL = 3)
0 36 SENSOR_VP ADC_H ADC1_CH0 - RTC_GPIO0 -
1 37 SENSOR_CAPP ADC_H ADC1_CH1 - RTC_GPIO1 -
2 38 SENSOR_CAPN ADC_H ADC1_CH2 - RTC_GPIO2 -
3 39 SENSOR_VN ADC_H ADC1_CH3 - RTC_GPIO3 -
4 34 VDET_1 - ADC1_CH6 - RTC_GPIO4 -
5 35 VDET_2 - ADC1_CH7 - RTC_GPIO5 -

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Analog Function RTC Function

RTC GPIO Num GPIO Num Pad Name Function 1 Function 2
1 2 3
(FUN_SEL = 0) (FUN_SEL = 3)
6 25 GPIO25 DAC_1 ADC2_CH8 - RTC_GPIO6 -
7 26 GPIO26 DAC_2 ADC2_CH9 - RTC_GPIO7 -
8 33 32K_XN XTAL_32K_N ADC1_CH5 TOUCH8 RTC_GPIO8 -
9 32 32K_XP XTAL_32K_P ADC1_CH4 TOUCH9 RTC_GPIO9 -
10 4 GPIO4 - ADC2_CH0 TOUCH0 RTC_GPIO10 I2C_SCL
11 0 GPIO0 - ADC2_CH1 TOUCH1 RTC_GPIO11 I2C_SDA
12 2 GPIO2 - ADC2_CH2 TOUCH2 RTC_GPIO12 I2C_SCL
13 15 MTDO - ADC2_CH3 TOUCH3 RTC_GPIO13 I2C_SDA
14 13 MTCK - ADC2_CH4 TOUCH4 RTC_GPIO14 -
15 12 MTDI - ADC2_CH5 TOUCH5 RTC_GPIO15 -
16 14 MTMS - ADC2_CH6 TOUCH6 RTC_GPIO16 -
17 27 GPIO27 - ADC2_CH7 TOUCH7 RTC_GPIO17 -

4.12 Register Summary

Name Description Address Access

GPIO_OUT_REG GPIO 0-31 output register 0x3FF44004 R/W
GPIO_OUT_W1TS_REG GPIO 0-31 output register_W1TS 0x3FF44008 WO
GPIO_OUT_W1TC_REG GPIO 0-31 output register_W1TC 0x3FF4400C WO
GPIO_OUT1_REG GPIO 32-39 output register 0x3FF44010 R/W
GPIO_OUT1_W1TS_REG GPIO 32-39 output bit set register 0x3FF44014 WO
GPIO_OUT1_W1TC_REG GPIO 32-39 output bit clear register 0x3FF44018 WO
GPIO_ENABLE_REG GPIO 0-31 output enable register 0x3FF44020 R/W
GPIO_ENABLE_W1TS_REG GPIO 0-31 output enable register_W1TS 0x3FF44024 WO
GPIO_ENABLE_W1TC_REG GPIO 0-31 output enable register_W1TC 0x3FF44028 WO
GPIO_ENABLE1_REG GPIO 32-39 output enable register 0x3FF4402C R/W
GPIO_ENABLE1_W1TS_REG GPIO 32-39 output enable bit set register 0x3FF44030 WO
GPIO_ENABLE1_W1TC_REG GPIO 32-39 output enable bit clear register 0x3FF44034 WO
GPIO_STRAP_REG Bootstrap pin value register 0x3FF44038 RO
GPIO_IN_REG GPIO 0-31 input register 0x3FF4403C RO
GPIO_IN1_REG GPIO 32-39 input register 0x3FF44040 RO
GPIO_STATUS_REG GPIO 0-31 interrupt status register 0x3FF44044 R/W
GPIO_STATUS_W1TS_REG GPIO 0-31 interrupt status register_W1TS 0x3FF44048 WO
GPIO_STATUS_W1TC_REG GPIO 0-31 interrupt status register_W1TC 0x3FF4404C WO
GPIO_STATUS1_REG GPIO 32-39 interrupt status register1 0x3FF44050 R/W
GPIO_STATUS1_W1TS_REG GPIO 32-39 interrupt status bit set register 0x3FF44054 WO
GPIO_STATUS1_W1TC_REG GPIO 32-39 interrupt status bit clear register 0x3FF44058 WO
GPIO_ACPU_INT_REG GPIO 0-31 APP_CPU interrupt status 0x3FF44060 RO
GPIO 0-31 APP_CPU non-maskable interrupt
GPIO_ACPU_NMI_INT_REG 0x3FF44064 RO
status
GPIO_PCPU_INT_REG GPIO 0-31 PRO_CPU interrupt status 0x3FF44068 RO

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Name Description Address Access

GPIO 0-31 PRO_CPU non-maskable interrupt
GPIO_PCPU_NMI_INT_REG 0x3FF4406C RO
status
GPIO_ACPU_INT1_REG GPIO 32-39 APP_CPU interrupt status 0x3FF44074 RO
GPIO 32-39 APP_CPU non-maskable interrupt
GPIO_ACPU_NMI_INT1_REG 0x3FF44078 RO
status
GPIO_PCPU_INT1_REG GPIO 32-39 PRO_CPU interrupt status 0x3FF4407C RO
GPIO 32-39 PRO_CPU non-maskable interrupt
GPIO_PCPU_NMI_INT1_REG 0x3FF44080 RO
status
GPIO_PIN0_REG Configuration for GPIO pin 0 0x3FF44088 R/W
GPIO_PIN1_REG Configuration for GPIO pin 1 0x3FF4408C R/W
GPIO_PIN2_REG Configuration for GPIO pin 2 0x3FF44090 R/W
... ...
GPIO_PIN38_REG Configuration for GPIO pin 38 0x3FF44120 R/W
GPIO_PIN39_REG Configuration for GPIO pin 39 0x3FF44124 R/W
GPIO_FUNC0_IN_SEL_CFG_REG Peripheral function 0 input selection register 0x3FF44130 R/W
GPIO_FUNC1_IN_SEL_CFG_REG Peripheral function 1 input selection register 0x3FF44134 R/W
... ...
GPIO_FUNC254_IN_SEL_CFG_REG Peripheral function 254 input selection register 0x3FF44528 R/W
GPIO_FUNC255_IN_SEL_CFG_REG Peripheral function 255 input selection register 0x3FF4452C R/W
GPIO_FUNC0_OUT_SEL_CFG_REG Peripheral output selection for GPIO 0 0x3FF44530 R/W
GPIO_FUNC1_OUT_SEL_CFG_REG Peripheral output selection for GPIO 1 0x3FF44534 R/W
... ...
GPIO_FUNC38_OUT_SEL_CFG_REG Peripheral output selection for GPIO 38 0x3FF445C8 R/W
GPIO_FUNC39_OUT_SEL_CFG_REG Peripheral output selection for GPIO 39 0x3FF445CC R/W

Name Description Address Access

IO_MUX_PIN_CTRL Clock output configuration register 0x3FF49000 R/W
IO_MUX_GPIO36_REG Configuration register for pad GPIO36 0x3FF49004 R/W
IO_MUX_GPIO37_REG Configuration register for pad GPIO37 0x3FF49008 R/W
IO_MUX_GPIO38_REG Configuration register for pad GPIO38 0x3FF4900C R/W
IO_MUX_GPIO39_REG Configuration register for pad GPIO39 0x3FF49010 R/W
IO_MUX_GPIO34_REG Configuration register for pad GPIO34 0x3FF49014 R/W
IO_MUX_GPIO35_REG Configuration register for pad GPIO35 0x3FF49018 R/W
IO_MUX_GPIO32_REG Configuration register for pad GPIO32 0x3FF4901C R/W
IO_MUX_GPIO33_REG Configuration register for pad GPIO33 0x3FF49020 R/W
IO_MUX_GPIO25_REG Configuration register for pad GPIO25 0x3FF49024 R/W
IO_MUX_GPIO26_REG Configuration register for pad GPIO26 0x3FF49028 R/W
IO_MUX_GPIO27_REG Configuration register for pad GPIO27 0x3FF4902C R/W
IO_MUX_MTMS_REG Configuration register for pad MTMS 0x3FF49030 R/W
IO_MUX_MTDI_REG Configuration register for pad MTDI 0x3FF49034 R/W
IO_MUX_MTCK_REG Configuration register for pad MTCK 0x3FF49038 R/W
IO_MUX_MTDO_REG Configuration register for pad MTDO 0x3FF4903C R/W
IO_MUX_GPIO2_REG Configuration register for pad GPIO2 0x3FF49040 R/W

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Name Description Address Access

IO_MUX_GPIO0_REG Configuration register for pad GPIO0 0x3FF49044 R/W
IO_MUX_GPIO4_REG Configuration register for pad GPIO4 0x3FF49048 R/W
IO_MUX_GPIO16_REG Configuration register for pad GPIO16 0x3FF4904C R/W
IO_MUX_GPIO17_REG Configuration register for pad GPIO17 0x3FF49050 R/W
IO_MUX_SD_DATA2_REG Configuration register for pad SD_DATA2 0x3FF49054 R/W
IO_MUX_SD_DATA3_REG Configuration register for pad SD_DATA3 0x3FF49058 R/W
IO_MUX_SD_CMD_REG Configuration register for pad SD_CMD 0x3FF4905C R/W
IO_MUX_SD_CLK_REG Configuration register for pad SD_CLK 0x3FF49060 R/W
IO_MUX_SD_DATA0_REG Configuration register for pad SD_DATA0 0x3FF49064 R/W
IO_MUX_SD_DATA1_REG Configuration register for pad SD_DATA1 0x3FF49068 R/W
IO_MUX_GPIO5_REG Configuration register for pad GPIO5 0x3FF4906C R/W
IO_MUX_GPIO18_REG Configuration register for pad GPIO18 0x3FF49070 R/W
IO_MUX_GPIO19_REG Configuration register for pad GPIO19 0x3FF49074 R/W
IO_MUX_GPIO20_REG Configuration register for pad GPIO20 0x3FF49078 R/W
IO_MUX_GPIO21_REG Configuration register for pad GPIO21 0x3FF4907C R/W
IO_MUX_GPIO22_REG Configuration register for pad GPIO22 0x3FF49080 R/W
IO_MUX_U0RXD_REG Configuration register for pad U0RXD 0x3FF49084 R/W
IO_MUX_U0TXD_REG Configuration register for pad U0TXD 0x3FF49088 R/W
IO_MUX_GPIO23_REG Configuration register for pad GPIO23 0x3FF4908C R/W
IO_MUX_GPIO24_REG Configuration register for pad GPIO24 0x3FF49090 R/W

Name Description Address Access

GPIO configuration / data registers
RTCIO_RTC_GPIO_OUT_REG RTC GPIO output register 0x3FF48400 R/W
RTCIO_RTC_GPIO_OUT_W1TS_REG RTC GPIO output bit set register 0x3FF48404 WO
RTCIO_RTC_GPIO_OUT_W1TC_REG RTC GPIO output bit clear register 0x3FF48408 WO
RTCIO_RTC_GPIO_ENABLE_REG RTC GPIO output enable register 0x3FF4840C R/W
RTCIO_RTC_GPIO_ENABLE_W1TS_REG RTC GPIO output enable bit set register 0x3FF48410 WO
RTCIO_RTC_GPIO_ENABLE_W1TC_REG RTC GPIO output enable bit clear register 0x3FF48414 WO
RTCIO_RTC_GPIO_STATUS_REG RTC GPIO interrupt status register 0x3FF48418 WO
RTCIO_RTC_GPIO_STATUS_W1TS_REG RTC GPIO interrupt status bit set register 0x3FF4841C WO
RTCIO_RTC_GPIO_STATUS_W1TC_REG RTC GPIO interrupt status bit clear register 0x3FF48420 WO
RTCIO_RTC_GPIO_IN_REG RTC GPIO input register 0x3FF48424 RO
RTCIO_RTC_GPIO_PIN0_REG RTC configuration for pin 0 0x3FF48428 R/W
RTCIO_RTC_GPIO_PIN1_REG RTC configuration for pin 1 0x3FF4842C R/W
RTCIO_RTC_GPIO_PIN2_REG RTC configuration for pin 2 0x3FF48430 R/W
RTCIO_RTC_GPIO_PIN3_REG RTC configuration for pin 3 0x3FF48434 R/W
RTCIO_RTC_GPIO_PIN4_REG RTC configuration for pin 4 0x3FF48438 R/W
RTCIO_RTC_GPIO_PIN5_REG RTC configuration for pin 5 0x3FF4843C R/W
RTCIO_RTC_GPIO_PIN6_REG RTC configuration for pin 6 0x3FF48440 R/W
RTCIO_RTC_GPIO_PIN7_REG RTC configuration for pin 7 0x3FF48444 R/W
RTCIO_RTC_GPIO_PIN8_REG RTC configuration for pin 8 0x3FF48448 R/W
RTCIO_RTC_GPIO_PIN9_REG RTC configuration for pin 9 0x3FF4844C R/W

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Name Description Address Access

RTCIO_RTC_GPIO_PIN10_REG RTC configuration for pin 10 0x3FF48450 R/W
RTCIO_RTC_GPIO_PIN11_REG RTC configuration for pin 11 0x3FF48454 R/W
RTCIO_RTC_GPIO_PIN12_REG RTC configuration for pin 12 0x3FF48458 R/W
RTCIO_RTC_GPIO_PIN13_REG RTC configuration for pin 13 0x3FF4845C R/W
RTCIO_RTC_GPIO_PIN14_REG RTC configuration for pin 14 0x3FF48460 R/W
RTCIO_RTC_GPIO_PIN15_REG RTC configuration for pin 15 0x3FF48464 R/W
RTCIO_RTC_GPIO_PIN16_REG RTC configuration for pin 16 0x3FF48468 R/W
RTCIO_RTC_GPIO_PIN17_REG RTC configuration for pin 17 0x3FF4846C R/W
RTCIO_DIG_PAD_HOLD_REG RTC GPIO hold register 0x3FF48474 R/W
GPIO RTC function configuration registers
RTCIO_HALL_SENS_REG Hall sensor configuration 0x3FF48478 R/W
RTCIO_SENSOR_PADS_REG Sensor pads configuration register 0x3FF4847C R/W
RTCIO_ADC_PAD_REG ADC configuration register 0x3FF48480 R/W
RTCIO_PAD_DAC1_REG DAC1 configuration register 0x3FF48484 R/W
RTCIO_PAD_DAC2_REG DAC2 configuration register 0x3FF48488 R/W
RTCIO_XTAL_32K_PAD_REG 32KHz crystal pads configuration register 0x3FF4848C R/W
RTCIO_TOUCH_CFG_REG Touch sensor configuration register 0x3FF48490 R/W
RTCIO_TOUCH_PAD0_REG Touch pad configuration register 0x3FF48494 R/W
... ...
RTCIO_TOUCH_PAD9_REG Touch pad configuration register 0x3FF484B8 R/W
RTCIO_EXT_WAKEUP0_REG External wake up configuration register 0x3FF484BC R/W
RTCIO_XTL_EXT_CTR_REG Crystal power down enable GPIO source 0x3FF484C0 R/W
RTCIO_SAR_I2C_IO_REG RTC I2C pad selection 0x3FF484C4 R/W

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4.13 Registers

Register 4.1: GPIO_OUT_REG (0x0004)

31 0

x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x Reset

GPIO_OUT_REG GPIO0-31 output value. (R/W)

Register 4.2: GPIO_OUT_W1TS_REG (0x0008)

31 0

x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x Reset

GPIO_OUT_W1TS_REG GPIO0-31 output set register. For every bit that is 1 in the value written here,
the corresponding bit in GPIO_OUT_REG will be set. (WO)

Register 4.3: GPIO_OUT_W1TC_REG (0x000c)

31 0

x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x Reset

GPIO_OUT_W1TC_REG GPIO0-31 output clear register. For every bit that is 1 in the value written
here, the corresponding bit in GPIO_OUT_REG will be cleared. (WO)

Register 4.4: GPIO_OUT1_REG (0x0010)

A
AT
_D
UT
d)

_O
ve
r

O
se

PI
(re

31 8 7 0

0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 x x x x x x x x Reset

GPIO_OUT_DATA GPIO32-39 output value. (R/W)

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Register 4.5: GPIO_OUT1_W1TS_REG (0x0014)

TA
_ DA
UT
d)

_O
ve
r

O
se

PI
(re

G
31 8 7 0

0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 x x x x x x x x Reset

GPIO_OUT_DATA GPIO32-39 output value set register. For every bit that is 1 in the value written
here, the corresponding bit in GPIO_OUT1_DATA will be set. (WO)

Register 4.6: GPIO_OUT1_W1TC_REG (0x0018)

A
AT
_D
UT
)
ed

_O
rv

O
se

PI
(re

G
31 8 7 0

0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 x x x x x x x x Reset

GPIO_OUT_DATA GPIO32-39 output value clear register. For every bit that is 1 in the value written
here, the corresponding bit in GPIO_OUT1_DATA will be cleared. (WO)

Register 4.7: GPIO_ENABLE_REG (0x0020)

31 0

x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x Reset

GPIO_ENABLE_REG GPIO0-31 output enable. (R/W)

Register 4.8: GPIO_ENABLE_W1TS_REG (0x0024)

31 0

x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x Reset

GPIO_ENABLE_W1TS_REG GPIO0-31 output enable set register. For every bit that is 1 in the value
written here, the corresponding bit in GPIO_ENABLE will be set. (WO)

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Register 4.9: GPIO_ENABLE_W1TC_REG (0x0028)

31 0

x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x Reset

GPIO_ENABLE_W1TC_REG GPIO0-31 output enable clear register. For every bit that is 1 in the
value written here, the corresponding bit in GPIO_ENABLE will be cleared. (WO)

Register 4.10: GPIO_ENABLE1_REG (0x002c)

A
AT
_D
B LE
NA
d )

_E
ve
r

O
se

PI
(re

G
31 8 7 0

0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 x x x x x x x x Reset

GPIO_ENABLE_DATA GPIO32-39 output enable. (R/W)

Register 4.11: GPIO_ENABLE1_W1TS_REG (0x0030)

TA
DA
E_
BL
NA
d )

_E
ve
r

O
se

PI
(re

31 8 7 0

0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 x x x x x x x x Reset

GPIO_ENABLE_DATA GPIO32-39 output enable set register. For every bit that is 1 in the value written
here, the corresponding bit in GPIO_ENABLE1 will be set. (WO)

Register 4.12: GPIO_ENABLE1_W1TC_REG (0x0034)

TA
DA
E_
BL
NA
)
ed

_E
rv

O
se

PI
(re

31 8 7 0

0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 x x x x x x x x Reset

GPIO_ENABLE_DATA GPIO32-39 output enable clear register. For every bit that is 1 in the value
written here, the corresponding bit in GPIO_ENABLE1 will be cleared. (WO)

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Register 4.13: GPIO_STRAP_REG (0x0038)

NG
PI
AP
TR
)
ed

_S
v
er

O
s

PI
(re

G
31 16 15 0

0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 x x x x x x x x x x x x x x x x Reset

GPIO_STRAPPING GPIO strapping results: Bit5-bit0 of boot_sel_chip[5:0] correspond to MTDI,

GPIO0, GPIO2, GPIO4, MTDO, GPIO5, respectively.

Register 4.14: GPIO_IN_REG (0x003c)

31 0

x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x Reset

GPIO_IN_REG GPIO0-31 input value. Each bit represents a pad input value, 1 for high level and 0
for low level. (RO)

Register 4.15: GPIO_IN1_REG (0x0040)

XT
NE
_
TA
DA
N_
)
ed

_I
rv

O
se

PI
(re

31 8 7 0

0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 x x x x x x x x Reset

GPIO_IN_DATA_NEXT GPIO32-39 input value. Each bit represents a pad input value. (RO)

Register 4.16: GPIO_STATUS_REG (0x0044)

31 0

x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x Reset

GPIO_STATUS_REG GPIO0-31 interrupt status register. Each bit can be either of the two interrupt
sources for the two CPUs. The enable bits in GPIO_STATUS_INTERRUPT, corresponding to the
0-4 bits in GPIO_PINn_REG should be set to 1. (R/W)

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Register 4.17: GPIO_STATUS_W1TS_REG (0x0048)

31 0

x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x Reset

GPIO_STATUS_W1TS_REG GPIO0-31 interrupt status set register. For every bit that is 1 in the value
written here, the corresponding bit in GPIO_STATUS_INTERRUPT will be set. (WO)

Register 4.18: GPIO_STATUS_W1TC_REG (0x004c)

31 0

x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x Reset

GPIO_STATUS_W1TC_REG GPIO0-31 interrupt status clear register. For every bit that is 1 in the
value written here, the corresponding bit in GPIO_STATUS_INTERRUPT will be cleared. (WO)

Register 4.19: GPIO_STATUS1_REG (0x0050)

PT
RU
T ER
IN
S_
TU
TA
d )

_S
ve
r

O
se

PI
(re

31 8 7 G 0

0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 x x x x x x x x Reset

GPIO_STATUS_INTERRUPT GPIO32-39 interrupt status. (R/W)

Register 4.20: GPIO_STATUS1_W1TS_REG (0x0054)

T
UP
RR
TE
IN
S_
TU
TA
)
ed

_S
rv

O
se

PI
(re

31 8 7 0

0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 x x x x x x x x Reset

GPIO_STATUS_INTERRUPT GPIO32-39 interrupt status set register. For every bit that is 1 in the
value written here, the corresponding bit in GPIO_STATUS_INTERRUPT1 will be set. (WO)

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Register 4.21: GPIO_STATUS1_W1TC_REG (0x0058)

P T
RU
TER
IN
S_
TU
TA
d)

_S
ve
r

O
se

PI
(re

G
31 8 7 0

0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 x x x x x x x x Reset

GPIO_STATUS_INTERRUPT GPIO32-39 interrupt status clear register. For every bit that is 1 in the
value written here, the corresponding bit in GPIO_STATUS_INTERRUPT1 will be cleared. (WO)

Register 4.22: GPIO_ACPU_INT_REG (0x0060)

31 0

x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x Reset

GPIO_ACPU_INT_REG GPIO0-31 APP CPU interrupt status. (RO)

Register 4.23: GPIO_ACPU_NMI_INT_REG (0x0064)

31 0

x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x Reset

GPIO_ACPU_NMI_INT_REG GPIO0-31 APP CPU non-maskable interrupt status. (RO)

Register 4.24: GPIO_PCPU_INT_REG (0x0068)

31 0

x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x Reset

GPIO_PCPU_INT_REG GPIO0-31 PRO CPU interrupt status. (RO)

Register 4.25: GPIO_PCPU_NMI_INT_REG (0x006c)

31 0

x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x Reset

GPIO_PCPU_NMI_INT_REG GPIO0-31 PRO CPU non-maskable interrupt status. (RO)

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Register 4.26: GPIO_ACPU_INT1_REG (0x0074)

T
IN
U_
CP
PP
d)

_A
ve
r

O
se

PI
(re

G
31 8 7 0

0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 x x x x x x x x Reset

GPIO_APPCPU_INT GPIO32-39 APP CPU interrupt status. (RO)

Register 4.27: GPIO_ACPU_NMI_INT1_REG (0x0078)

T
IN
I_
NM
U_
CP
PP
)
ed

_A
rv

O
se

PI
(re

G
31 8 7 0

0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 x x x x x x x x Reset

GPIO_APPCPU_NMI_INT GPIO32-39 APP CPU non-maskable interrupt status. (RO)

Register 4.28: GPIO_PCPU_INT1_REG (0x007c)

T
IN
U_
CP
RO
)
ed

_P
rv

O
se

PI
(re

31 8 7 0

0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 x x x x x x x x Reset

GPIO_PROCPU_INT GPIO32-39 PRO CPU interrupt status. (RO)

Register 4.29: GPIO_PCPU_NMI_INT1_REG (0x0080)

T
IN
I_
NM
U_
CP
RO
d)

_P
e
rv

O
se

PI
(re

31 8 7 0

0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 x x x x x x x x Reset

GPIO_PROCPU_NMI_INT GPIO32-39 PRO CPU non-maskable interrupt status. (RO)

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Register 4.30: GPIO_PINn_REG (n: 0-39) (0x88+0x4*n)

LE
AB
EN

ER
P_

IV
PE
A

DR
EU
EN

TY

D_
AK
T_

_
NT

rv _PA
IN

_I
n_

n_

n
IN

IN

IN

(re PIN
d)

)
ed

ed

ed
_P

_P

_P
ve

rv

rv

_
er

O
se

se

se
s

PI

PI

PI

PI
(re

(re

(re
G

G
31 18 17 13 12 11 10 9 7 6 3 2 1 0

0 0 0 0 0 0 0 0 0 0 0 0 0 0 x x x x x 0 0 x x x x 0 0 0 0 x 0 0 Reset

GPIO_PINn_INT_ENA Interrupt enable bits for pin n: (R/W)

bit0: APP CPU interrupt enable;
bit1: APP CPU non-maskable interrupt enable;
bit3: PRO CPU interrupt enable;
bit4: PRO CPU non-maskable interrupt enable.

GPIO_PINn_WAKEUP_ENABLE GPIO wake-up enable will only wake up the CPU from Light-sleep.
(R/W)

GPIO_PINn_INT_TYPE Interrupt type selection: (R/W)

0: GPIO interrupt disable;
1: rising edge trigger;
2: falling edge trigger;
3: any edge trigger;
4: low level trigger;
5: high level trigger.

GPIO_PINn_PAD_DRIVER 0: normal output; 1: open drain output. (R/W)

Register 4.31: GPIO_FUNCm_IN_SEL_CFG_REG (m: 0-255) (0x130+0x4*m)

L
SE
V_

L
SE
IN
_I L
E
N_

N_
C m _S

_I
UN IN

Cm
_F _
O m

UN
PI IG
d)

G O_S
ve

_F
r

O
se

PI

PI
(re

31 8 7 6 5 0

0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 x x x x x x x x Reset

GPIO_SIGm_IN_SEL Bypass the GPIO Matrix. 1: route through GPIO Matrix, 0: connect signal
directly to peripheral configured in the IO_MUX. (R/W)

GPIO_FUNCm_IN_INV_SEL Invert the input value. 1: invert; 0: do not invert. (R/W)

GPIO_FUNCm_IN_SEL Selection control for peripheral input m. A value of 0-39 selects which of the
40 GPIO Matrix input pins this signal is connected to, or 0x38 for a constantly high input or 0x30
for a constantly low input. (R/W)

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Register 4.32: GPIO_FUNCn_OUT_SEL_CFG_REG (n: 0-19, 21-23, 25-27, 32-33) (0x530+0x4*n)

UT SE EL

EL
_O N_ _S

_S
_I L

EL
Cn OE INV

NV

_S
UN n_ N_

UT
_F C E
O N O

_O
PI U n _

Cn
G O_F NC

UN
)

PI U
ed

G O_F

_F
rv

O
se

PI

PI
(re

G
31 12 11 10 9 8 0

0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 x x x x x x x x x x x x Reset

GPIO_FUNCn_OEN_INV_SEL 1: Invert the output enable signal; 0: do not invert the output enable
signal. (R/W)

GPIO_FUNCn_OEN_SEL 1: Force the output enable signal to be sourced from bit n of

GPIO_ENABLE_REG; 0: use output enable signal from peripheral. (R/W)

GPIO_FUNCn_OUT_INV_SEL 1: Invert the output value; 0: do not invert the output value. (R/W)

GPIO_FUNCn_OUT_SEL Selection control for GPIO output n. A value of s (0<=s<256)

connects peripheral output s to GPIO output n. A value of 256 selects bit n of
GPIO_OUT_REG/GPIO_OUT1_REG and GPIO_ENABLE_REG/GPIO_ENABLE1_REG as the out-
put value and output enable. (R/W)

Register 4.33: IO_MUX_PIN_CTRL (0x3FF49000)

3

1
LK

LK

LK
_C

_C

_C
RL

RL

RL
)
ed

CT

CT

CT
rv
se

N_

N_

N_
(re

PI

PI

PI

31 12 11 8 7 4 3 0

0x0 0x0 0x0 0x0 Reset

If you want to output clock for I2S0 to:

CLK_OUT1, then set PIN_CTRL[3:0] = 0x0;
CLK_OUT2, then set PIN_CTRL[3:0] = 0x0 and PIN_CTRL[7:4] = 0x0;
CLK_OUT3, then set PIN_CTRL[3:0] = 0x0 and PIN_CTRL[11:8] = 0x0.
If you want to output clock for I2S1 to:
CLK_OUT1, then set PIN_CTRL[3:0] = 0xF;
CLK_OUT2, then set PIN_CTRL[3:0] = 0xF and PIN_CTRL[7:4] = 0x0;
CLK_OUT3, then set PIN_CTRL[3:0] = 0xF and PIN_CTRL[11:8] = 0x0. (R/W)

Note:
Only the above mentioned combinations of clock source and clock output pins are possible.
The CLK_OUT1-3 can be found in the IO_MUX Pad Summary.

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Register 4.34: IO_MUX_x_REG (x: GPIO0-GPIO39) (0x10+4*x)

SL _W U
M _SE D
CU V
N_ PU

CU D
L

FU RV

CU P
P P
)

CU L
E
ed

P
SE

M _W
M _IE

_O
_D
FU _W
W
FU IE
D
rv

N_

N_
CU

CU
se

N
FU
(re

M
31 15 14 12 11 10 9 8 7 6 5 4 3 2 1 0

0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0x0 0x2 0 0 0 0x0 0 0 0 0 0 Reset

MCU_SEL Select the IO_MUX function for this signal. 0 selects Function 1, 1 selects Function 2, etc.
(R/W)

FUN_DRV Select the drive strength of the pad. A higher value corresponds with a higher strength.
For GPIO34-39, FUN_DRV is always 0. (R/W)

FUN_IE Input enable of the pad. 1: input enabled; 0: input disabled. (R/W)

FUN_WPU Pull-up enable of the pad. 1: internal pull-up enabled; 0: internal pull-up disabled. For
GPIO34-39, FUN_WPU is always 0. (R/W)

FUN_WPD Pull-down enable of the pad. 1: internal pull-down enabled, 0: internal pull-down dis-
abled. For GPIO34-39, FUN_WPD is always 0. (R/W)

MCU_DRV Select the drive strength of the pad during sleep mode. A higher value corresponds with
a higher strength. (R/W)

MCU_IE Input enable of the pad during sleep mode. 1: input enabled; 0: input disabled. (R/W)

MCU_WPU Pull-up enable of the pad during sleep mode. 1: internal pull-up enabled; 0: internal
pull-up disabled. (R/W)

MCU_WPD Pull-down enable of the pad during sleep mode. 1: internal pull-down enabled; 0: internal
pull-down disabled. (R/W)

SLP_SEL Sleep mode selection of this pad. Set to 1 to put the pad in sleep mode. (R/W)

MCU_OE Output enable of the pad in sleep mode. 1: enable output; 0: disable output. (R/W)

Register 4.35: RTCIO_RTC_GPIO_OUT_REG (0x0000)

A
AT
_D
UT
_O
O
PI
_G
TC

)
_R

ed
rv
O
CI

se
RT

(re

31 14 13 0

x x x x x x x x x x x x x x x x x x 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Reset

RTCIO_RTC_GPIO_OUT_DATA GPIO0-17 output register. Bit14 is GPIO[0], bit15 is GPIO[1], etc.

(R/W)

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4. IO_MUX and GPIO Matrix

Register 4.36: RTCIO_RTC_GPIO_OUT_W1TS_REG (0x0004)

S
1T
A _W
AT
_D
UT
_O
O
PI
_G
TC

)
_R

ed
rv
O
CI

se
RT

(re
31 14 13 0

x x x x x x x x x x x x x x x x x x 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Reset

RTCIO_RTC_GPIO_OUT_DATA_W1TS GPIO0-17 output set register. For every bit that is 1 in the
value written here, the corresponding bit in RTCIO_RTC_GPIO_OUT will be set. (WO)

Register 4.37: RTCIO_RTC_GPIO_OUT_W1TC_REG (0x0008)

C
1T
W
A_
AT
_D
UT
_O
O
PI
_G
TC

)
_R

ed
rv
O
CI

se
RT

(re

31 14 13 0

x x x x x x x x x x x x x x x x x x 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Reset

RTCIO_RTC_GPIO_OUT_DATA_W1TC GPIO0-17 output clear register. For every bit that is 1 in the
value written here, the corresponding bit in RTCIO_RTC_GPIO_OUT will be cleared. (WO)

Register 4.38: RTCIO_RTC_GPIO_ENABLE_REG (0x000C)

E
BL
NA
_E
O
PI
_G
TC

)
_R

ed
rv
O
CI

se
RT

(re

31 14 13 0

x x x x x x x x x x x x x x x x x x 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Reset

RTCIO_RTC_GPIO_ENABLE GPIO0-17 output enable. Bit14 is GPIO[0], bit15 is GPIO[1], etc. 1

means this GPIO pad is output. (R/W)

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4. IO_MUX and GPIO Matrix

Register 4.39: RTCIO_RTC_GPIO_ENABLE_W1TS_REG (0x0010)

S
1T
_W
B LE
NA
_E
O
PI
_ G
TC

)
_R

ed
rv
O
CI

se
RT

(re
31 14 13 0

x x x x x x x x x x x x x x x x x x 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Reset

RTCIO_RTC_GPIO_ENABLE_W1TS GPIO0-17 output enable set register. For every bit that is 1 in
the value written here, the corresponding bit in RTCIO_RTC_GPIO_ENABLE will be set. (WO)

Register 4.40: RTCIO_RTC_GPIO_ENABLE_W1TC_REG (0x0014)

C
1T
W
E_
BL
NA
_E
O
PI
G
C_
T

)
_R

ed
rv
O
CI

se
RT

(re
31 14 13 0

x x x x x x x x x x x x x x x x x x 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Reset

RTCIO_RTC_GPIO_ENABLE_W1TC GPIO0-17 output enable clear register. For every bit that is 1 in
the value written here, the corresponding bit in RTCIO_RTC_GPIO_ENABLE will be cleared. (WO)

Register 4.41: RTCIO_RTC_GPIO_STATUS_REG (0x0018)

T
IN
S_
TU
TA
_S
O
PI
_G
TC

)
_R

ed
rv
O
CI

se
RT

(re

31 14 13 0

x x x x x x x x x x x x x x x x x x 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Reset

RTCIO_RTC_GPIO_STATUS_INT GPIO0-17 interrupt status. Bit14 is GPIO[0], bit15 is GPIO[1],

etc. This register should be used together with RTCIO_RTC_GPIO_PINn_INT_TYPE in RT-
CIO_RTC_GPIO_PINn_REG. 1: corresponding interrupt; 0: no interrupt. (R/W)

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4. IO_MUX and GPIO Matrix

Register 4.42: RTCIO_RTC_GPIO_STATUS_W1TS_REG (0x001C)

S
1T
_W
NT
S _I
TU
TA
_S
O
PI
_G
TC

)
_R

ed
rv
O
CI

se
RT

(re
31 14 13 0

x x x x x x x x x x x x x x x x x x 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Reset

RTCIO_RTC_GPIO_STATUS_INT_W1TS GPIO0-17 interrupt set register. For every bit that is 1 in

the value written here, the corresponding bit in RTCIO_RTC_GPIO_STATUS_INT will be set. (WO)

Register 4.43: RTCIO_RTC_GPIO_STATUS_W1TC_REG (0x0020)

C
1T
W
T_
IN
S_
TU
TA
_S
O
PI
_G
TC

)
_R

ed
rv
O
CI

se
RT

(re

31 14 13 0

x x x x x x x x x x x x x x x x x x 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Reset

RTCIO_RTC_GPIO_STATUS_INT_W1TC GPIO0-17 interrupt clear register. For every bit that is 1 in

the value written here, the corresponding bit in RTCIO_RTC_GPIO_STATUS_INT will be cleared.
(WO)

Register 4.44: RTCIO_RTC_GPIO_IN_REG (0x0024)

T
EX
N _N
_I
O
PI
_G
TC

)
_R

ed
rv
O
CI

se
RT

(re

31 14 13 0

x x x x x x x x x x x x x x x x x x 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Reset

RTCIO_RTC_GPIO_IN_NEXT GPIO0-17 input value. Bit14 is GPIO[0], bit15 is GPIO[1], etc. Each
bit represents a pad input value, 1 for high level, and 0 for low level. (RO)

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4. IO_MUX and GPIO Matrix

Register 4.45: RTCIO_RTC_GPIO_PINn_REG (n: 0-17) (28+4*n)

LE
AB
EN

ER
P_

IV
E
YP

DR
EU

D_
AK

T_

PA
IN
W
n_

n_

n_
IN

IN

IN
_P

_P

_P
O

IO
PI

PI

ed GP
_G

_G

C_
TC

TC

(re _RT
)

)
_R

_R
ed

ed
rv

rv

rv
O

O
CI

CI

CI
se

se

se
RT

RT

RT
(re

(re
31 11 10 9 7 6 3 2 1 0

0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 x x x x 0 0 0 0 x 0 0 Reset

RTCIO_RTC_GPIO_PINn_WAKEUP_ENABLE GPIO wake-up enable. This will only wake up the

ESP32 from Light-sleep. (R/W)

RTCIO_RTC_GPIO_PINn_INT_TYPE GPIO interrupt type selection. (R/W)

0: GPIO interrupt disable;
1: rising edge trigger;
2: falling edge trigger;
3: any edge trigger;
4: low level trigger;
5: high level trigger.

RTCIO_RTC_GPIO_PINn_PAD_DRIVER Pad driver selection. 0: normal output; 1: open drain.

(R/W)

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4. IO_MUX and GPIO Matrix

Register 4.46: RTCIO_DIG_PAD_HOLD_REG (0x0074)

31 0

0 Reset

RTCIO_DIG_PAD_HOLD_REG Selects the digital pads which should be put on hold. While 0 allows
normal operation, 1 puts the pad on hold. (R/W)

Name Description
Bit[0] Set to 1 to enable the Hold function of pad U0RTD
Bit[1] Set to 1 to enable the Hold function of pad U0TXD
Bit[2] Set to 1 to enable the Hold function of pad
SD_CLK
Bit[3] Set to 1 to enable the Hold function of pad
SD_DATA0
Bit[4] Set to 1 to enable the Hold function of pad
SD_DATA1
Bit[5] Set to 1 to enable the Hold function of pad
SD_DATA2
Bit[6] Set to 1 to enable the Hold function of pad
SD_DATA3
Bit[7] Set to 1 to enable the Hold function of pad
SD_CMD
Bit[8] Set to 1 to enable the Hold function of pad GPIO5
Bit[9] Set to 1 to enable the Hold function of pad GPIO16
Bit[10] Set to 1 to enable the Hold function of pad GPIO17
Bit[11] Set to 1 to enable the Hold function of pad GPIO18
Bit[12] Set to 1 to enable the Hold function of pad GPIO19
Bit[13] Set to 1 to enable the Hold function of pad GPIO20
Bit[14] Set to 1 to enable the Hold function of pad GPIO21
Bit[15] Set to 1 to enable the Hold function of pad GPIO22
Bit[16] Set to 1 to enable the Hold function of pad GPIO23

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4. IO_MUX and GPIO Matrix

Register 4.47: RTCIO_HALL_SENS_REG (0x0078)

AS ALL
E
PH H
L_ D_
AL XP
_H L_
O L
CI HA

d)
ve
RT IO_

er
C

s
RT

(re
31 30 29 0

0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Reset

RTCIO_HALL_XPD_HALL Power on hall sensor and connect to VP and VN. (R/W)

RTCIO_HALL_PHASE Reverse the polarity of the hall sensor. (R/W)

Register 4.48: RTCIO_SENSOR_PADS_REG (0x007C)

N _ X_ L
_M X_ L
UX SEL

CI ENS R_ NS FUN L

NS SE E2 LP L

NS SE E3 LP L

L
RT IO_ EN _SE 1_F P_I L

RT IO_ EN _SE 2_F P_I L

RT IO_ EN _SE 3_F P_I L

4_ P_ L
NS SE E3 U SE
CI SE R_ SE4 MU SE

RT _SE R_ NS 1_S SE

RT _SE R_ ENS 2_S SE

RT _SE R_ ENS 3_S SE

SE
E L E

E L E

E L E

SE SL SE
E

_S S S E4_ _IE

IE
_S

U E

UN E

UN E

FU IE
RT IO_ SO ENS 1_S P_S

NS _S _S

NS _S _S
RT IO_ EN R_ ENS 2_H LD
RT IO_ EN R_ ENS 3_H LD
O N R N _ LD
NS R_ NS _M LD

E2 N_I

_I
RT _SE R_ ENS 2_M X_

N_

N_
4_ P_
CI ENS R_ NS FUN

CI ENS R_ NS FUN
O S E U
C S SO S E O
C S SO S E O
CI SE SO SE E4 O
RT _SE SO _SE SE1 HO

FU
S E L

SE E L
RT IO_ EN R_ ENS 1_H

S
_

R_ N 4_
1

3
C S SO S E

O N R_ SE

SE E

SO _S SE
RT IO_ EN R_ ENS

NS

NS

NS

S
N

EN OR EN

N
SE

S O SE

S O SE

S SO SE

E
C S SO S

S
RT IO_ EN R_

O N R_

O N R_

O N R_
R

R
C S SO

CI SE SO

CI SE SO

CI SE SO

CI SE SO
S

S
RT IO_ EN

R T O_ N

)
C S

C S

C S

ed
RT IO_

RT O_

RT O_

R T O_

rv
O

O
CI

CI

CI

CI

se
C

C
C
RT

RT

RT

RT

(re
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 0

0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Reset

RTCIO_SENSOR_SENSEn_HOLD Set to 1 to hold the output value on sensen; 0 is for normal op-
eration. (R/W)

RTCIO_SENSOR_SENSEn_MUX_SEL 1: route sensen to the RTC block; 0: route sensen to the

digital IO_MUX. (R/W)

RTCIO_SENSOR_SENSEn_FUN_SEL Select the RTC IO_MUX function for this pad. 0: select Func-
tion 0; 1: select Function 1. (R/W)

RTCIO_SENSOR_SENSEn_SLP_SEL Selection of sleep mode for the pad: set to 1 to put the pad
in sleep mode. (R/W)

RTCIO_SENSOR_SENSEn_SLP_IE Input enable of the pad in sleep mode. 1: enabled; 0: disabled.

(R/W)

RTCIO_SENSOR_SENSEn_FUN_IE Input enable of the pad. 1: enabled; 0: disabled. (R/W)

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4. IO_MUX and GPIO Matrix

Register 4.49: RTCIO_ADC_PAD_REG (0x0080)

C1 X_ L
L

DC AD _S SEL
1 P L

2_ LP_ EL
AD MU _SE
_F SE

RT _AD _A 1_ _SE

AD DC _SL _SE

_F IE

IE
RT IO_ _A _FU _IE

FU IE
DC _S _S
RT _AD _A 2_ OLD
AD 1_ LD

C2 N_

N_
_ X

O C DC UN

O C DC UN
A 1 P

_A 2 P
C2 MU
C_ DC HO

C_ DC SL

L
O C DC H
CI AD _A 1_

_A _ 2
RT IO_ DC DC

C
D
C A _A

CI AD _A

CI AD A
_

_
RT IO_ DC

CI DC

RT IO_ DC

RT IO_ DC

)
C A

C A

ed
RT IO_

RT O_

rv
O

O
CI

CI

se
C

C
RT

RT

RT

(re
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 0

0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Reset

RTCIO_ADC_ADCn_HOLD Set to 1 to hold the output value on the pad; 0 is for normal operation.
(R/W)

RTCIO_ADC_ADCn_MUX_SEL 0: route pad to the digital IO_MUX; (R/W)

1: route pad to the RTC block.

RTCIO_ADC_ADCn_FUN_SEL Select the RTC function for this pad. 0: select Function 0; 1: select
Function 1. (R/W)

RTCIO_ADC_ADCn_SLP_SEL Signal selection of pad’s sleep mode. Set this bit to 1 to put the pad
to sleep. (R/W)

RTCIO_ADC_ADCn_SLP_IE Input enable of the pad in sleep mode. 1 enabled; 0 disabled. (R/W)

RTCIO_ADC_ADCn_FUN_IE Input enable of the pad. 1 enabled; 0 disabled. (R/W)

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4. IO_MUX and GPIO Matrix

Register 4.50: RTCIO_PAD_DAC1_REG (0x0084)

E
RC
O
_F
RT IO_ AD_ C1 X_S C

PD
UN L

AD D 1_ P_ L
E
U A

SE

C1 FUN OE
_P _P C L E

AC E
_P AC SL IE

_X
RT IO_ _PD _M _D

O D A _S _S
DA 1_ LD

_ D _I
_

DA 1_ P_
AC
RV

_R E
UE

C1 PD

CI PA PD C1 LP
_P AC HO
C1 RD
CI PA PD _D

_D

RT IO_ AD_ DA _S
RT _PA DA _X

CI PA PD _F
AD D 1_
RT IO_ AD_ C1

C1

P C1

1
_P _P C

C
A

O D A

DA

D_ A

RT O_ D_ A
RT O_ _PD

RT _PA _PD
_P

P
D

AD

O D

D
RT _PA

CI PA

)
P

_P

C P

ed
RT IO_

rv
O

O
CI

CI

CI

CI

se
C

C
RT

RT

RT

(re
31 30 29 28 27 26 19 18 17 16 15 14 13 12 11 10 9 0

2 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Reset

RTCIO_PAD_PDAC1_DRV Select the drive strength of the pad. (R/W)

RTCIO_PAD_PDAC1_HOLD Set to 1 to hold the output value on the pad; set to 0 for normal oper-
ation. (R/W)

RTCIO_PAD_PDAC1_RDE 1: Pull-down on pad enabled; 0: Pull-down disabled. (R/W)

RTCIO_PAD_PDAC1_RUE 1: Pull-up on pad enabled; 0: Pull-up disabled. (R/W)

RTCIO_PAD_PDAC1_DAC PAD DAC1 output value. (R/W)

RTCIO_PAD_PDAC1_XPD_DAC Power on DAC1. Usually, PDAC1 needs to be tristated if we power

on the DAC, i.e. IE=0, OE=0, RDE=0, RUE=0. (R/W)

RTCIO_PAD_PDAC1_MUX_SEL 0: route pad to the digital IO_MUX; (R/W)

1: route to the RTC block.

RTCIO_PAD_PDAC1_FUN_SEL the functional selection signal of the pad. (R/W)

RTCIO_PAD_PDAC1_SLP_SEL Sleep mode selection signal of the pad. Set this bit to 1 to put the
pad to sleep. (R/W)

RTCIO_PAD_PDAC1_SLP_IE Input enable of the pad in sleep mode. 1: enabled; 0: disabled. (R/W)

RTCIO_PAD_PDAC1_SLP_OE Output enable of the pad. 1: enabled ; 0: disabled. (R/W)

RTCIO_PAD_PDAC1_FUN_IE Input enable of the pad. 1: enabled it; 0: disabled. (R/W)

RTCIO_PAD_PDAC1_DAC_XPD_FORCE Power on DAC1. Usually, we need to tristate PDAC1 if

we power on the DAC, i.e. IE=0, OE=0, RDE=0, RUE=0. (R/W)

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4. IO_MUX and GPIO Matrix

Register 4.51: RTCIO_PAD_DAC2_REG (0x0088)

E
RC
O
_F
RT IO_ AD_ C2 X_S C

PD
UN L

AD D 2_ P_ L
E
U A

SE

C2 FUN OE
_P _P C L E

AC E
_P AC SL IE

_X
RT IO_ _PD _M _D

O D A _S _S
DA 2_ LD

_ D _I
_

DA 2_ P_
AC
RV

_R E
UE

C2 PD

CI PA PD C2 LP
_P AC HO
C2 RD
CI PA PD _D

_D

RT IO_ AD_ DA _S
RT _PA DA _X

CI PA PD _F
AD D 2_
RT IO_ AD_ C2

C2

P C2

2
_P _P C

C
A

O D A

DA

D_ A

RT O_ D_ A
RT O_ _PD

RT _PA _PD
_P

P
D

AD

O D

D
RT _PA

CI PA

)
P

_P

C P

ed
RT IO_

rv
O

O
CI

CI

CI

CI

se
C

C
RT

RT

RT

(re
31 30 29 28 27 26 19 18 17 16 15 14 13 12 11 10 9 0

2 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Reset

RTCIO_PAD_PDAC2_DRV Select the drive strength of the pad. (R/W)

RTCIO_PAD_PDAC2_HOLD Set to 1 to hold the output value on the pad; 0 is for normal operation.
(R/W)

RTCIO_PAD_PDAC2_RDE 1: Pull-down on pad enabled; 0: Pull-down disabled. (R/W)

RTCIO_PAD_PDAC2_RUE 1: Pull-up on pad enabled; 0: Pull-up disabled. (R/W)

RTCIO_PAD_PDAC2_DAC PAD DAC2 output value. (R/W)

RTCIO_PAD_PDAC2_XPD_DAC Power on DAC2. PDAC2 needs to be tristated if we power on the

DAC, i.e. IE=0, OE=0, RDE=0, RUE=0. (R/W)

RTCIO_PAD_PDAC2_MUX_SEL 0: route pad to the digital IO_MUX; (R/W)

1: route to the RTC block.

RTCIO_PAD_PDAC2_FUN_SEL Select the RTC function for this pad. 0: select Function 0; 1: select
Function 1. (R/W)

RTCIO_PAD_PDAC2_SLP_SEL Sleep mode selection signal of the pad. Set this bit to 1 to put the
pad to sleep. (R/W)

RTCIO_PAD_PDAC2_SLP_IE Input enable of the pad in sleep mode. 1: enabled; 0: disabled. (R/W)

RTCIO_PAD_PDAC2_SLP_OE Output enable of the pad. 1: enabled; 0: disabled. (R/W)

RTCIO_PAD_PDAC2_FUN_IE Input enable of the pad. 1: enabled; 0: disabled. (R/W)

RTCIO_PAD_PDAC2_DAC_XPD_FORCE Power on DAC2. Usually, we need to tristate PDAC2 if

we power on the DAC, i.e. IE=0, OE=0, RDE=0, RUE=0. (R/W)

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4. IO_MUX and GPIO Matrix

Register 4.52: RTCIO_XTAL_32K_PAD_REG (0x008C)

2K
2K
32 UX EL
L
EL
K

L
_X N_ P_ L
P_ UX K

_X P_ P_ L
_F SE

_3
_X _FU _OE

CI XT _X P_ _SE

RE N_ E
AL 32 SL SE
RT _XT L_X D_X _32

_3
AL 2 L E
32 M 32

P_ _IE
M _S

IE
32 SL IE
S

32 SL IE
FU O
S

AL
32 RD D

_X P_ LD

_
N_

AL
RT _XT L_X N_ LP_
_X N_ L_

RT _XT L_X P_ P_

P_ P_
_X N_ L
O AL 32 RV

N E

2P E

N
O AL 32 RV

P_ E
E

UN
N P

XT
CI TAL 32 HO

CI TAL 32 HO
_X _RU

TA

XT
32 RD
RU

U
AL 32 TA

O A 32 SL
D

O A 32 S
_D

S
F

S_
RT IO_ TAL C_X

S_
N_

X _X N_

CI T X _
X _X P_

IA
32

RT O_ AL 32

32

RT IO_ TAL 32

DB
A

O A P
3

3
RT IO_ L_D

D
_X

CI XT _X

CI XT _X

CI XT _X

RT IO_ L_X

CI XT _X

X
_

L_

_
CI TAL

RT IO_ TAL

RT IO_ TAL

RT _ L

CI TAL

RT O_ AL

AL
A

A
RT _XT

RT _XT

RT _XT

CI XT

CI XT

(re _XT

)
ed
_X

C X

C X

C X

C X

_X
RT O_

R T O_

RT O_

rv
O

O
CI

CI

CI

CI

CI

CI

se
C

C
RT

RT

RT

RT

RT

RT
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

2 0 0 0 2 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 Reset

RTCIO_XTAL_X32N_DRV Select the drive strength of the pad. (R/W)

RTCIO_XTAL_X32N_HOLD Set to 1 to hold the output value on the pad; 0 is for normal operation.
(R/W)

RTCIO_XTAL_X32N_RDE 1: Pull-down on pad enabled; 0: Pull-down disabled. (R/W)

RTCIO_XTAL_X32N_RUE 1: Pull-up on pad enabled; 0: Pull-up disabled. (R/W)

RTCIO_XTAL_X32P_DRV Select the drive strength of the pad. (R/W)

RTCIO_XTAL_X32P_HOLD Set to 1 to hold the output value on the pad, 0 is for normal operation.
(R/W)

RTCIO_XTAL_X32P_RDE 1: Pull-down on pad enabled; 0: Pull-down disabled. (R/W)

RTCIO_XTAL_X32P_RUE 1: Pull-up on pad enabled; 0: Pull-up disabled. (R/W)

RTCIO_XTAL_DAC_XTAL_32K 32K XTAL bias current DAC value. (R/W)

RTCIO_XTAL_XPD_XTAL_32K Power up 32 KHz crystal oscillator. (R/W)

RTCIO_XTAL_X32N_MUX_SEL 0: route X32N pad to the digital IO_MUX; 1: route to RTC block.
(R/W)

RTCIO_XTAL_X32P_MUX_SEL 0: route X32P pad to the digital IO_MUX; 1: route to RTC block.
(R/W)

RTCIO_XTAL_X32N_FUN_SEL Select the RTC function. 0: select function 0; 1: select function 1.

(R/W)

RTCIO_XTAL_X32N_SLP_SEL Sleep mode selection. Set this bit to 1 to put the pad to sleep. (R/W)

RTCIO_XTAL_X32N_SLP_IE Input enable of the pad in sleep mode. 1: enabled; 0: disabled. (R/W)

RTCIO_XTAL_X32N_SLP_OE Output enable of the pad. 1: enabled; 0; disabled. (R/W)

RTCIO_XTAL_X32N_FUN_IE Input enable of the pad. 1: enabled; 0: disabled. (R/W)

RTCIO_XTAL_X32P_FUN_SEL Select the RTC function. 0: select function 0; 1: select function 1.

(R/W)

RTCIO_XTAL_X32P_SLP_SEL Sleep mode selection. Set this bit to 1 to put the pad to sleep. (R/W)

RTCIO_XTAL_X32P_SLP_IE Input enable of the pad in sleep mode. 1: enabled; 0: disabled. (R/W)

Continued on the next page...

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4. IO_MUX and GPIO Matrix

Register 4.52: RTCIO_XTAL_32K_PAD_REG (0x008C)

Continued from the previous page...

RTCIO_XTAL_X32P_SLP_OE Output enable of the pad in sleep mode. 1: enabled; 0: disabled.

(R/W)

RTCIO_XTAL_X32P_FUN_IE Input enable of the pad. 1: enabled; 0: disabled. (R/W)

RTCIO_XTAL_DRES_XTAL_32K 32K XTAL resistor bias control. (R/W)

RTCIO_XTAL_DBIAS_XTAL_32K 32K XTAL self-bias reference control. (R/W)

Register 4.53: RTCIO_TOUCH_CFG_REG (0x0090)

RE S

E
IA

G
FH
H_ _B

UR
AN
EF
D

DC
DR

DR
O _XP

H_

H_

H_
H
UC

UC

UC

UC

UC
RT _TO

)
ed
_T

_T

_T

_T

rv
O

O
CI

CI

CI

CI

CI

se
RT

RT

RT

RT

(re

31 30 29 28 27 26 25 24 23 22 0

0 1 1 0 0 1 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Reset

RTCIO_TOUCH_XPD_BIAS Touch sensor bias power on bit. 1: power on; 0: disabled. (R/W)

RTCIO_TOUCH_DREFH Touch sensor saw wave top voltage. (R/W)

RTCIO_TOUCH_DREFL Touch sensor saw wave bottom voltage. (R/W)

RTCIO_TOUCH_DRANGE Touch sensor saw wave voltage range. (R/W)

RTCIO_TOUCH_DCUR Touch sensor bias current. When BIAS_SLEEP is enabled, this setting is
available. (R/W)

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4. IO_MUX and GPIO Matrix

Register 4.54: RTCIO_TOUCH_PADn_REG (n: 0-9) (94+4*n)

EL
_F PIO
H_ n_T D T
D P P

_S
H AD TIE T
O _PA n_X _O

Dn _G
UC _P n_ AR
AC

UN
O
RT _TO CH AD _ST
_D
Dn

O U _P n
CI TO CH AD
PA

PA
RT O_ U _P
H_

CI TO CH
UC

UC
RT O_ U
O

CI TO
)

)
ed

ed
_T

_T
R T O_
rv

rv
O

O
CI

CI

CI
se

se
RT

RT
(re

(re
31 26 25 23 22 21 20 19 18 17 16 0

0 0 0 0 0 0 0x4 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Reset

RTCIO_TOUCH_PADn_DAC Touch sensor slope control. 3-bit for each touch pad, defaults to 100.
(R/W)

RTCIO_TOUCH_PADn_START Start touch sensor. (R/W)

RTCIO_TOUCH_PADn_TIE_OPT Default touch sensor tie option. 0: tie low; 1: tie high. (R/W)

RTCIO_TOUCH_PADn_XPD Touch sensor power on. (R/W)

RTCIO_TOUCH_PADn_TO_GPIO Connect the RTC pad input to digital pad input; 0 is available.
(R/W)

RTCIO_TOUCH_PADn_FUN_SEL Selects the function of RTC pad. 0: RTC Function 1; 3: RTC

Function 2. (R/W)

Register 4.55: RTCIO_EXT_WAKEUP0_REG (0x00BC)

L
E
_S
P0
EU
AK
W
X T_

d)
_E

e
rv
O
CI

se
RT

(re

31 27 26 0

0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Reset

RTCIO_EXT_WAKEUP0_SEL GPIO[0-17] can be used to wake up the chip when the chip is in the
sleep mode. This register prompts the pad source to wake up the chip when the latter is in
deep/light sleep mode. 0: select GPIO0; 1: select GPIO2, etc. (R/W)

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4. IO_MUX and GPIO Matrix

Register 4.56: RTCIO_XTL_EXT_CTR_REG (0x00C0)

L
SE
R_
CT
X T_
_E
TL

d)
_X

ve
O

er
CI

s
RT

(re
31 27 26 0

0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Reset

RTCIO_XTL_EXT_CTR_SEL Select the external crystal power down enable source to get into
sleep mode. 0: select GPIO0; 1: select GPIO2, etc. The input value on this pin XOR RT-
CIO_RTC_EXT_XTAL_CONF_REG[30] is the crystal power down enable signal. (R/W)

Register 4.57: RTCIO_SAR_I2C_IO_REG (0x00C4)

EL

EL
_S

_S
DA

CL
_S

_S
2C

2C
_I

_I
AR

AR

d)
_S

_S

e
rv
O

O
CI

CI

se
RT

RT

(re

31 30 29 28 27 0

0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Reset

RTCIO_SAR_I2C_SDA_SEL Selects the other pad as the RTC I2C SDA signal. 0: pad
TOUCH_PAD[1]; 1: pad TOUCH_PAD[3]. Default value is 0. (R/W)

RTCIO_SAR_I2C_SCL_SEL Selects the other pad as the RTC I2C SCL signal. 0: pad
TOUCH_PAD[0]; 1: pad TOUCH_PAD[2]. Default value is 0. (R/W)

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5. DPort Register

5. DPort Register

5.1 Introduction
The ESP32 integrates a large number of peripherals, and enables the control of individual peripherals to achieve
optimal characteristics in performance-vs-power-consumption scenarios. The DPort registers control clock
management (clock gating), power management, and the configuration of peripherals and core-system modules.
The system arranges each module with configuration registers contained in the DPort Register.

5.2 Features
DPort registers correspond to different peripheral blocks and core modules:

• System and memory

• Reset and clock

• Interrupt matrix

• DMA

• PID/MPU/MMU

• APP_CPU

• Peripheral clock gating and reset

5.3 Functional Description

5.3.1 System and Memory Register
The following registers are used for system and memory configuration, such as cache configuration and memory
remapping. For a detailed description of these registers, please refer to Chapter System and Memory.

• DPORT_PRO_BOOT_REMAP_CTRL_REG

• DPORT_APP_BOOT_REMAP_CTRL_REG

• DPORT_CACHE_MUX_MODE_REG

5.3.2 Reset and Clock Registers

The following register is used for Reset and Clock. For a detailed description of the register, please refer to Reset
and Clock.

• DPORT_CPU_PER_CONF_REG

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5. DPort Register

5.3.3 Interrupt Matrix Register

The following registers are used for configuring and mapping interrupts through the interrupt matrix. For a
detailed description of the registers, please refer to Interrupt Matrix.

• DPORT_CPU_INTR_FROM_CPU_0_REG

• DPORT_CPU_INTR_FROM_CPU_1_REG

• DPORT_CPU_INTR_FROM_CPU_2_REG

• DPORT_CPU_INTR_FROM_CPU_3_REG

• DPORT_PRO_INTR_STATUS_0_REG

• DPORT_PRO_INTR_STATUS_1_REG

• DPORT_PRO_INTR_STATUS_2_REG

• DPORT_APP_INTR_STATUS_0_REG

• DPORT_APP_INTR_STATUS_1_REG

• DPORT_APP_INTR_STATUS_2_REG

• DPORT_PRO_MAC_INTR_MAP_REG

• DPORT_PRO_MAC_NMI_MAP_REG

• DPORT_PRO_BB_INT_MAP_REG

• DPORT_PRO_BT_MAC_INT_MAP_REG

• DPORT_PRO_BT_BB_INT_MAP_REG

• DPORT_PRO_BT_BB_NMI_MAP_REG

• DPORT_PRO_RWBT_IRQ_MAP_REG

• DPORT_PRO_RWBLE_IRQ_MAP_REG

• DPORT_PRO_RWBT_NMI_MAP_REG

• DPORT_PRO_RWBLE_NMI_MAP_REG

• DPORT_PRO_SLC0_INTR_MAP_REG

• DPORT_PRO_SLC1_INTR_MAP_REG

• DPORT_PRO_UHCI0_INTR_MAP_REG

• DPORT_PRO_UHCI1_INTR_MAP_REG

• DPORT_PRO_TG_T0_LEVEL_INT_MAP_REG

• DPORT_PRO_TG_T1_LEVEL_INT_MAP_REG

• DPORT_PRO_TG_WDT_LEVEL_INT_MAP_REG

• DPORT_PRO_TG_LACT_LEVEL_INT_MAP_REG

• DPORT_PRO_TG1_T0_LEVEL_INT_MAP_REG

• DPORT_PRO_TG1_T1_LEVEL_INT_MAP_REG

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5. DPort Register

• DPORT_PRO_TG1_WDT_LEVEL_INT_MAP_REG

• DPORT_PRO_TG1_LACT_LEVEL_INT_MAP_REG

• DPORT_PRO_GPIO_INTERRUPT_MAP_REG

• DPORT_PRO_GPIO_INTERRUPT_NMI_MAP_REG

• DPORT_PRO_CPU_INTR_FROM_CPU_0_MAP_REG

• DPORT_PRO_CPU_INTR_FROM_CPU_1_MAP_REG

• DPORT_PRO_CPU_INTR_FROM_CPU_2_MAP_REG

• DPORT_PRO_CPU_INTR_FROM_CPU_3_MAP_REG

• DPORT_PRO_SPI_INTR_0_MAP_REG

• DPORT_PRO_SPI_INTR_1_MAP_REG

• DPORT_PRO_SPI_INTR_2_MAP_REG

• DPORT_PRO_SPI_INTR_3_MAP_REG

• DPORT_PRO_I2S0_INT_MAP_REG

• DPORT_PRO_I2S1_INT_MAP_REG

• DPORT_PRO_UART_INTR_MAP_REG

• DPORT_PRO_UART1_INTR_MAP_REG

• DPORT_PRO_UART2_INTR_MAP_REG

• DPORT_PRO_SDIO_HOST_INTERRUPT_MAP_REG

• DPORT_PRO_EMAC_INT_MAP_REG

• DPORT_PRO_PWM0_INTR_MAP_REG

• DPORT_PRO_PWM1_INTR_MAP_REG

• DPORT_PRO_PWM2_INTR_MAP_REG

• DPORT_PRO_PWM3_INTR_MAP_REG

• DPORT_PRO_LEDC_INT_MAP_REG

• DPORT_PRO_EFUSE_INT_MAP_REG

• DPORT_PRO_CAN_INT_MAP_REG

• DPORT_PRO_RTC_CORE_INTR_MAP_REG

• DPORT_PRO_RMT_INTR_MAP_REG

• DPORT_PRO_PCNT_INTR_MAP_REG

• DPORT_PRO_I2C_EXT0_INTR_MAP_REG

• DPORT_PRO_I2C_EXT1_INTR_MAP_REG

• DPORT_PRO_RSA_INTR_MAP_REG

• DPORT_PRO_SPI1_DMA_INT_MAP_REG

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5. DPort Register

• DPORT_PRO_SPI2_DMA_INT_MAP_REG

• DPORT_PRO_SPI3_DMA_INT_MAP_REG

• DPORT_PRO_WDG_INT_MAP_REG

• DPORT_PRO_TIMER_INT1_MAP_REG

• DPORT_PRO_TIMER_INT2_MAP_REG

• DPORT_PRO_TG_T0_EDGE_INT_MAP_REG

• DPORT_PRO_TG_T1_EDGE_INT_MAP_REG

• DPORT_PRO_TG_WDT_EDGE_INT_MAP_REG

• DPORT_PRO_TG_LACT_EDGE_INT_MAP_REG

• DPORT_PRO_TG1_T0_EDGE_INT_MAP_REG

• DPORT_PRO_TG1_T1_EDGE_INT_MAP_REG

• DPORT_PRO_TG1_WDT_EDGE_INT_MAP_REG

• DPORT_PRO_TG1_LACT_EDGE_INT_MAP_REG

• DPORT_PRO_MMU_IA_INT_MAP_REG

• DPORT_PRO_MPU_IA_INT_MAP_REG

• DPORT_PRO_CACHE_IA_INT_MAP_REG

• DPORT_APP_MAC_INTR_MAP_REG

• DPORT_APP_MAC_NMI_MAP_REG

• DPORT_APP_BB_INT_MAP_REG

• DPORT_APP_BT_MAC_INT_MAP_REG

• DPORT_APP_BT_BB_INT_MAP_REG

• DPORT_APP_BT_BB_NMI_MAP_REG

• DPORT_APP_RWBT_IRQ_MAP_REG

• DPORT_APP_RWBLE_IRQ_MAP_REG

• DPORT_APP_RWBT_NMI_MAP_REG

• DPORT_APP_RWBLE_NMI_MAP_REG

• DPORT_APP_SLC0_INTR_MAP_REG

• DPORT_APP_SLC1_INTR_MAP_REG

• DPORT_APP_UHCI0_INTR_MAP_REG

• DPORT_APP_UHCI1_INTR_MAP_REG

• DPORT_APP_TG_T0_LEVEL_INT_MAP_REG

• DPORT_APP_TG_T1_LEVEL_INT_MAP_REG

• DPORT_APP_TG_WDT_LEVEL_INT_MAP_REG

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5. DPort Register

• DPORT_APP_TG_LACT_LEVEL_INT_MAP_REG

• DPORT_APP_TG1_T0_LEVEL_INT_MAP_REG

• DPORT_APP_TG1_T1_LEVEL_INT_MAP_REG

• DPORT_APP_TG1_WDT_LEVEL_INT_MAP_REG

• DPORT_APP_TG1_LACT_LEVEL_INT_MAP_REG

• DPORT_APP_GPIO_INTERRUPT_MAP_REG

• DPORT_APP_GPIO_INTERRUPT_NMI_MAP_REG

• DPORT_APP_CPU_INTR_FROM_CPU_0_MAP_REG

• DPORT_APP_CPU_INTR_FROM_CPU_1_MAP_REG

• DPORT_APP_CPU_INTR_FROM_CPU_2_MAP_REG

• DPORT_APP_CPU_INTR_FROM_CPU_3_MAP_REG

• DPORT_APP_SPI_INTR_0_MAP_REG

• DPORT_APP_SPI_INTR_1_MAP_REG

• DPORT_APP_SPI_INTR_2_MAP_REG

• DPORT_APP_SPI_INTR_3_MAP_REG

• DPORT_APP_I2S0_INT_MAP_REG

• DPORT_APP_I2S1_INT_MAP_REG

• DPORT_APP_UART_INTR_MAP_REG

• DPORT_APP_UART1_INTR_MAP_REG

• DPORT_APP_UART2_INTR_MAP_REG

• DPORT_APP_SDIO_HOST_INTERRUPT_MAP_REG

• DPORT_APP_EMAC_INT_MAP_REG

• DPORT_APP_PWM0_INTR_MAP_REG

• DPORT_APP_PWM1_INTR_MAP_REG

• DPORT_APP_PWM2_INTR_MAP_REG

• DPORT_APP_PWM3_INTR_MAP_REG

• DPORT_APP_LEDC_INT_MAP_REG

• DPORT_APP_EFUSE_INT_MAP_REG

• DPORT_APP_CAN_INT_MAP_REG

• DPORT_APP_RTC_CORE_INTR_MAP_REG

• DPORT_APP_RMT_INTR_MAP_REG

• DPORT_APP_PCNT_INTR_MAP_REG

• DPORT_APP_I2C_EXT0_INTR_MAP_REG

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5. DPort Register

• DPORT_APP_I2C_EXT1_INTR_MAP_REG

• DPORT_APP_RSA_INTR_MAP_REG

• DPORT_APP_SPI1_DMA_INT_MAP_REG

• DPORT_APP_SPI2_DMA_INT_MAP_REG

• DPORT_APP_SPI3_DMA_INT_MAP_REG

• DPORT_APP_WDG_INT_MAP_REG

• DPORT_APP_TIMER_INT1_MAP_REG

• DPORT_APP_TIMER_INT2_MAP_REG

• DPORT_APP_TG_T0_EDGE_INT_MAP_REG

• DPORT_APP_TG_T1_EDGE_INT_MAP_REG

• DPORT_APP_TG_WDT_EDGE_INT_MAP_REG

• DPORT_APP_TG_LACT_EDGE_INT_MAP_REG

• DPORT_APP_TG1_T0_EDGE_INT_MAP_REG

• DPORT_APP_TG1_T1_EDGE_INT_MAP_REG

• DPORT_APP_TG1_WDT_EDGE_INT_MAP_REG

• DPORT_APP_TG1_LACT_EDGE_INT_MAP_REG

• DPORT_APP_MMU_IA_INT_MAP_REG

• DPORT_APP_MPU_IA_INT_MAP_REG

• DPORT_APP_CACHE_IA_INT_MAP_REG

5.3.4 DMA Registers

The following register is used for the SPI DMA configuration. For a detailed description of the register, please refer
to DMA.

• DPORT_SPI_DMA_CHAN_SEL_REG

5.3.5 PID/MPU/MMU Registers

The following registers are used for PID/MPU/MMU configuration and operation control. For a detailed
description of the registers, please refer to PID/MPU/MMU.

• DPORT_PRO_CACHE_CTRL_REG

• DPORT_APP_CACHE_CTRL_REG

• DPORT_IMMU_PAGE_MODE_REG

• DPORT_DMMU_PAGE_MODE_REG

• DPORT_AHB_MPU_TABLE_0_REG

• DPORT_AHB_MPU_TABLE_1_REG

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5. DPort Register

• DPORT_AHBLITE_MPU_TABLE_UART_REG

• DPORT_AHBLITE_MPU_TABLE_SPI1_REG

• DPORT_AHBLITE_MPU_TABLE_SPI0_REG

• DPORT_AHBLITE_MPU_TABLE_GPIO_REG

• DPORT_AHBLITE_MPU_TABLE_FE2_REG

• DPORT_AHBLITE_MPU_TABLE_FE_REG

• DPORT_AHBLITE_MPU_TABLE_TIMER_REG

• DPORT_AHBLITE_MPU_TABLE_RTC_REG

• DPORT_AHBLITE_MPU_TABLE_IO_MUX_REG

• DPORT_AHBLITE_MPU_TABLE_WDG_REG

• DPORT_AHBLITE_MPU_TABLE_HINF_REG

• DPORT_AHBLITE_MPU_TABLE_UHCI1_REG

• DPORT_AHBLITE_MPU_TABLE_I2S0_REG

• DPORT_AHBLITE_MPU_TABLE_UART1_REG

• DPORT_AHBLITE_MPU_TABLE_I2C_EXT0_REG

• DPORT_AHBLITE_MPU_TABLE_UHCI0_REG

• DPORT_AHBLITE_MPU_TABLE_SLCHOST_REG

• DPORT_AHBLITE_MPU_TABLE_RMT_REG

• DPORT_AHBLITE_MPU_TABLE_PCNT_REG

• DPORT_AHBLITE_MPU_TABLE_SLC_REG

• DPORT_AHBLITE_MPU_TABLE_LEDC_REG

• DPORT_AHBLITE_MPU_TABLE_EFUSE_REG

• DPORT_AHBLITE_MPU_TABLE_SPI_ENCRYPT_REG

• DPORT_AHBLITE_MPU_TABLE_PWM0_REG

• DPORT_AHBLITE_MPU_TABLE_TIMERGROUP_REG

• DPORT_AHBLITE_MPU_TABLE_TIMERGROUP1_REG

• DPORT_AHBLITE_MPU_TABLE_SPI2_REG

• DPORT_AHBLITE_MPU_TABLE_SPI3_REG

• DPORT_AHBLITE_MPU_TABLE_APB_CTRL_REG

• DPORT_AHBLITE_MPU_TABLE_I2C_EXT1_REG

• DPORT_AHBLITE_MPU_TABLE_SDIO_HOST_REG

• DPORT_AHBLITE_MPU_TABLE_EMAC_REG

• DPORT_AHBLITE_MPU_TABLE_PWM1_REG

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• DPORT_AHBLITE_MPU_TABLE_I2S1_REG

• DPORT_AHBLITE_MPU_TABLE_UART2_REG

• DPORT_AHBLITE_MPU_TABLE_PWM2_REG

• DPORT_AHBLITE_MPU_TABLE_PWM3_REG

• DPORT_AHBLITE_MPU_TABLE_PWR_REG

• DPORT_IMMU_TABLE0_REG

• DPORT_IMMU_TABLE1_REG

• DPORT_IMMU_TABLE2_REG

• DPORT_IMMU_TABLE3_REG

• DPORT_IMMU_TABLE4_REG

• DPORT_IMMU_TABLE5_REG

• DPORT_IMMU_TABLE6_REG

• DPORT_IMMU_TABLE7_REG

• DPORT_IMMU_TABLE8_REG

• DPORT_IMMU_TABLE9_REG

• DPORT_IMMU_TABLE10_REG

• DPORT_IMMU_TABLE11_REG

• DPORT_IMMU_TABLE12_REG

• DPORT_IMMU_TABLE13_REG

• DPORT_IMMU_TABLE14_REG

• DPORT_IMMU_TABLE15_REG

• DPORT_DMMU_TABLE0_REG

• DPORT_DMMU_TABLE1_REG

• DPORT_DMMU_TABLE2_REG

• DPORT_DMMU_TABLE3_REG

• DPORT_DMMU_TABLE4_REG

• DPORT_DMMU_TABLE5_REG

• DPORT_DMMU_TABLE6_REG

• DPORT_DMMU_TABLE7_REG

• DPORT_DMMU_TABLE8_REG

• DPORT_DMMU_TABLE9_REG

• DPORT_DMMU_TABLE10_REG

• DPORT_DMMU_TABLE11_REG

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• DPORT_DMMU_TABLE12_REG

• DPORT_DMMU_TABLE13_REG

• DPORT_DMMU_TABLE14_REG

• DPORT_DMMU_TABLE15_REG

5.3.6 APP_CPU Controller Registers

DPort registers are used for some basic configuration of the APP_CPU, such as performing a stalling execution,
and for configuring the ROM boot jump address.

• APP_CPU is reset when DPORT_APPCPU_RESETTING=1. It is released when

DPORT_APPCPU_RESETTING=0.

• When DPORT_APPCPU_CLKGATE_EN=0, the APP_CPU clock can be disabled to reduce power

consumption.

• When DPORT_APPCPU_RUNSTALL=1, the APP_CPU can be put into a stalled state.

• When APP_CPU is booted up with a ROM code, it will jump to the address stored in the
DPORT_APPCPU_BOOT_ADDR register.

5.3.7 Peripheral Clock Gating and Reset

Reset and clock gating registers covered in this section are active-high registers. Note that the reset bits are not
self-cleared by hardware. When a clock-gating register bit is set to 1, the corresponding clock is enabled. Setting
the register bit to 0 disables the clock. Setting a reset register bit to 1 puts the peripheral in a reset state, while
setting the register bit to 0 disables the reset state, thus enabling normal operation.

• DPORT_PERI_CLK_EN_REG: enables the hardware accelerator clock.

– BIT4, Digital Signature

– BIT3, Secure boot

– BIT2, RSA Accelerator

– BIT1, SHA Accelerator

– BIT0, AES Accelerator

• DPORT_PERI_RST_EN_REG: resets the accelerator.

– BIT4, Digital Signature

AES Accelerator and RSA Accelerator will also be reset.

– BIT3, Secure boot

AES Accelerator and SHA Accelerator will also be reset.

– BIT2, RSA Accelerator

– BIT1, SHA Accelerator

– BIT0, AES Accelerator

• DPORT_PERIP_CLK_EN_REG=1: enables the peripheral clock.

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5. DPort Register

– BIT26, PWM3

– BIT25, PWM2

– BIT24, UART MEM

All UART-shared memory. As long as a UART is working, the UART memory clock cannot be in the
gating state.

– BIT23, UART2

– BIT22, SPI_DMA

– BIT21, I2S1

– BIT20, PWM1

– BIT19, CAN

– BIT18, I2C1

– BIT17, PWM0

– BIT16, SPI3

– BIT15, Timer Group1

– BIT14, eFuse

– BIT13, Timer Group0

– BIT12, UHCI1

– BIT11, LED_PWM

– BIT10, PULSE_CNT

– BIT9, Remote Controller

– BIT8, UHCI0

– BIT7, I2C0

– BIT6, SPI2

– BIT5, UART1

– BIT4, I2S0

– BIT3, WDG

– BIT2, UART

– BIT1, SPI

– BIT0, Timers

• DPORT_PERIP_RST_EN_REG: resets peripherals

– BIT26, PWM3

– BIT25, PWM2

– BIT24, UART MEM

– BIT23, UART2

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5. DPort Register

– BIT22, SPI_DMA

– BIT21, I2S1

– BIT20, PWM1

– BIT19, CAN

– BIT18, I2C1

– BIT17, PWM0

– BIT16, SPI3

– BIT15, Timer Group1

– BIT14, eFuse

– BIT13, Timer Group0

– BIT12, UHCI1

– BIT11, LED_PWM

– BIT10, PULSE_CNT

– BIT9, Remote Controller

– BIT8, UHCI0

– BIT7, I2C0

– BIT6, SPI2

– BIT5, UART1

– BIT4, I2S0

– BIT3, WDG

– BIT2, UART

– BIT1, SPI

– BIT0, Timers

• DPORT_WIFI_CLK_EN_REG: used for Wi-Fi and BT clock gating.

• DPORT_WIFI_RST_EN_REG: used for Wi-Fi and BT reset.

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5.4 Register Summary

Name Description Address Access

PRO_BOOT_REMAP_CTRL_REG remap mode for PRO_CPU 0x3FF00000 R/W
APP_BOOT_REMAP_CTRL_REG remap mode for APP_CPU 0x3FF00004 R/W
PERI_CLK_EN_REG clock gate for peripherals 0x3FF0001C R/W
PERI_RST_EN_REG reset for peripherals 0x3FF00020 R/W
APPCPU_CTRL_REG_A_REG reset for APP_CPU 0x3FF0002C R/W
APPCPU_CTRL_REG_B_REG clock gate for APP_CPU 0x3FF00030 R/W
APPCPU_CTRL_REG_C_REG stall for APP_CPU 0x3FF00034 R/W
APPCPU_CTRL_REG_D_REG boot address for APP_CPU 0x3FF00038 R/W
determines the virtual address mode
PRO_CACHE_CTRL_REG 0x3FF00040 R/W
of the external SRAM
determines the virtual address mode
APP_CACHE_CTRL_REG 0x3FF00058 R/W
of the external SRAM
the mode of the two caches sharing
CACHE_MUX_MODE_REG 0x3FF0007C R/W
the memory
page size in the MMU for the internal
IMMU_PAGE_MODE_REG 0x3FF00080 R/W
SRAM 0
page size in the MMU for the internal
DMMU_PAGE_MODE_REG 0x3FF00084 R/W
SRAM 2
SRAM_PD_CTRL_REG_0_REG powers down internal SRAM_REG 0x3FF00098 R/W
SRAM_PD_CTRL_REG_1_REG powers down internal SRAM_REG 0x3FF0009C R/W
AHB_MPU_TABLE_0_REG MPU for configuring DMA 0x3FF000B4 R/W
AHB_MPU_TABLE_1_REG MPU for configuring DMA 0x3FF000B8 R/W
PERIP_CLK_EN_REG clock gate for peripherals 0x3FF000C0 R/W
PERIP_RST_EN_REG reset for peripherals 0x3FF000C4 R/W
SLAVE_SPI_CONFIG_REG enables decryption in external flash 0x3FF000C8 R/W
WIFI_CLK_EN_REG clock gate for Wi-Fi 0x3FF000CC R/W
WIFI_RST_EN_REG reset for Wi-Fi 0x3FF000D0 R/W
CPU_INTR_FROM_CPU_0_REG interrupt 0 in both CPUs 0x3FF000DC R/W
CPU_INTR_FROM_CPU_1_REG interrupt 1 in both CPUs 0x3FF000E0 R/W
CPU_INTR_FROM_CPU_2_REG interrupt 2 in both CPUs 0x3FF000E4 R/W
CPU_INTR_FROM_CPU_3_REG interrupt 3 in both CPUs 0x3FF000E8 R/W
PRO_INTR_STATUS_REG_0_REG PRO_CPU interrupt status 0 0x3FF000EC RO
PRO_INTR_STATUS_REG_1_REG PRO_CPU interrupt status 1 0x3FF000F0 RO
PRO_INTR_STATUS_REG_2_REG PRO_CPU interrupt status 2 0x3FF000F4 RO
APP_INTR_STATUS_REG_0_REG APP_CPU interrupt status 0 0x3FF000F8 RO
APP_INTR_STATUS_REG_1_REG APP_CPU interrupt status 1 0x3FF000FC RO
APP_INTR_STATUS_REG_2_REG APP_CPU interrupt status 2 0x3FF00100 RO
PRO_MAC_INTR_MAP_REG interrupt map 0x3FF00104 R/W
PRO_MAC_NMI_MAP_REG interrupt map 0x3FF00108 R/W
PRO_BB_INT_MAP_REG interrupt map 0x3FF0010C R/W

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Name Description Address Access

PRO_BT_MAC_INT_MAP_REG interrupt map 0x3FF00110 R/W
PRO_BT_BB_INT_MAP_REG interrupt map 0x3FF00114 R/W
PRO_BT_BB_NMI_MAP_REG interrupt map 0x3FF00118 R/W
PRO_RWBT_IRQ_MAP_REG interrupt map 0x3FF0011C R/W
PRO_RWBLE_IRQ_MAP_REG interrupt map 0x3FF00120 R/W
PRO_RWBT_NMI_MAP_REG interrupt map 0x3FF00124 R/W
PRO_RWBLE_NMI_MAP_REG interrupt map 0x3FF00128 R/W
PRO_SLC0_INTR_MAP_REG interrupt map 0x3FF0012C R/W
PRO_SLC1_INTR_MAP_REG interrupt map 0x3FF00130 R/W
PRO_UHCI0_INTR_MAP_REG interrupt map 0x3FF00134 R/W
PRO_UHCI1_INTR_MAP_REG interrupt map 0x3FF00138 R/W
PRO_TG_T0_LEVEL_INT_MAP_REG interrupt map 0x3FF0013C R/W
PRO_TG_T1_LEVEL_INT_MAP_REG interrupt map 0x3FF00140 R/W
PRO_TG_WDT_LEVEL_INT_MAP_REG interrupt map 0x3FF00144 R/W
PRO_TG_LACT_LEVEL_INT_MAP_REG interrupt map 0x3FF00148 R/W
PRO_TG1_T0_LEVEL_INT_MAP_REG interrupt map 0x3FF0014C R/W
PRO_TG1_T1_LEVEL_INT_MAP_REG interrupt map 0x3FF00150 R/W
PRO_TG1_WDT_LEVEL_INT_MAP_REG interrupt map 0x3FF00154 R/W
PRO_TG1_LACT_LEVEL_INT_MAP_REG interrupt map 0x3FF00158 R/W
PRO_GPIO_INTERRUPT_MAP_REG interrupt map 0x3FF0015C R/W
PRO_GPIO_INTERRUPT_NMI_MAP_REG interrupt map 0x3FF00160 R/W
PRO_CPU_INTR_FROM_CPU_0_MAP_REG interrupt map 0x3FF00164 R/W
PRO_CPU_INTR_FROM_CPU_1_MAP_REG interrupt map 0x3FF00168 R/W
PRO_CPU_INTR_FROM_CPU_2_MAP_REG Interrupt map 0x3FF0016C R/W
PRO_CPU_INTR_FROM_CPU_3_MAP_REG interrupt map 0x3FF00170 R/W
PRO_SPI_INTR_0_MAP_REG interrupt map 0x3FF00174 R/W
PRO_SPI_INTR_1_MAP_REG interrupt map 0x3FF00178 R/W
PRO_SPI_INTR_2_MAP_REG interrupt map 0x3FF0017C R/W
PRO_SPI_INTR_3_MAP_REG interrupt map 0x3FF00180 R/W
PRO_I2S0_INT_MAP_REG interrupt map 0x3FF00184 R/W
PRO_I2S1_INT_MAP_REG interrupt map 0x3FF00188 R/W
PRO_UART_INTR_MAP_REG interrupt map 0x3FF0018C R/W
PRO_UART1_INTR_MAP_REG interrupt map 0x3FF00190 R/W
PRO_UART2_INTR_MAP_REG interrupt map 0x3FF00194 R/W
PRO_SDIO_HOST_INTERRUPT_MAP_REG interrupt map 0x3FF00198 R/W
PRO_EMAC_INT_MAP_REG interrupt map 0x3FF0019C R/W
PRO_PWM0_INTR_MAP_REG interrupt map 0x3FF001A0 R/W
PRO_PWM1_INTR_MAP_REG interrupt map 0x3FF001A4 R/W
PRO_PWM2_INTR_MAP_REG interrupt map 0x3FF001A8 R/W
PRO_PWM3_INTR_MAP_REG interrupt map 0x3FF001AC R/W
PRO_LEDC_INT_MAP_REG interrupt map 0x3FF001B0 R/W
PRO_EFUSE_INT_MAP_REG interrupt map 0x3FF001B4 R/W

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Name Description Address Access

PRO_CAN_INT_MAP_REG interrupt map 0x3FF001B8 R/W
PRO_RTC_CORE_INTR_MAP_REG interrupt map 0x3FF001BC R/W
PRO_RMT_INTR_MAP_REG interrupt map 0x3FF001C0 R/W
PRO_PCNT_INTR_MAP_REG interrupt map 0x3FF001C4 R/W
PRO_I2C_EXT0_INTR_MAP_REG interrupt map 0x3FF001C8 R/W
PRO_I2C_EXT1_INTR_MAP_REG interrupt map 0x3FF001CC R/W
PRO_RSA_INTR_MAP_REG interrupt map 0x3FF001D0 R/W
PRO_SPI1_DMA_INT_MAP_REG interrupt map 0x3FF001D4 R/W
PRO_SPI2_DMA_INT_MAP_REG interrupt map 0x3FF001D8 R/W
PRO_SPI3_DMA_INT_MAP_REG interrupt map 0x3FF001DC R/W
PRO_WDG_INT_MAP_REG interrupt map 0x3FF001E0 R/W
PRO_TIMER_INT1_MAP_REG interrupt map 0x3FF001E4 R/W
PRO_TIMER_INT2_MAP_REG interrupt map 0x3FF001E8 R/W
PRO_TG_T0_EDGE_INT_MAP_REG interrupt map 0x3FF001EC R/W
PRO_TG_T1_EDGE_INT_MAP_REG interrupt map 0x3FF001F0 R/W
PRO_TG_WDT_EDGE_INT_MAP_REG interrupt map 0x3FF001F4 R/W
PRO_TG_LACT_EDGE_INT_MAP_REG interrupt map 0x3FF001F8 R/W
PRO_TG1_T0_EDGE_INT_MAP_REG interrupt map 0x3FF001FC R/W
PRO_TG1_T1_EDGE_INT_MAP_REG interrupt map 0x3FF00200 R/W
PRO_TG1_WDT_EDGE_INT_MAP_REG interrupt map 0x3FF00204 R/W
PRO_TG1_LACT_EDGE_INT_MAP_REG interrupt map 0x3FF00208 R/W
PRO_MMU_IA_INT_MAP_REG interrupt map 0x3FF0020C R/W
PRO_MPU_IA_INT_MAP_REG interrupt map 0x3FF00210 R/W
PRO_CACHE_IA_INT_MAP_REG interrupt map 0x3FF00214 R/W
APP_MAC_INTR_MAP_REG interrupt map 0x3FF00218 R/W
APP_MAC_NMI_MAP_REG interrupt map 0x3FF0021C R/W
APP_BB_INT_MAP_REG interrupt map 0x3FF00220 R/W
APP_BT_MAC_INT_MAP_REG interrupt map 0x3FF00224 R/W
APP_BT_BB_INT_MAP_REG interrupt map 0x3FF00228 R/W
APP_BT_BB_NMI_MAP_REG interrupt map 0x3FF0022C R/W
APP_RWBT_IRQ_MAP_REG interrupt map 0x3FF00230 R/W
APP_RWBLE_IRQ_MAP_REG interrupt map 0x3FF00234 R/W
APP_RWBT_NMI_MAP_REG interrupt map 0x3FF00238 R/W
APP_RWBLE_NMI_MAP_REG interrupt map 0x3FF0023C R/W
APP_SLC0_INTR_MAP_REG interrupt map 0x3FF00240 R/W
APP_SLC1_INTR_MAP_REG interrupt map 0x3FF00244 R/W
APP_UHCI0_INTR_MAP_REG interrupt map 0x3FF00248 R/W
APP_UHCI1_INTR_MAP_REG interrupt map 0x3FF0024C R/W
APP_TG_T0_LEVEL_INT_MAP_REG interrupt map 0x3FF00250 R/W
APP_TG_T1_LEVEL_INT_MAP_REG interrupt map 0x3FF00254 R/W
APP_TG_WDT_LEVEL_INT_MAP_REG interrupt map 0x3FF00258 R/W
APP_TG_LACT_LEVEL_INT_MAP_REG interrupt map 0x3FF0025C R/W

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5. DPort Register

Name Description Address Access

APP_TG1_T0_LEVEL_INT_MAP_REG interrupt map 0x3FF00260 R/W
APP_TG1_T1_LEVEL_INT_MAP_REG interrupt map 0x3FF00264 R/W
APP_TG1_WDT_LEVEL_INT_MAP_REG interrupt map 0x3FF00268 R/W
APP_TG1_LACT_LEVEL_INT_MAP_REG interrupt map 0x3FF0026C R/W
APP_GPIO_INTERRUPT_MAP_REG interrupt map 0x3FF00270 R/W
APP_GPIO_INTERRUPT_NMI_MAP_REG interrupt map 0x3FF00274 R/W
APP_CPU_INTR_FROM_CPU_0_MAP_REG interrupt map 0x3FF00278 R/W
APP_CPU_INTR_FROM_CPU_1_MAP_REG interrupt map 0x3FF0027C R/W
APP_CPU_INTR_FROM_CPU_2_MAP_REG interrupt map 0x3FF00280 R/W
APP_CPU_INTR_FROM_CPU_3_MAP_REG interrupt map 0x3FF00284 R/W
APP_SPI_INTR_0_MAP_REG interrupt map 0x3FF00288 R/W
APP_SPI_INTR_1_MAP_REG interrupt map 0x3FF0028C R/W
APP_SPI_INTR_2_MAP_REG interrupt map 0x3FF00290 R/W
APP_SPI_INTR_3_MAP_REG interrupt map 0x3FF00294 R/W
APP_I2S0_INT_MAP_REG interrupt map 0x3FF00298 R/W
APP_I2S1_INT_MAP_REG interrupt map 0x3FF0029C R/W
APP_UART_INTR_MAP_REG interrupt map 0x3FF002A0 R/W
APP_UART1_INTR_MAP_REG interrupt map 0x3FF002A4 R/W
APP_UART2_INTR_MAP_REG interrupt map 0x3FF002A8 R/W
APP_SDIO_HOST_INTERRUPT_MAP_REG interrupt map 0x3FF002AC R/W
APP_EMAC_INT_MAP_REG interrupt map 0x3FF002B0 R/W
APP_PWM0_INTR_MAP_REG interrupt map 0x3FF002B4 R/W
APP_PWM1_INTR_MAP_REG interrupt map 0x3FF002B8 R/W
APP_PWM2_INTR_MAP_REG interrupt map 0x3FF002BC R/W
APP_PWM3_INTR_MAP_REG interrupt map 0x3FF002C0 R/W
APP_LEDC_INT_MAP_REG interrupt map 0x3FF002C4 R/W
APP_EFUSE_INT_MAP_REG interrupt map 0x3FF002C8 R/W
APP_CAN_INT_MAP_REG interrupt map 0x3FF002CC R/W
APP_RTC_CORE_INTR_MAP_REG interrupt map 0x3FF002D0 R/W
APP_RMT_INTR_MAP_REG interrupt map 0x3FF002D4 R/W
APP_PCNT_INTR_MAP_REG interrupt map 0x3FF002D8 R/W
APP_I2C_EXT0_INTR_MAP_REG interrupt map 0x3FF002DC R/W
APP_I2C_EXT1_INTR_MAP_REG interrupt map 0x3FF002E0 R/W
APP_RSA_INTR_MAP_REG interrupt map 0x3FF002E4 R/W
APP_SPI1_DMA_INT_MAP_REG interrupt map 0x3FF002E8 R/W
APP_SPI2_DMA_INT_MAP_REG interrupt map 0x3FF002EC R/W
APP_SPI3_DMA_INT_MAP_REG interrupt map 0x3FF002F0 R/W
APP_WDG_INT_MAP_REG interrupt map 0x3FF002F4 R/W
APP_TIMER_INT1_MAP_REG interrupt map 0x3FF002F8 R/W
APP_TIMER_INT2_MAP_REG interrupt map 0x3FF002FC R/W
APP_TG_T0_EDGE_INT_MAP_REG interrupt map 0x3FF00300 R/W
APP_TG_T1_EDGE_INT_MAP_REG interrupt map 0x3FF00304 R/W

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5. DPort Register

Name Description Address Access

APP_TG_WDT_EDGE_INT_MAP_REG interrupt map 0x3FF00308 R/W
APP_TG_LACT_EDGE_INT_MAP_REG interrupt map 0x3FF0030C R/W
APP_TG1_T0_EDGE_INT_MAP_REG interrupt map 0x3FF00310 R/W
APP_TG1_T1_EDGE_INT_MAP_REG interrupt map 0x3FF00314 R/W
APP_TG1_WDT_EDGE_INT_MAP_REG interrupt map 0x3FF00318 R/W
APP_TG1_LACT_EDGE_INT_MAP_REG interrupt map 0x3FF0031C R/W
APP_MMU_IA_INT_MAP_REG interrupt map 0x3FF00320 R/W
APP_MPU_IA_INT_MAP_REG interrupt map 0x3FF00324 R/W
APP_CACHE_IA_INT_MAP_REG interrupt map 0x3FF00328 R/W
AHBLITE_MPU_TABLE_UART_REG MPU for peripherals 0x3FF0032C R/W
AHBLITE_MPU_TABLE_SPI1_REG MPU for peripherals 0x3FF00330 R/W
AHBLITE_MPU_TABLE_SPI0_REG MPU for peripherals 0x3FF00334 R/W
AHBLITE_MPU_TABLE_GPIO_REG MPU for peripherals 0x3FF00338 R/W
AHBLITE_MPU_TABLE_RTC_REG MPU for peripherals 0x3FF00348 R/W
AHBLITE_MPU_TABLE_IO_MUX_REG MPU for peripherals 0x3FF0034C R/W
AHBLITE_MPU_TABLE_HINF_REG MPU for peripherals 0x3FF00354 R/W
AHBLITE_MPU_TABLE_UHCI1_REG MPU for peripherals 0x3FF00358 R/W
AHBLITE_MPU_TABLE_I2S0_REG MPU for peripherals 0x3FF00364 R/W
AHBLITE_MPU_TABLE_UART1_REG MPU for peripherals 0x3FF00368 R/W
AHBLITE_MPU_TABLE_I2C_EXT0_REG MPU for peripherals 0x3FF00374 R/W
AHBLITE_MPU_TABLE_UHCI0_REG MPU for peripherals 0x3FF00378 R/W
AHBLITE_MPU_TABLE_SLCHOST_REG MPU for peripherals 0x3FF0037C R/W
AHBLITE_MPU_TABLE_RMT_REG MPU for peripherals 0x3FF00380 R/W
AHBLITE_MPU_TABLE_PCNT_REG MPU for peripherals 0x3FF00384 R/W
AHBLITE_MPU_TABLE_SLC_REG MPU for peripherals 0x3FF00388 R/W
AHBLITE_MPU_TABLE_LEDC_REG MPU for peripherals 0x3FF0038C R/W
AHBLITE_MPU_TABLE_EFUSE_REG MPU for peripherals 0x3FF00390 R/W
AHBLITE_MPU_TABLE_SPI_ENCRYPT_REG MPU for peripherals 0x3FF00394 R/W
AHBLITE_MPU_TABLE_PWM0_REG MPU for peripherals 0x3FF0039C R/W
AHBLITE_MPU_TABLE_TIMERGROUP_REG MPU for peripherals 0x3FF003A0 R/W
AHBLITE_MPU_TABLE_TIMERGROUP1_REG MPU for peripherals 0x3FF003A4 R/W
AHBLITE_MPU_TABLE_SPI2_REG MPU for peripherals 0x3FF003A8 R/W
AHBLITE_MPU_TABLE_SPI3_REG MPU for peripherals 0x3FF003AC R/W
AHBLITE_MPU_TABLE_APB_CTRL_REG MPU for peripherals 0x3FF003B0 R/W
AHBLITE_MPU_TABLE_I2C_EXT1_REG MPU for peripherals 0x3FF003B4 R/W
AHBLITE_MPU_TABLE_SDIO_HOST_REG MPU for peripherals 0x3FF003B8 R/W
AHBLITE_MPU_TABLE_EMAC_REG MPU for peripherals 0x3FF003BC R/W
AHBLITE_MPU_TABLE_PWM1_REG MPU for peripherals 0x3FF003C4 R/W
AHBLITE_MPU_TABLE_I2S1_REG MPU for peripherals 0x3FF003C8 R/W
AHBLITE_MPU_TABLE_UART2_REG MPU for peripherals 0x3FF003CC R/W
AHBLITE_MPU_TABLE_PWM2_REG MPU for peripherals 0x3FF003D0 R/W
AHBLITE_MPU_TABLE_PWM3_REG MPU for peripherals 0x3FF003D4 R/W

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5. DPort Register

Name Description Address Access

AHBLITE_MPU_TABLE_PWR_REG MPU for peripherals 0x3FF003E4 R/W
IMMU_TABLE0_REG MMU register 1 for internal SRAM 0 0x3FF00504 R/W
IMMU_TABLE1_REG MMU register 1 for internal SRAM 0 0x3FF00508 R/W
IMMU_TABLE2_REG MMU register 1 for Internal SRAM 0 0x3FF0050C R/W
IMMU_TABLE3_REG MMU register 1 for internal SRAM 0 0x3FF00510 R/W
IMMU_TABLE4_REG MMU register 1 for internal SRAM 0 0x3FF00514 R/W
IMMU_TABLE5_REG MMU register 1 for internal SRAM 0 0x3FF00518 R/W
IMMU_TABLE6_REG MMU register 1 for internal SRAM 0 0x3FF0051C R/W
IMMU_TABLE7_REG MMU register 1 for internal SRAM 0 0x3FF00520 R/W
IMMU_TABLE8_REG MMU register 1 for internal SRAM 0 0x3FF00524 R/W
IMMU_TABLE9_REG MMU register 1 for internal SRAM 0 0x3FF00528 R/W
IMMU_TABLE10_REG MMU register 1 for internal SRAM 0 0x3FF0052C R/W
IMMU_TABLE11_REG MMU register 1 for internal SRAM 0 0x3FF00530 R/W
IMMU_TABLE12_REG MMU register 1 for Internal SRAM 0 0x3FF00534 R/W
IMMU_TABLE13_REG MMU register 1 for internal SRAM 0 0x3FF00538 R/W
IMMU_TABLE14_REG MMU register 1 for internal SRAM 0 0x3FF0053C R/W
IMMU_TABLE15_REG MMU register 1 for internal SRAM 0 0x3FF00540 R/W
DMMU_TABLE0_REG MMU register 1 for Internal SRAM 2 0x3FF00544 R/W
DMMU_TABLE1_REG MMU register 1 for internal SRAM 2 0x3FF00548 R/W
DMMU_TABLE2_REG MMU register 1 for internal SRAM 2 0x3FF0054C R/W
DMMU_TABLE3_REG MMU register 1 for internal SRAM 2 0x3FF00550 R/W
DMMU_TABLE4_REG MMU register 1 for internal SRAM 2 0x3FF00554 R/W
DMMU_TABLE5_REG MMU register 1 for internal SRAM 2 0x3FF00558 R/W
DMMU_TABLE6_REG MMU register 1 for internal SRAM 2 0x3FF0055C R/W
DMMU_TABLE7_REG MMU register 1 for internal SRAM 2 0x3FF00560 R/W
DMMU_TABLE8_REG MMU register 1 for internal SRAM 2 0x3FF00564 R/W
DMMU_TABLE9_REG MMU register 1 for internal SRAM 2 0x3FF00568 R/W
DMMU_TABLE10_REG MMU register 1 for internal SRAM 2 0x3FF0056C R/W
DMMU_TABLE11_REG MMU register 1 for internal SRAM 2 0x3FF00570 R/W
DMMU_TABLE12_REG MMU register 1 for internal SRAM 2 0x3FF00574 R/W
DMMU_TABLE13_REG MMU register 1 for internal SRAM 2 0x3FF00578 R/W
DMMU_TABLE14_REG MMU register 1 for internal SRAM 2 0x3FF0057C R/W
DMMU_TABLE15_REG MMU register 1 for internal SRAM 2 0x3FF00580 R/W
SECURE_BOOT_CTRL_REG mode for secure_boot 0x3FF005A4 R/W
selects DMA channel for SPI1, SPI2,
SPI_DMA_CHAN_SEL_REG 0x3FF005A8 R/W
and SPI3

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5. DPort Register

5.5 Registers

Register 5.1: PRO_BOOT_REMAP_CTRL_REG (0x000)

AP
M
RE
T_
O
d)

O
ve

_B
r
se

O
PR
(re
31 1 0

0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Reset

PRO_BOOT_REMAP Remap mode for PRO_CPU. (R/W)

Register 5.2: APP_BOOT_REMAP_CTRL_REG (0x004)

AP
M
RE
T_
O
d)

BO
e
rv

P_
se

AP
(re

31 1 0

0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Reset

APP_BOOT_REMAP Remap mode for APP_CPU. (R/W)

Register 5.3: PERI_CLK_EN_REG (0x01C)

31 0

0x000000000 Reset

PERI_CLK_EN_REG Clock gate for peripherals. (R/W)

Register 5.4: PERI_RST_EN_REG (0x020)

31 0

0x000000000 Reset

PERI_RST_EN_REG Reset for peripherals. (R/W)

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5. DPort Register

Register 5.5: APPCPU_CTRL_REG_A_REG (0x02C)

NG
TI
ET
ES
_R
d)

PU
ve

PC
ser

AP
(re
31 1 0

0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 Reset

APPCPU_RESETTING Reset for APP_CPU. (R/W)

Register 5.6: APPCPU_CTRL_REG_B_REG (0x030)

N
E_E
AT
G
LK
_C
d)

PU
e
rv

PC
se

AP
(re

31 1 0

0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Reset

APPCPU_CLKGATE_EN Clock gate for APP_CPU. (R/W)

Register 5.7: APPCPU_CTRL_REG_C_REG (0x034)

L
AL
ST
UN
_R
d)

PU
ve

PC
r
se

AP
(re

31 1 0

0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Reset

APPCPU_RUNSTALL Stall for APP_CPU. (R/W)

Register 5.8: APPCPU_CTRL_REG_D_REG (0x038)

31 0

0x000000000 Reset

APPCPU_CTRL_REG_D_REG Boot address for APP_CPU. (R/W)

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5. DPort Register

Register 5.9: CPU_PER_CONF_REG (0x03C)

EL
S
D_
O
RI
E
UP
)
ed

CP
rv

U_
se

CP
(re
31 2 1 0

0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Reset

CPU_CPUPERIOD_SEL Select CPU clock. (R/W)

Register 5.10: PRO_CACHE_CTRL_REG (0x040)

NA _E NE
BL NA
_E SH DO
NA

E
HE FLU H_
_E
M

AC E_ US
_I T
RA
LE LI

_C H L
G P
L

O AC _F
_H

IN _S

PR _C HE
AM

_S M

O AC
O RA
)

)
ed

ed

ed

ed
R

PR _C
_D

PR _D
rv

rv

rv

rv
se

se

se

se
O

O
PR

PR

PR
(re

(re

(re

(re
31 17 16 15 12 11 10 9 6 5 4 3 2 0

0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 Reset

PRO_DRAM_HL Determines the virtual address mode of the external SRAM. (R/W)

PRO_DRAM_SPLIT Determines the virtual address mode of the external SRAM. (R/W)

PRO_SINGLE_IRAM_ENA Determines a special mode for PRO_CPU access to the external flash.
(R/W)

PRO_CACHE_FLUSH_DONE PRO_CPU cache-flush done. (RO)

PRO_CACHE_FLUSH_ENA Flushes the PRO_CPU cache. (R/W)

PRO_CACHE_ENABLE Enables the PRO_CPU cache. (R/W)

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5. DPort Register

Register 5.11: APP_CACHE_CTRL_REG (0x058)

AB _EN E
EN H ON
LE A
NA

E_ LUS _D
_E

CH _F SH
M
_I T

CA HE LU
RA
LE PLI
L

P_ AC _F
_H

NG S

AP _C HE
SI M_
M

P AC
(re RA

P_ RA
d)

d)

)
ed

ed
ve

AP _C
D

AP D
rv

rv

rv
r

P_

P_
se

se

se

se
P
AP

AP

AP
(re

(re

(re
31 15 14 13 12 11 10 9 6 5 4 3 2 0

0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 Reset

APP_DRAM_HL Determines the virtual address mode of the External SRAM. (R/W)

APP_DRAM_SPLIT Determines the virtual address mode of the External SRAM. (R/W)

APP_SINGLE_IRAM_ENA Determines a special mode for APP_CPU access to the external flash.
(R/W)

APP_CACHE_FLUSH_DONE APP_CPU cache-flush done. (RO)

APP_CACHE_FLUSH_ENA Flushes the APP_CPU cache. (R/W)

APP_CACHE_ENABLE Enables the APP_CPU cache. (R/W)

Register 5.12: CACHE_MUX_MODE_REG (0x07C)

DE
O
_M
UX
M
d)

E_
e
rv

CH
se

CA
(re

31 2 1 0

0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Reset

CACHE_MUX_MODE The mode of the two caches sharing the memory. (R/W)

Register 5.13: IMMU_PAGE_MODE_REG (0x080)

DE
O
M
E_
G
PA
d)

d)
e

e
U_
rv

rv
se

se
M
(re

(re
IM

31 3 2 1 0

0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Reset

IMMU_PAGE_MODE Page size in the MMU for the internal SRAM 0. (R/W)

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5. DPort Register

Register 5.14: DMMU_PAGE_MODE_REG (0x084)

DE
O
ed _M
E
se AG
d)

)
P
U_
ve

rv
er

M
s

DM
(re

(re
31 3 2 1 0

0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Reset

DMMU_PAGE_MODE Page size in the MMU for the internal SRAM 2. (R/W)

Register 5.15: SRAM_PD_CTRL_REG_0_REG (0x098)

31 0

0x000000000 Reset

SRAM_PD_CTRL_REG_0_REG Powers down the internal SRAM. (R/W)

Register 5.16: SRAM_PD_CTRL_REG_1_REG (0x09C)

D_1
d)

_P
ve

AM
r
se

SR
(re

31 1 0

0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Reset

SRAM_PD_1 Powers down the internal SRAM. (R/W)

Register 5.17: AHB_MPU_TABLE_0_REG (0x0B4)

31 0

0x0FFFFFFFF Reset

AHB_MPU_TABLE_0_REG MPU for DMA. (R/W)

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5. DPort Register

Register 5.18: AHB_MPU_TABLE_1_REG (0x0B8)

1_
NT
RA
G
S S_
CE
)
ed

AC
rv

B_
se

AH
(re
31 9 8 0

0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0x1FF Reset

AHB_ACCESS_GRANT_1 MPU for DMA. (R/W)

Register 5.19: PERIP_CLK_EN_REG (0x0C0)

31 0

0x0F9C1E06F Reset

PERIP_CLK_EN_REG Clock gate for peripherals. (R/W)

Register 5.20: PERIP_RST_EN_REG (0x0C4)

31 0

0x000000000 Reset

PERIP_RST_EN_REG Reset for peripherals. (R/W)

Register 5.21: SLAVE_SPI_CONFIG_REG (0x0C8)

LE
LE

AB
AB

EN
EN

T_
T_

YP
YP

CR
CR

EN
DE
I_

I_
SP

SP
d)

)
ed

ed
E_

E_
e
rv

rv

rv
AV

AV
se

se

se
SL

SL
(re

(re

(re

31 13 12 11 9 8 7 0

0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Reset

SLAVE_SPI_DECRYPT_ENABLE Enables decryption in the external flash. (R/W)

SLAVE_SPI_ENCRYPT_ENABLE Enables encryption in the external flash. (R/W)

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5. DPort Register

Register 5.22: WIFI_CLK_EN_REG (0x0CC)

31 0

0x0FFFCE030 Reset

WIFI_CLK_EN_REG Clock gate for Wi-Fi. (R/W)

Register 5.23: WIFI_RST_EN_REG (0x0D0)

31 0

0x000000000 Reset

WIFI_RST_EN_REG Reset for Wi-Fi. (R/W)

Register 5.24: CPU_INTR_FROM_CPU_n_REG (n: 0-3) (0xDC+4*n)

n
U_
P
_C
M
O
FR
R_
)

T
ed

IN
rv

U_
se

CP
(re

31 1 0

0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Reset

CPU_INTR_FROM_CPU_n Interrupt in both CPUs. (R/W)

Register 5.25: PRO_INTR_STATUS_REG_n_REG (n: 0-2) (0xEC+4*n)

31 0

0x000000000 Reset

PRO_INTR_STATUS_REG_n_REG PRO_CPU interrupt status. (RO)

Register 5.26: APP_INTR_STATUS_REG_n_REG (n: 0-2) (0xF8+4*n)

31 0

0x000000000 Reset

APP_INTR_STATUS_REG_n_REG APP_CPU interrupt status. (RO)

Register 5.27: PRO_MAC_INTR_MAP_REG (0x104)

Register 5.28: PRO_MAC_NMI_MAP_REG (0x108)

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5. DPort Register

Register 5.29: PRO_BB_INT_MAP_REG (0x10C)

Register 5.30: PRO_BT_MAC_INT_MAP_REG (0x110)

Register 5.31: PRO_BT_BB_INT_MAP_REG (0x114)

Register 5.32: PRO_BT_BB_NMI_MAP_REG (0x118)

Register 5.33: PRO_RWBT_IRQ_MAP_REG (0x11C)

Register 5.34: PRO_RWBLE_IRQ_MAP_REG (0x120)

Register 5.35: PRO_RWBT_NMI_MAP_REG (0x124)

Register 5.36: PRO_RWBLE_NMI_MAP_REG (0x128)

Register 5.37: PRO_SLC0_INTR_MAP_REG (0x12C)

Register 5.38: PRO_SLC1_INTR_MAP_REG (0x130)

Register 5.39: PRO_UHCI0_INTR_MAP_REG (0x134)

Register 5.40: PRO_UHCI1_INTR_MAP_REG (0x138)

Register 5.41: PRO_TG_T0_LEVEL_INT_MAP_REG (0x13C)

Register 5.42: PRO_TG_T1_LEVEL_INT_MAP_REG (0x140)

Register 5.43: PRO_TG_WDT_LEVEL_INT_MAP_REG (0x144)

Register 5.44: PRO_TG_LACT_LEVEL_INT_MAP_REG (0x148)

Register 5.45: PRO_TG1_T0_LEVEL_INT_MAP_REG (0x14C)

Register 5.46: PRO_TG1_T1_LEVEL_INT_MAP_REG (0x150)

Register 5.47: PRO_TG1_WDT_LEVEL_INT_MAP_REG (0x154)

Register 5.48: PRO_TG1_LACT_LEVEL_INT_MAP_REG (0x158)

Register 5.49: PRO_GPIO_INTERRUPT_MAP_REG (0x15C)

Register 5.50: PRO_GPIO_INTERRUPT_NMI_MAP_REG (0x160)

Register 5.51: PRO_CPU_INTR_FROM_CPU_0_MAP_REG (0x164)

Register 5.52: PRO_CPU_INTR_FROM_CPU_1_MAP_REG (0x168)

Register 5.53: PRO_CPU_INTR_FROM_CPU_2_MAP_REG (0x16C)

Register 5.54: PRO_CPU_INTR_FROM_CPU_3_MAP_REG (0x170)

Register 5.55: PRO_SPI_INTR_0_MAP_REG (0x174)

Register 5.56: PRO_SPI_INTR_1_MAP_REG (0x178)

Register 5.57: PRO_SPI_INTR_2_MAP_REG (0x17C)

Register 5.58: PRO_SPI_INTR_3_MAP_REG (0x180)

Register 5.59: PRO_I2S0_INT_MAP_REG (0x184)

Register 5.60: PRO_I2S1_INT_MAP_REG (0x188)

Register 5.61: PRO_UART_INTR_MAP_REG (0x18C)

Register 5.62: PRO_UART1_INTR_MAP_REG (0x190)

Register 5.63: PRO_UART2_INTR_MAP_REG (0x194)

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5. DPort Register

Register 5.64: PRO_SDIO_HOST_INTERRUPT_MAP_REG (0x198)

Register 5.65: PRO_EMAC_INT_MAP_REG (0x19C)
Register 5.66: PRO_PWM0_INTR_MAP_REG (0x1A0)
Register 5.67: PRO_PWM1_INTR_MAP_REG (0x1A4)
Register 5.68: PRO_PWM2_INTR_MAP_REG (0x1A8)
Register 5.69: PRO_PWM3_INTR_MAP_REG (0x1AC)
Register 5.70: PRO_LEDC_INT_MAP_REG (0x1B0)
Register 5.71: PRO_EFUSE_INT_MAP_REG (0x1B4)
Register 5.72: PRO_CAN_INT_MAP_REG (0x1B8)
Register 5.73: PRO_RTC_CORE_INTR_MAP_REG (0x1BC)
Register 5.74: PRO_RMT_INTR_MAP_REG (0x1C0)
Register 5.75: PRO_PCNT_INTR_MAP_REG (0x1C4)
Register 5.76: PRO_I2C_EXT0_INTR_MAP_REG (0x1C8)
Register 5.77: PRO_I2C_EXT1_INTR_MAP_REG (0x1CC)
Register 5.78: PRO_RSA_INTR_MAP_REG (0x1D0)
Register 5.79: PRO_SPI1_DMA_INT_MAP_REG (0x1D4)
Register 5.80: PRO_SPI2_DMA_INT_MAP_REG (0x1D8)
Register 5.81: PRO_SPI3_DMA_INT_MAP_REG (0x1DC)
Register 5.82: PRO_WDG_INT_MAP_REG (0x1E0)
Register 5.83: PRO_TIMER_INT1_MAP_REG (0x1E4)
Register 5.84: PRO_TIMER_INT2_MAP_REG (0x1E8)
Register 5.85: PRO_TG_T0_EDGE_INT_MAP_REG (0x1EC)
Register 5.86: PRO_TG_T1_EDGE_INT_MAP_REG (0x1F0)
Register 5.87: PRO_TG_WDT_EDGE_INT_MAP_REG (0x1F4)
Register 5.88: PRO_TG_LACT_EDGE_INT_MAP_REG (0x1F8)
Register 5.89: PRO_TG1_T0_EDGE_INT_MAP_REG (0x1FC)
Register 5.90: PRO_TG1_T1_EDGE_INT_MAP_REG (0x200)
Register 5.91: PRO_TG1_WDT_EDGE_INT_MAP_REG (0x204)
Register 5.92: PRO_TG1_LACT_EDGE_INT_MAP_REG (0x208)
Register 5.93: PRO_MMU_IA_INT_MAP_REG (0x20C)
Register 5.94: PRO_MPU_IA_INT_MAP_REG (0x210)
Register 5.95: PRO_CACHE_IA_INT_MAP_REG (0x214)
AP
d)

_M
e
rv

_*
se

O
PR
(re

31 5 4 0

0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 16 Reset

PRO_*_MAP Interrupt map. (R/W)

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5. DPort Register

Register 5.96: APP_MAC_INTR_MAP_REG (0x218)

Register 5.97: APP_MAC_NMI_MAP_REG (0x21C)

Register 5.98: APP_BB_INT_MAP_REG (0x220)

Register 5.99: APP_BT_MAC_INT_MAP_REG (0x224)

Register 5.100: APP_BT_BB_INT_MAP_REG (0x228)

Register 5.101: APP_BT_BB_NMI_MAP_REG (0x22C)

Register 5.102: APP_RWBT_IRQ_MAP_REG (0x230)

Register 5.103: APP_RWBLE_IRQ_MAP_REG (0x234)

Register 5.104: APP_RWBT_NMI_MAP_REG (0x238)

Register 5.105: APP_RWBLE_NMI_MAP_REG (0x23C)

Register 5.106: APP_SLC0_INTR_MAP_REG (0x240)

Register 5.107: APP_SLC1_INTR_MAP_REG (0x244)

Register 5.108: APP_UHCI0_INTR_MAP_REG (0x248)

Register 5.109: APP_UHCI1_INTR_MAP_REG (0x24C)

Register 5.110: APP_TG_T0_LEVEL_INT_MAP_REG (0x250)

Register 5.111: APP_TG_T1_LEVEL_INT_MAP_REG (0x254)

Register 5.112: APP_TG_WDT_LEVEL_INT_MAP_REG (0x258)

Register 5.113: APP_TG_LACT_LEVEL_INT_MAP_REG (0x25C)

Register 5.114: APP_TG1_T0_LEVEL_INT_MAP_REG (0x260)

Register 5.115: APP_TG1_T1_LEVEL_INT_MAP_REG (0x264)

Register 5.116: APP_TG1_WDT_LEVEL_INT_MAP_REG (0x268)

Register 5.117: APP_TG1_LACT_LEVEL_INT_MAP_REG (0x26C)

Register 5.118: APP_GPIO_INTERRUPT_MAP_REG (0x270)

Register 5.119: APP_GPIO_INTERRUPT_NMI_MAP_REG (0x274)

Register 5.120: APP_CPU_INTR_FROM_CPU_0_MAP_REG (0x278)

Register 5.121: APP_CPU_INTR_FROM_CPU_1_MAP_REG (0x27C)

Register 5.122: APP_CPU_INTR_FROM_CPU_2_MAP_REG (0x280)

Register 5.123: APP_CPU_INTR_FROM_CPU_3_MAP_REG (0x284)

Register 5.124: APP_SPI_INTR_0_MAP_REG (0x288)

Register 5.125: APP_SPI_INTR_1_MAP_REG (0x28C)

Register 5.126: APP_SPI_INTR_2_MAP_REG (0x290)

Register 5.127: APP_SPI_INTR_3_MAP_REG (0x294)

Register 5.128: APP_I2S0_INT_MAP_REG (0x298)

Register 5.129: APP_I2S1_INT_MAP_REG (0x29C)

Register 5.130: APP_UART_INTR_MAP_REG (0x2A0)

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5. DPort Register

Register 5.131: APP_UART1_INTR_MAP_REG (0x2A4)

Register 5.132: APP_UART2_INTR_MAP_REG (0x2A8)

Register 5.133: APP_SDIO_HOST_INTERRUPT_MAP_REG (0x2AC)

Register 5.134: APP_EMAC_INT_MAP_REG (0x2B0)

Register 5.135: APP_PWM0_INTR_MAP_REG (0x2B4)

Register 5.136: APP_PWM1_INTR_MAP_REG (0x2B8)

Register 5.137: APP_PWM2_INTR_MAP_REG (0x2BC)

Register 5.138: APP_PWM3_INTR_MAP_REG (0x2C0)

Register 5.139: APP_LEDC_INT_MAP_REG (0x2C4)

Register 5.140: APP_EFUSE_INT_MAP_REG (0x2C8)

Register 5.141: APP_CAN_INT_MAP_REG (0x2CC)

Register 5.142: APP_RTC_CORE_INTR_MAP_REG (0x2D0)

Register 5.143: APP_RMT_INTR_MAP_REG (0x2D4)

Register 5.144: APP_PCNT_INTR_MAP_REG (0x2D8)

Register 5.145: APP_I2C_EXT0_INTR_MAP_REG (0x2DC)

Register 5.146: APP_I2C_EXT1_INTR_MAP_REG (0x2E0)

Register 5.147: APP_RSA_INTR_MAP_REG (0x2E4)

Register 5.148: APP_SPI1_DMA_INT_MAP_REG (0x2E8)

Register 5.149: APP_SPI2_DMA_INT_MAP_REG (0x2EC)

Register 5.150: APP_SPI3_DMA_INT_MAP_REG (0x2F0)

Register 5.151: APP_WDG_INT_MAP_REG (0x2F4)

Register 5.152: APP_TIMER_INT1_MAP_REG (0x2F8)

Register 5.153: APP_TIMER_INT2_MAP_REG (0x2FC)

Register 5.154: APP_TG_T0_EDGE_INT_MAP_REG (0x300)

Register 5.155: APP_TG_T1_EDGE_INT_MAP_REG (0x304)

Register 5.156: APP_TG_WDT_EDGE_INT_MAP_REG (0x308)

Register 5.157: APP_TG_LACT_EDGE_INT_MAP_REG (0x30C)

Register 5.158: APP_TG1_T0_EDGE_INT_MAP_REG (0x310)

Register 5.159: APP_TG1_T1_EDGE_INT_MAP_REG (0x314)

Register 5.160: APP_TG1_WDT_EDGE_INT_MAP_REG (0x318)

Register 5.161: APP_TG1_LACT_EDGE_INT_MAP_REG (0x31C)

Register 5.162: APP_MMU_IA_INT_MAP_REG (0x320)

Register 5.163: APP_MPU_IA_INT_MAP_REG (0x324)

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5. DPort Register

Register 5.164: APP_CACHE_IA_INT_MAP_REG (0x328)

AP
)

M
ed

*_
rv

P_
se

AP
(re
31 5 4 0

0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 16 Reset

APP_*_MAP Interrupt map. (R/W)

Register 5.165: AHBLITE_MPU_TABLE_UART_REG (0x32C)

Register 5.166: AHBLITE_MPU_TABLE_SPI1_REG (0x330)

Register 5.167: AHBLITE_MPU_TABLE_SPI0_REG (0x334)

Register 5.168: AHBLITE_MPU_TABLE_GPIO_REG (0x338)

Register 5.169: AHBLITE_MPU_TABLE_RTC_REG (0x348)

Register 5.170: AHBLITE_MPU_TABLE_IO_MUX_REG (0x34C)

Register 5.171: AHBLITE_MPU_TABLE_HINF_REG (0x354)

Register 5.172: AHBLITE_MPU_TABLE_UHCI1_REG (0x358)

Register 5.173: AHBLITE_MPU_TABLE_I2S0_REG (0x364)

Register 5.174: AHBLITE_MPU_TABLE_UART1_REG (0x368)

Register 5.175: AHBLITE_MPU_TABLE_I2C_EXT0_REG (0x374)

Register 5.176: AHBLITE_MPU_TABLE_UHCI0_REG (0x378)

Register 5.177: AHBLITE_MPU_TABLE_SLCHOST_REG (0x37C)

Register 5.178: AHBLITE_MPU_TABLE_RMT_REG (0x380)

Register 5.179: AHBLITE_MPU_TABLE_PCNT_REG (0x384)

Register 5.180: AHBLITE_MPU_TABLE_SLC_REG (0x388)

Register 5.181: AHBLITE_MPU_TABLE_LEDC_REG (0x38C)

Register 5.182: AHBLITE_MPU_TABLE_EFUSE_REG (0x390)

Register 5.183: AHBLITE_MPU_TABLE_SPI_ENCRYPT_REG (0x394)

Register 5.184: AHBLITE_MPU_TABLE_PWM0_REG (0x39C)

Register 5.185: AHBLITE_MPU_TABLE_TIMERGROUP_REG (0x3A0)

Register 5.186: AHBLITE_MPU_TABLE_TIMERGROUP1_REG (0x3A4)

Register 5.187: AHBLITE_MPU_TABLE_SPI2_REG (0x3A8)

Register 5.188: AHBLITE_MPU_TABLE_SPI3_REG (0x3AC)

Register 5.189: AHBLITE_MPU_TABLE_APB_CTRL_REG (0x3B0)

Register 5.190: AHBLITE_MPU_TABLE_I2C_EXT1_REG (0x3B4)

Register 5.191: AHBLITE_MPU_TABLE_SDIO_HOST_REG (0x3B8)

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Register 5.192: AHBLITE_MPU_TABLE_EMAC_REG (0x3BC)

Register 5.193: AHBLITE_MPU_TABLE_PWM1_REG (0x3C4)

Register 5.194: AHBLITE_MPU_TABLE_I2S1_REG (0x3C8)

Register 5.195: AHBLITE_MPU_TABLE_UART2_REG (0x3CC)

Register 5.196: AHBLITE_MPU_TABLE_PWM2_REG (0x3D0)

Register 5.197: AHBLITE_MPU_TABLE_PWM3_REG (0x3D4)

Register 5.198: AHBLITE_MPU_TABLE_PWR_REG (0x3E4)

IG
NF
CO
_
NT
RA
_G
SS
CE
AC
*_
E_
d )
ve

IT
BL
r
se

AH
(re

31 6 5 0

0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Reset

AHBLITE_*_ACCESS_GRANT_CONFIG MPU for peripherals. (R/W)

Register 5.199: IMMU_TABLEn_REG (n: 0-15) (0x504+4*n)

n
BLE
)

TA
ed

U_
rv
se

M
(re

IM

31 7 6 0

0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 15 Reset

IMMU_TABLEn MMU for internal SRAM. (R/W)

Register 5.200: DMMU_TABLEn_REG (n: 0-15) (0x544+4*n)

En
BL
TA
)
ed

U_
rv

M
se

DM
(re

31 7 6 0

0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 15 Reset

DMMU_TABLEn MMU for internal SRAM. (R/W)

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Register 5.201: SECURE_BOOT_CTRL_REG (0x5A4)

L
_SE
ER
AD
O
TL
O
O
_B
W
_S
d)

RE
ve

CU
r
se

SE
(re
31 1 0

0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Reset

SECURE_SW_BOOTLOADER_SEL Mode for secure_boot. (R/W)

Register 5.202: SPI_DMA_CHAN_SEL_REG (0x5A8)

EL

EL
E
_S

_S

_S
AN

AN

AN
CH

CH

CH
A_

A_

A_
DM

DM

M
_D
_

2_
d)

I3

I1
PI
e

SP

SP
rv

S
se

I_

I_

I_
SP

SP

SP
(re

31 6 5 4 3 2 1 0

0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Reset

SPI_SPI3_DMA_CHAN_SEL Selects DMA channel for SPI3. (R/W)

SPI_SPI2_DMA_CHAN_SEL Selects DMA channel for SPI2. (R/W)

SPI_SPI1_DMA_CHAN_SEL Selects DMA channel for SPI1. (R/W)

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6. DMA Controller

6.1 Overview
Direct Memory Access (DMA) is used for high-speed data transfer between peripherals and memory, as well as
from memory to memory. Data can be quickly moved with DMA without any CPU intervention, thus allowing for
more efficient use of the cores when processing data.

In the ESP32, 13 peripherals are capable of using DMA for data transfer, namely, UART0, UART1, UART2, SPI1,
SPI2, SPI3, I2S0, I2S1, SDIO slave, SD/MMC host, EMAC, BT, and Wi-Fi.

6.2 Features
The DMA controllers in the ESP32 feature:

• AHB bus architecture

• Support for full-duplex and half-duplex data transfers

• Programmable data transfer length in bytes

• Support for 4-beat burst transfer

• 328 KB DMA address space

• All high-speed communication modules powered by DMA

6.3 Functional Description

All modules that require high-speed data transfer in bulk contain a DMA controller. DMA addressing uses the
same data bus as the CPU to read/write to the internal RAM.

Each DMA controller features different functions. However, the architecture of the DMA engine (DMA_ENGINE) is
the same in all DMA controllers.

6.3.1 DMA Engine Architecture

Figure 12: DMA Engine Architecture

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The DMA Engine accesses SRAM over the AHB BUS. In Figure 12, the RAM represents the internal SRAM banks
available on ESP32. Further details on the SRAM addressing range can be found in Chapter System and
Memory. Software can use a DMA Engine by assigning a linked list to define the DMA operational
parameters.

The DMA Engine transmits the data from the RAM to a peripheral, according to the contents of the out_link
descriptor. Also, the DMA Engine stores the data received from a peripheral into a specified RAM location,
according to the contents of the in_link descriptor.

6.3.2 Linked List

Figure 13: Linked List Structure

The DMA descriptor’s linked lists (out_link and in_link) have the same structure. As shown in Figure 13, a
linked-list descriptor consists of three words. The meaning of each field is as follows:

• owner (DW0) [31]: The allowed operator of the buffer corresponding to the current linked list.
1’b0: the allowed operator is the CPU;
1’b1: the allowed operator is the DMA controller.

• eof (DW0) [30]: End-Of-File character.

1’b0: the linked-list item does not mark the end of the linked list;
1’b1: the linked-list item is at the end of the linked list.

• reserved (DW0) [29:24]: Reserved bits.

Software should not write 1’s in this space.

• length (DW0) [23:12]: The number of valid bytes in the buffer corresponding to the current linked list. The
field value indicates the number of bytes to be transferred to/from the buffer denoted by word DW1.

• size (DW0) [11:0]: The size of the buffer corresponding to the current linked list.
NOTE: The size must be word-aligned.

• buffer address pointer (DW1): Buffer address pointer. This is the address of the data buffer.
NOTE: The buffer address must be word-aligned.

• next descriptor address (DW2): The address pointer of the next linked-list item. The value is 0, if the current
linked-list item is the last on the list (eof=1).

When receiving data, if the data transfer length is smaller than the specified buffer size, DMA will not use the
remaining space. This enables the DMA engine to be used for transferring an arbitrary number of data
bytes.

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6.4 UART DMA (UDMA)

The ESP32 has three UART interfaces that share two UDMA (UART DMA) controllers. The UHCIx_UART_CE (x is
0 or 1) is used for selecting the UDMA.

Figure 14: Data Transfer in UDMA Mode

Figure 14 shows the data transfer in UDMA mode. Before the DMA Engine receives data, software must initialize
the receive-linked-list. UHCIx_INLINK_ADDR is used to point to the first in_link descriptor. The register must be
programmed with the lower 20 bits of the address of the initial linked-list item. After UHCIx_INLINK_START is set,
the Universal Host Controller Interface (UHCI) will transmit the data received by UART to the Decoder. After being
parsed, the data will be stored in the RAM as specified by the receive-linked-list descriptor.

Before DMA transmits data, software must initialize the transmit-linked-list and the data to be transferred.
UHCI_OUTLINK_ADDR is used to point to the first out_link descriptor. The register must be programmed with
the lower 20 bits of the address of the initial transmit-linked-list item. After UHCIx_OUTLINK_START is set, the
DMA Engine will read data from the RAM location specified by the linked-list descriptor and then transfer the data
through the Encoder. The DMA Engine will then shift the data out serially through the UART transmitter.

The UART DMA follows a format of (separator + data + separator). The Encoder is used for adding separators
before and after data, as well as using special-character sequences to replace data that are the same as
separators. The Decoder is used for removing separators before and after data, as well as replacing the
special-character sequences with separators. There can be multiple consecutive separators marking the
beginning or end of data. These separators can be configured through UHCIx_SEPER_CH, with the default
values being 0xC0. Data that are the same as separators can be replaced with UHCIx_ESC_SEQ0_CHAR0
(0xDB by default) and UHCIx_ESC_SEQ0_CHAR1 (0xDD by default). After the transmission process is complete,
a UHCIx_OUT_TOTAL_EOF_INT interrupt will be generated. After the reception procedure is complete, a
UHCIx_IN_SUC_EOF_INT interrupt will be generated.

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6.5 SPI DMA Interface

Figure 15: SPI DMA

ESP32 SPI modules can use DMA as well as the CPU for data exchange with peripherals. As can be seen from
Figure 15, two DMA channels are shared by SPI1, SPI2 and SPI3 controllers. Each DMA channel can be used by
any one SPI controller at any given time.

The ESP32 SPI DMA Engine also uses a linked list to receive/transmit data. Burst transmission is supported. The
minimum data length for a single transfer is one byte. Consecutive data transfer is also supported.

SPI1_DMA_CHAN_SEL[1:0], SPI2_DMA_CHAN_SEL[1:0] and SPI3_DMA_CHAN_SEL[1:0] in

DPORT_SPI_DMA_CHAN_SEL_REG must be configured to enable the SPI DMA interface for a specific SPI
controller. Each SPI controller corresponds to one domain which has two bits with values 0, 1 and 2. Value 3 is
reserved and must not be configured for operation.

Considering SPI1 as an example,

if SPI SPI1_DMA_CHAN_SEL[1:0] = 0, then SPI1 does not use any DMA channel;
if SPI1_DMA_CHAN_SEL[1:0] = 1, then SPI1 enables DMA channel1;
if SPI1_DMA_CHAN_SEL[1:0] = 2, then SPI1 enables DMA channel2.

The SPI_OUTLINK_START bit in SPI_DMA_OUT_LINK_REG and the SPI_INLINK_START bit in

SPI_DMA_IN_LINK_REG are used for enabling the DMA Engine. The two bits are self-cleared by hardware.
When SPI_OUTLINK_START is set to 1, the DMA Engine starts processing the outbound linked list descriptor
and prepares to transmit data. When SPI_INLINK_START is set to 1, then the DMA Engine starts processing the
inbound linked-list descriptor and gets prepared to receive data.

Software should configure the SPI DMA as follows:

1. Reset the DMA state machine and FIFO parameters;

2. Configure the DMA-related registers for operation;

3. Configure the SPI-controller-related registers accordingly;

4. Set SPI_USR to enable DMA operation.

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6.6 I2S DMA Interface

The ESP32 integrates two I2S modules, I2S0 and I2S1, each of which is powered by a DMA channel. The
REG_I2S_DSCR_EN bit in I2S_FIFO_CONF_REG is used for enabling the DMA operation. ESP32 I2S DMA uses
the standard linked-list descriptor to configure DMA operations for data transfer. Burst transfer is supported.
However, unlike the SPI DMA channels, the data size for a single transfer is one word, or four bytes.
REG_I2S_RX_EOF_NUM[31:0] bit in I2S_RXEOF_NUM_REG is used for configuring the data size of a single
transfer operation, in multiples of one word.

I2S_OUTLINK_START bit in I2S_OUT_LINK_REG and I2S_INLINK_START bit in I2S_IN_LINK_REG are used for
enabling the DMA Engine and are self-cleared by hardware. When I2S_OUTLINK_START is set to 1, the DMA
Engine starts processing the outbound linked-list descriptor and gets prepared to send data. When
I2S_INLINK_START is set to 1, the DMA Engine starts processing the inbound linked-list descriptor and gets
prepared to receive data.

Software should configure the I2S DMA as follows:

1. Configure I2S-controller-related registers;

2. Reset the DMA state machine and FIFO parameters;

3. Configure DMA-related registers for operation;

4. In I2S master mode, set I2S_TX_START bit or I2S_RX_START bit to initiate an I2S operation;
In I2S slave mode, set I2S_TX_START bit or I2S_RX_START bit and wait for data transfer to be initiated by
the host device.

For more information on I2S DMA interrupts, please see Section DMA Interrupts, in Chapter I2S.

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7. SPI

7.1 Overview

Figure 16: SPI Architecture

As Figure 16 shows, ESP32 integrates four SPI controllers which can be used to communicate with external
devices that use the SPI protocol. Controller SPI0 is used as a buffer for accessing external memory. Controller
SPI1 can be used as a master. Controllers SPI2 and SPI3 can be configured as either a master or a slave. When
used as a master, each SPI controller can drive multiple CS signals (CS0 ~ CS2) to activate multiple slaves.
Controllers SPI1 ~ SPI3 share two DMA channels.

The SPI signal buses consist of D, Q, CS0-CS2, CLK, WP, and HD signals, as Table 25 shows. Controllers SPI0
and SPI1 share one signal bus through an arbiter; the signals of the shared bus start with ”SPI”. Controllers SPI2
and SPI3 use signal buses starting with ”HSPI” and ”VSPI” respectively. The I/O lines included in the
above-mentioned signal buses can be mapped to pins via either the IO_MUX module or the GPIO matrix. (Please
refer to Chapter IO_MUX for details.)

The SPI controller supports four-line full-duplex/half-duplex communication (MOSI, MISO, CS, and CLK lines) and
three-line half-duplex-only communication (DATA, CS, and CLK lines) in GP-SPI mode. In QSPI mode, an SPI
controller accesses the flash or SRAM by using signal buses D, Q, CS0 ~ CS2, CLK, WP, and HD as a four-bit
parallel SPI bus. The mapping between SPI bus signals and pin function signals under different communication
modes is shown in Table 25.

Table 25: Mapping Between SPI Bus Signals and Pin Function Signals

Four-line GP-SPI Three-line GP-SPI QSPI Pin function signals

Full-duplex/half- Half-duplex signal Signal bus SPI signal HSPI signal VSPI signal
duplex signal bus bus bus bus bus
MOSI DATA D SPID HSPID VSPID
MISO - Q SPIQ HSPIQ VSPIQ
CS CS CS SPICS0 HSPICS0 VSPICS0
CLK CLK CLK SPICLK HSPICLK VSPICLK
- - WP SPIWP HSPIWP VSPIWP
- - HD SPIHD HSPIHD VSPIHD

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7.2 SPI Features

General Purpose SPI (GP-SPI)

• Programmable data transfer length, in multiples of 1 byte

• Four-line full-duplex/half-duplex communication and three-line half-duplex communication support

• Master mode and slave mode

• Programmable CPOL and CPHA

• Programmable clock

Parallel QSPI

• Communication format support for specific slave devices such as flash

• Programmable communication format

• Six variations of flash-read operations available

• Automatic shift between flash and SRAM access

• Automatic wait states for flash access

SPI DMA Support

• Support for sending and receiving data using linked lists

SPI Interrupt Hardware

• SPI interrupts

• SPI DMA interrupts

7.3 GP-SPI
The SPI master mode supports four-line full-duplex/half-duplex communication and three-line half-duplex
communication. Figure 17 outlines the connections needed for four-line full-duplex/half-duplex
communications.

Figure 17: SPI Master and Slave Full-duplex/Half-duplex Communication

The SPI1 ~ SPI3 controllers can communicate with other slaves as a standard SPI master. SPI2 and SPI3 can
be configured as either a master or a slave. Every SPI master can be connected to three slaves at most by

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7. SPI

default. When not using DMA, the maximum length of data received/sent in one burst is 64 bytes. The data
length is in multiples of one byte.

7.3.1 GP-SPI Four-line Full-duplex Communication

When configured to four-line full-duplex mode, the ESP32 SPI can act as either a master or a slave. The length of
received and sent data needs to be set by configuring the SPI_MISO_DLEN_REG, SPI_MOSI_DLEN_REG
registers for master mode as well as SPI_SLV_RDBUF_DLEN_REG, SPI_SLV_WRBUF_DLEN_REG registers for
slave mode. The SPI_DOUTDIN bit and SPI_USR_MOSI bit in register SPI_USER_REG should be configured to
enable this communication mode. The SPI_USR bit in register SPI_CMD_REG needs to be configured to initialize
a data transfer.

7.3.2 GP-SPI Four-line Half-duplex Communication

When configured to four-line half-duplex mode, the ESP32 SPI can act as either a master or a slave. In this
mode, the SPI communication supports flexible communication format as: command + address + dummy phase
+ received and/or sent data. The format is specified as follows:

1. command: length of 0 ~ 16 bits; Master Out Slave In (MOSI).

2. address: length of 0 ~ 32/64 bits; Master Out Slave In (MOSI).

3. dummy phase: length of 0 ~ 256 SPI clocks.

4. received and/or sent data: length of 0 ~ 512 bits (64 bytes); Master Out Slave In (MOSI) or Master In Slave
Out (MISO).

The address length is up to 32 bits in GP-SPI master mode and 64 bits in QSPI master mode. The command
phase, address phase, dummy phase and received/sent data phase are controlled by bits
SPI_USR_COMMAND, SPI_USR_ADDR, SPI_USR_DUMMY and SPI_USR_MISO/SPI_USR_MOSI respectively
in register SPI_USER_REG. A certain phase is enabled only when its corresponding control bit is set to 1. Details
can be found in register description. When SPI works as a master, the register can be configured by software as
required to determine whether or not to enable a certain phase.

When SPI works as a slave, the communication format must contain command, address, received and/or sent
data, among which the command has several options listed in Table 26. During data transmission or reception,
the CS signal should keep logic level low. If the CS signal is pulled up during transmission, the internal state of
the slave will be reset.

Table 26: Command Definitions Supported by GP-SPI Slave in Half-duplex Mode

Command Description
0x1 Received by slave; writes data sent by the master into the slave status register via MOSI.
0x2 Received by slave; writes data sent by the master into the slave data buffer via MOSI.
0x3 Sent by slave; sends data in the slave buffer to master via MISO.
0x4 Sent by slave; sends data in the slave status register to master via MISO.
Writes master data on MOSI into data buffer and then sends the date in the slave data buffer
0x6
to MISO.

The master can write the slave status register SPI_SLV_WR_STATUS_REG, and decide whether to read data from
register SPI_SLV_WR_STATUS_REG or register SPI_RD_STATUS_REG via the SPI_SLV_STATUS_READBACK

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7. SPI

bit in register SPI_SLAVE1_REG. The SPI master can maintain communication with the slave by reading and
writing slave status register, thus realizing complex communication with ease.

The length of received and sent data is controlled by SPI_MISO_DLEN_REG and SPI_MOSI_DLEN_REG in
master mode, as well as SPI_SLV_RDBUF_DLEN_REG and SPI_SLV_WRBUF_DLEN_REG in slave mode. A
reception or transmission of data is controlled by bit SPI_USR_MOSI or SPI_USR_MISO in SPI_USER_REG. The
SPI_USR bit in register SPI_CMD_REG needs to be configured to initialize a data transfer.

7.3.3 GP-SPI Three-line Half-duplex Communication

The three-line half-duplex communication differs from four-line half-duplex communication in that the reception
and transmission shares one signal bus and that the communication format must contain command, address,
received and/or sent data. Software can enable three-line half-duplex communication by configuring SPI_SIO bit
in SPI_USER_REG register.

Note:

• In half-duplex communication, the order of command, address, received and/or sent data in the communication
format should be followed strictly.

• In half-duplex communication, communication formats ”command + address + received data + sent data” and
”received data + sent data” are not applicable to DMA.

• When ESP32 SPI acts as a slave, the master CS should be active at least one SPI clock period before a read/write
process is initiated, and should be inactive at least one SPI clock period after the read/write process is completed.

7.3.4 GP-SPI Data Buffer

Figure 18: SPI Data Buffer

ESP32 SPI has 16 × 32 bits of data buffer to buffer data-send and data-receive operations. As is shown in Figure
18, received data is written from the low byte of SPI_W0_REG by default and the writing ends with
SPI_W15_REG. If the data length is over 64 bytes, the extra part will be written from SPI_W0_REG.

Data buffer blocks SPI_W0_REG ~ SPI_W7_REG and SPI_W8_REG ~ SPI_W15_REG data correspond to the
lower part and the higher part respectively. They can be used separately, and are controlled by the
SPI_USR_MOSI_HIGHPART bit and the SPI_USR_MISO_HIGHPART bit in register SPI_USER_REG. For
example, if SPI is configured as a master, when SPI_USR_MOSI_HIGHPART = 1,
SPI_W8_REG ~ SPI_W15_REG are used as buffer for sending data; when SPI_USR_MISO_HIGHPART = 1,
SPI_W8_REG ~ SPI_W15_REG are used as buffer for receiving data. If SPI acts as a slave, when

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SPI_USR_MOSI_HIGHPART = 1, SPI_W8_REG ~ SPI_W15_REG are used as buffer for receiving data; when
SPI_USR_MISO_HIGHPART = 1, SPI_W8_REG ~ SPI_W15_REG are used as buffer for sending data.

7.4 GP-SPI Clock Control

The maximum output clock frequency of ESP32 GP-SPI master is fapb /2, and the maximum input clock
frequency of the ESP32 GP-SPI slave is fapb /8. The master can derive other clock frequencies via frequency
division.

fapb
fspi =
(SPI_CLKCNT_N+1)(SPI_CLKDIV_PRE+1)

SPI_CLKCNT_N and SPI_CLKDIV_PRE are two bits of register SPI_CLOCK_REG (Please refer to 7.7 Register
Description for details). SPI_CLKCNT_H = ⌊ SPI_CLKCNT_N+1
2 –1⌋, SPI_CLKCNT_N=SPI_CLKCNT_L. When the
SPI_CLK_EQU_SYSCLK bit in register SPI_CLOCK_REG is set to 1, and the other bits are set to 0, SPI output
clock frequency is fapb . For other clock frequencies, SPI_CLK_EQU_SYSCLK needs to be 0. In slave mode,
SPI_CLKCNT_N, SPI_CLKCNT_L, SPI_CLKCNT_H and SPI_CLKDIV_PRE should all be 0.

7.4.1 GP-SPI Clock Polarity (CPOL) and Clock Phase (CPHA)

The clock polarity and clock phase of ESP32 SPI are controlled by SPI_CK_IDLE_EDGE bit in register
SPI_PIN_REG, SPI_CK_OUT_EDGE bit and SPI_CK_I_EDGE bit in register SPI_USER_REG, as well as
SPI_MISO_DELAY_MODE[1:0] bit, SPI_MISO_DELAY_NUM[2:0] bit, SPI_MOSI_DELAY_MODE[1:0] bit,
SPI_MOSI_DELAY_MUM[2:0] bit in register SPI_CTRL2_REG. Table 27 and Table 28 show the clock polarity and
phase as well as the corresponding register values for ESP32 SPI master and slave, respectively. Note that for
mode0 and mode2 in Table 28, the registers are configured differently in non-DMA mode and DMA mode, and
that the SPI slave data is output in advance in DMA mode.

Table 27: Clock Polarity and Phase, and Corresponding SPI Register Values for SPI Master

Registers mode0 mode1 mode2 mode3

SPI_CK_IDLE_EDGE 0 0 1 1
SPI_CK_OUT_EDGE 0 1 1 0
SPI_MISO_DELAY_MODE 2(0) 1(0) 1(0) 2(0)
SPI_MISO_DELAY_NUM 0 0 0 0
SPI_MOSI_DELAY_MODE 0 0 0 0
SPI_MOSI_DELAY_NUM 0 0 0 0

Table 28: Clock Polarity and Phase, and Corresponding SPI Register Values for SPI Slave

Registers mode0 mode1 mode2 mode3

Non-DMA DMA Non-DMA DMA
SPI_CK_IDLE_EDGE 1 0 1 0 1 0
SPI_CK_I_EDGE 0 1 1 1 0 0
SPI_MISO_DELAY_MODE 0 0 2 0 0 1
SPI_MISO_DELAY_NUM 0 2 0 0 2 0

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SPI_MOSI_DELAY_MODE 2 0 0 1 0 0
SPI_MOSI_DELAY_NUM 2 3 0 2 3 0

1. mode0 means CPOL=0, CPHA=0. When SPI is idle, the clock output is logic low; data changes on the
falling edge of the SPI clock and is sampled on the rising edge;

2. mode1 means CPOL=0, CPHA=1. When SPI is idle, the clock output is logic low; data changes on the
rising edge of the SPI clock and is sampled on the falling edge;

3. mode2 means when CPOL=1, CPHA=0. When SPI is idle, the clock output is logic high; data changes on
the rising edge of the SPI clock and is sampled on the falling edge;

4. mode3 means when CPOL=1, CPHA=1. When SPI is idle, the clock output is logic high; data changes on
the falling edge of the SPI clock and is sampled on the rising edge.

7.4.2 GP-SPI Timing

The data signals of ESP32 GP-SPI can be mapped to physical pins either via IO_MUX or via IO_MUX and GPIO
matrix. Input signals will be delayed by two clkapb clock cycles when they pass through the matrix. Output
signals will not be delayed.

When GP-SPI is used as master and the data signals are not received by the SPI controller via GPIO matrix, if
GP-SPI output clock frequency is clkapb /2, register SPI_MISO_DELAY_MODE should be set to 0 when
configuring the clock polarity. If GP-SPI output clock frequency is not higher than clkapb /4, register
SPI_MISO_DELAY_MODE can be set to the corresponding value in Table 27 when configuring the clock
polarity.

When GP-SPI is used in master mode and the data signals enter the SPI controller via the GPIO matrix:

1. If GP-SPI output clock frequency is clkapb /2, register SPI_MISO_DELAY_MODE should be set to 0 and the
dummy phase should be enabled (SPI_USR_DUMMY = 1) for one clkspi clock cycle
(SPI_USR_DUMMY_CYCLELEN = 0) when configuring the clock polarity;

2. If GP-SPI output clock frequency is clkapb /4, register SPI_MISO_DELAY_MODE should be set to 0 when
configuring the clock polarity;

3. If GP-SPI output clock frequency is not higher than clkapb /8, register SPI_MISO_DELAY_MODE can be set
to the corresponding value in Table 27 when configuring the clock polarity.

When GP-SPI is used in slave mode, the clock signal and the data signals should be routed to the SPI controller
via the same path, i.e., neither the clock signal nor the data signals passes through GPIO matrix, or both of them
pass through GPIO matrix. This is important in ensuring that the signals are not delayed by different time periods
before they reach the SPI hardware.

Assume that tspi , tpre and tv in Figure 19 denote SPI clock period, how far ahead data output is, and data output
delay time, respectively. Assume the SPI slave’s main clock period is tapb . For non-DMA mode0, SPI slave data
output is delayed by tv :

• tv < 3.5 ∗ tapb , if CLK does not pass through GPIO matrix;

• tv < 5.5 ∗ tapb , if CLK passes through GPIO matrix.

In DMA mode1 and mode3, SPI slave data output is delayed by the same period of time as in non-DMA mode.
However, for mode0 and mode2, SPI slave data is output earlier by tpre :

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• tpre < (tspi /2 − 5.5 ∗ tapb ), if CLK does not pass through GPIO matrix;

• tpre < (tspi /2 − 7.5 ∗ tapb ), if CLK passes through GPIO matrix.

Figure 19: GP-SPI ������

To conclude, if signals do not pass through GPIO matrix, the SPI slave clock frequency is up to fapb /8; if signals
pass through GPIO matrix, the SPI slave clock frequency is up to fapb /12. Note that (tspi /2–tpre ) represents data
output hold time for SPI slave in mode0 and mode2.

7.5 Parallel QSPI

ESP32 SPI controllers support SPI bus memory devices (such as flash and SRAM). The hardware connection
between the SPI pins and the memories is shown by Figure 20.

Figure 20: Parallel QSPI

SPI1, SPI2 and SPI3 controllers can also be configured as QSPI master to connect to external memory. The
maximum output clock frequency of the SPI memory interface is fapb , with the same clock configuration as that
of the GP-SPI master.

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Figure 21: Communication Format of Parallel QSPI

7.5.1 Communication Format of Parallel QSPI

To support communication with special slave devices, ESP32 QSPI implements a specifically designed
communication protocol. The communication format of ESP32 QSPI master is the same as that of GP-SPI
four-line half-duplex communication, except that in address phase and data phase, software can configure
registers to enable two-line or four-line transmission. Figure 21 shows a QSPI communication mode with four-line
transmission in address phase and data phase.

ESP32 QSPI supports flash-read operation in one-line, two-line, and four-line modes. When working as a QSPI
master, the command phase, address phase, dummy phase and data phase can be configured as needed, as
flexible as in GP-SPI mode.

Note that GPI-SPI full-duplex mode does not support dummy phase.

7.6 GP-SPI Interrupt Hardware

ESP32 SPI generates two types of interrupts. One is the SPI interrupt and the other is the SPI DMA
interrupt.

ESP32 SPI reckons the completion of send- and/or receive-operations as the completion of one operation from
the controller and generates one interrupt. When ESP32 SPI is configured to slave mode, the slave will generate
read/write status registers and read/write buffer data interrupts according to different operations.

7.6.1 SPI Interrupts

The SPI_*_INTEN bits in the SPI_SLAVE_REG register can be set to enable SPI interrupts. When an SPI interrupt
happens, the interrupt flag in the corresponding SPI_*_DONE register will get set. This flag is writable, and an
interrupt can be cleared by setting the bit to zero.

• SPI_TRANS_DONE_INT: Triggered when an SPI operation is done.

• SPI_SLV_WR_STA_INT: Triggered when an SPI slave status write is done.

• SPI_SLV_RD_STA_INT: Triggered when an SPI slave status read is done.

• SPI_SLV_WR_BUF_INT: Triggered when an SPI slave buffer write is done.

• SPI_SLV_RD_BUD_INT: Triggered when an SPI slave buffer read is done.

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7.6.2 DMA Interrupts

• SPI_OUT_TOTAL_EOF_INT: Triggered when all linked lists are sent.

• SPI_OUT_EOF_INT: Triggered when one linked list is sent.

• SPI_OUT_DONE_INT: Triggered when the last linked list item has zero length.

• SPI_IN_SUC_EOF_INT: Triggered when all linked lists are received.

• SPI_IN_ERR_EOF_INT: Triggered when there is an error receiving linked lists.

• SPI_IN_DONE_INT: Triggered when the last received linked list had a length of 0.

• SPI_INLINK_DSCR_ERROR_INT: Triggered when the received linked list is invalid.

• SPI_OUTLINK_DSCR_ERROR_INT: Triggered when the linked list to be sent is invalid.

• SPI_INLINK_DSCR_EMPTY_INT: Triggered when no valid linked list is available.

7.7 Register Summary

Name Description SPI0 SPI1 SPI2 SPI3 Acc

Control and configuration registers
Bit order and
SPI_CTRL_REG QIO/DIO/QOUT/DOUT 3FF43008 3FF42008 3FF64008 3FF65008 R/W
mode settings
SPI_CTRL2_REG Timing configuration 3FF43014 3FF42014 3FF64014 3FF65014 R/W
SPI_CLOCK_REG Clock configuration 3FF43018 3FF42018 3FF64018 3FF65018 R/W
Polarity and CS con-
SPI_PIN_REG 3FF43034 3FF42034 3FF64034 3FF65034 R/W
figuration
Slave mode configuration registers
Slave mode config-
SPI_SLAVE_REG uration and interrupt 3FF43038 3FF42038 3FF64038 3FF65038 R/W
status
SPI_SLAVE1_REG Slave data bit lengths 3FF4303C 3FF4203C 3FF6403C 3FF6503C R/W
Dummy cycle length
SPI_SLAVE2_REG 3FF43040 3FF42040 3FF64040 3FF65040 R/W
configuration
Slave status/higher
SPI_SLV_WR_STATUS_REG 3FF43030 3FF42030 3FF64030 3FF65030 R/W
master address
Write-buffer opera-
SPI_SLV_WRBUF_DLEN_REG 3FF43048 3FF42048 3FF64048 3FF65048 R/W
tion length
Read-buffer opera-
SPI_SLV_RDBUF_DLEN_REG 3FF4304C 3FF4204C 3FF6404C 3FF6504C R/W
tion length
Read data operation
SPI_SLV_RD_BIT_REG 3FF43064 3FF42064 3FF64064 3FF65064 R/W
length
User-defined command mode registers
Start user-defined
SPI_CMD_REG 3FF43000 3FF42000 3FF64000 3FF65000 R/W
command
SPI_ADDR_REG Address data 3FF43004 3FF42004 3FF64004 3FF65004 R/W

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Name Description SPI0 SPI1 SPI2 SPI3 Acc

User defined com-
SPI_USER_REG 3FF4301C 3FF4201C 3FF6401C 3FF6501C R/W
mand configuration
Address and dummy
SPI_USER1_REG 3FF43020 3FF42020 3FF64020 3FF65020 R/W
cycle configuration
Command length
SPI_USER2_REG and value configura- 3FF43024 3FF42024 3FF64024 3FF65024 R/W
tion
SPI_MOSI_DLEN_REG MOSI length 3FF43028 3FF42028 3FF64028 3FF65028 R/W
SPI_W0_REG SPI data register 0 3FF43080 3FF42080 3FF64080 3FF65080 R/W
SPI_W1_REG SPI data register 1 3FF43084 3FF42084 3FF64084 3FF65084 R/W
SPI_W2_REG SPI data register 2 3FF43088 3FF42088 3FF64088 3FF65088 R/W
SPI_W3_REG SPI data register 3 3FF4308C 3FF4208C 3FF6408C 3FF6508C R/W
SPI_W4_REG SPI data register 4 3FF43090 3FF42090 3FF64090 3FF65090 R/W
SPI_W5_REG SPI data register 5 3FF43094 3FF42094 3FF64094 3FF65094 R/W
SPI_W6_REG SPI data register 6 3FF43098 3FF42098 3FF64098 3FF65098 R/W
SPI_W7_REG SPI data register 7 3FF4309C 3FF4209C 3FF6409C 3FF6509C R/W
SPI_W8_REG SPI data register 8 3FF430A0 3FF420A0 3FF640A0 3FF650A0 R/W
SPI_W9_REG SPI data register 9 3FF430A4 3FF420A4 3FF640A4 3FF650A4 R/W
SPI_W10_REG SPI data register 10 3FF430A8 3FF420A8 3FF640A8 3FF650A8 R/W
SPI_W11_REG SPI data register 11 3FF430AC 3FF420AC 3FF640AC 3FF650AC R/W
SPI_W12_REG SPI data register 12 3FF430B0 3FF420B0 3FF640B0 3FF650B0 R/W
SPI_W13_REG SPI data register 13 3FF430B4 3FF420B4 3FF640B4 3FF650B4 R/W
SPI_W14_REG SPI data register 14 3FF430B8 3FF420B8 3FF640B8 3FF650B8 R/W
SPI_W15_REG SPI data register 15 3FF430BC 3FF420BC 3FF640BC 3FF650BC R/W
DMA configuration registers
DMA configuration
SPI_DMA_CONF_REG 3FF43100 3FF42100 3FF64100 3FF65100 R/W
register
DMA outlink address
SPI_DMA_OUT_LINK_REG 3FF43104 3FF42104 3FF64104 3FF65104 R/W
and configuration
DMA inlink address
SPI_DMA_IN_LINK_REG 3FF43108 3FF42108 3FF64108 3FF65108 R/W
and configuration
SPI_DMA_STATUS_REG DMA status 3FF4310C 3FF4210C 3FF6410C 3FF6510C RO
Descriptor address
SPI_IN_ERR_EOF_DES_ADDR_REG where an error 3FF43120 3FF42120 3FF64120 3FF65120 RO
occurs
Descriptor address
SPI_IN_SUC_EOF_DES_ADDR_REG 3FF43124 3FF42124 3FF64124 3FF65124 RO
where EOF occurs
Current descriptor
SPI_INLINK_DSCR_REG 3FF43128 3FF42128 3FF64128 3FF65128 RO
pointer
Next descriptor data
SPI_INLINK_DSCR_BF0_REG 3FF4312C 3FF4212C 3FF6412C 3FF6512C RO
pointer
Current descriptor
SPI_INLINK_DSCR_BF1_REG 3FF43130 3FF42130 3FF64130 3FF65130 RO
data pointer

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Name Description SPI0 SPI1 SPI2 SPI3 Acc

Relative buffer ad-
SPI_OUT_EOF_BFR_DES_ADDR_REG dress where EOF 3FF43134 3FF42134 3FF64134 3FF65134 RO
occurs
Descriptor address
SPI_OUT_EOF_DES_ADDR_REG 3FF43138 3FF42138 3FF64138 3FF65138 RO
where EOF occurs
Current descriptor
SPI_OUTLINK_DSCR_REG 3FF4313C 3FF4213C 3FF6413C 3FF6513C RO
pointer
Next descriptor data
SPI_OUTLINK_DSCR_BF0_REG 3FF43140 3FF42140 3FF64140 3FF65140 RO
pointer
Current descriptor
SPI_OUTLINK_DSCR_BF1_REG 3FF43144 3FF42144 3FF64144 3FF65144 RO
data pointer
DMA memory read
SPI_DMA_RSTATUS_REG 3FF43148 3FF42148 3FF64148 3FF65148 RO
status
DMA memory write
SPI_DMA_TSTATUS_REG 3FF4314C 3FF4214C 3FF6414C 3FF6514C RO
status
DMA interrupt registers
SPI_DMA_INT_RAW_REG Raw interrupt status 3FF43114 3FF42114 3FF64114 3FF65114 RO
Masked interrupt sta-
SPI_DMA_INT_ST_REG 3FF43118 3FF42118 3FF64118 3FF65118 RO
tus
SPI_DMA_INT_ENA_REG Interrupt enable bits 3FF43110 3FF42110 3FF64110 3FF65110 R/W
SPI_DMA_INT_CLR_REG Interrupt clear bits 3FF4311C 3FF4211C 3FF6411C 3FF6511C R/W

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7. SPI

7.8 Registers

Register 7.1: SPI_CMD_REG (0x0)

d)

)
ed
R
ve

US

rv
er

se
I_
s

SP
(re

(re
31 19 18 17 0

0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Reset

SPI_USR An SPI operation will be triggered when this bit is set. The bit will be cleared once the
operation is done. (R/W)

Register 7.2: SPI_ADDR_REG (0x4)

31 0

0x000000000 Reset

SPI_ADDR_REG It stores the transmitting address when master is in half-duplex mode or QSPI mode.
If the address length is bigger than 32 bits, SPI_SLV_WR_STATUS_REG contains the lower 32 bits.
The register in valid only when SPI_USR_ADDR is set to 1. (R/W)

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7. SPI

Register 7.3: SPI_CTRL_REG (0x8)

(re FR D_ RD R
se EA Q ER

DE
I_ EA O E

_M L
SP FR IT_ RD

O
UA

RD UA
SP rve D_ IO
SP WP ) IO
I_ _B _O

Q
I_ d D

ST _D
D_
SP RD IT

FA D
I_ _B

EA

I_ EA
)

)
ed

ed

ed
SP WR

FR

SP FR
rv

rv

rv
se

se

se
I_

I_

I_
SP

SP
(re

(re

(re
31 27 26 25 24 23 22 21 20 19 15 14 13 12 0

0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 Reset

SPI_WR_BIT_ORDER This bit determines the bit order for command, address and data in transmitted
signal. 1: sends LSB first; 0: sends MSB first. (R/W)

SPI_RD_BIT_ORDER This bit determines the bit order for received data in received signal. 1: receives
LSB first; 0: receives MSB first. (R/W)

SPI_FREAD_QIO This bit is used to enable four-line address writes and data reads in QSPI mode.
(R/W)

SPI_FREAD_DIO This bit is used to enable two-line address writes and data reads in QSPI mode.
(R/W)

SPI_WP This bit determines the write-protection signal output when SPI is idle in QSPI mode. 1:
output high; 0: output low. (R/W)

SPI_FREAD_QUAD This bit is used to enable four-line data reads in QSPI mode. (R/W)

SPI_FREAD_DUAL This bit is used to enable two-line data reads in QSPI mode. (R/W)

SPI_FASTRD_MODE Reserved.

Register 7.4: SPI_CTRL1_REG (0xC)

Y
E LA
_D
LD
O
_H

ed)
CS

rv
se
I_
SP

(re

31 28 27 0

0x05 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Reset

SPI_CS_HOLD_DELAY Reserved.

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7. SPI

Register 7.5: SPI_RD_STATUS_REG (0x10)

T
EX
S_

S
U

TU
AT

TA
ST

S
I_

I_
SP

SP
31 24 23 16 15 0

0x000 0x000 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Reset

SPI_STATUS_EXT Reserved.

SPI_STATUS Reserved.

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7. SPI

Register 7.6: SPI_CTRL2_REG (0x14)

DE
DE

DE

O
UM

M
DE

M
O

O
NU
M

_M

_M

H_
_N
O
NU

Y_
_M

IG
AY

AY

AY

E
A

E
Y_

M
_H
AY

IM
EL

EL

EL

EL

TI
LA

UT

_T
L

_D

_D

_D

_D

P_
DE

DE

LD
_O

TU
SI

SI

O
S_

IS

IS

ed
O

HO
CK
CS

SE
M

M
C

rv
I_

I_

I_

I_

I_

I_

I_

I_

I_
se
SP

SP

SP

SP

SP

SP

SP

SP

SP
re
31 28 27 26 25 23 22 21 20 18 17 16 15 12 11 8 7 4 3 0

0x00 0x0 0x0 0x0 0x0 0x0 0x00 0x00 0x01 0x01 Reset

SPI_CS_DELAY_NUM Reserved.

SPI_CS_DELAY_MODE Reserved.

SPI_MOSI_DELAY_NUM It is used to configure the number of system clock cycles by which the
MOSI signals are delayed. (R/W)

SPI_MOSI_DELAY_MODE This register field determines the way the MOSI signals are delayed by
SPI clock. (R/W)
After being delayed by SPI_MOSI_DELAY_NUM system clocks, the MOSI signals will then be de-
layed by the configuration of SPI_MOSI_DELAY_MODE, specifically:
0: no delay.
1: if SPI_CK_OUT_EDGE or SPI_CK_I_EDGE is set, the MOSI signals are delayed by half a cycle,
otherwise they are delayed by one cycle.
2: if SPI_CK_OUT_EDGE or SPI_CK_I_EDGE is set, the MOSI signals are delayed by one cycle,
otherwise they are delayed by half a cycle.
3: the MOSI signals are delayed one cycle.

SPI_MISO_DELAY_NUM It is used to configure the number of system clock cycles by which the
MISO signals are delayed. (R/W)

SPI_MISO_DELAY_MODE This register field determines the way MISO signals are delayed by SPI
clock. (R/W)
After being delayed by SPI_MISO_DELAY_NUM system clock, the MISO signals will then be de-
layed by the configuration of SPI_MISO_DELAY_MODE, specifically:
0: no delay.
1: if SPI_CK_OUT_EDGE or SPI_CK_I_EDGE is set, the MISO signals are delayed by half a cycle,
otherwise they are delayed by one cycle.
2: if SPI_CK_OUT_EDGE or SPI_CK_I_EDGE is set, the MISO signals are delayed by one cycle,
otherwise they are delayed by half a cycle.
3: the MISO signals are delayed by one cycle.

SPI_HOLD_TIME The number of SPI clock cycles by which CS pin signals are delayed. It is only valid
when SPI_CS_HOLD is set to 1. (R/W)

SPI_SETUP_TIME It is to configure the time between the CS signal active edge and the first SPI
clock edge. It is only valid in half-duplex mode or QSPI mode and when SPI_CS_SETUP is set to
1. (R/W)

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7. SPI

Register 7.7: SPI_CLOCK_REG (0x18)

LK
SC
SY

RE

H
U_

_L
_P

T_

_
NT

NT
Q

IV

CN
_E

KC

KC
D
K

LK

LK
CL

CL

CL
C

C
I_

I_

I_

I_

I_
SP

SP

SP

SP

SP
31 30 18 17 12 11 6 5 0

1 0 0 0 0 0 0 0 0 0 0 0 0 0 0x03 0x01 0x03 Reset

SPI_CLK_EQU_SYSCLK In master mode, when this bit is set to 1, SPI output clock is equal to system
clock; when set to 0, SPI output clock is divided from system clock. In slave mode, it should be
set to 0. (R/W)

SPI_CLKDIV_PRE In master mode, it is used to configure the pre-divider value for SPI output clock.
It is only valid when SPI_CLK_EQU_SYSCLK is 0. In slave mode, it should be set to 0. (R/W)

SPI_CLKCNT_N In master mode, it is used to configure the divider for SPI output clock. It is only
valid when SPI_CLK_EQU_SYSCLK is 0. In slave mode, it should be set to 0. (R/W)

SPI_CLKCNT_H In master mode, SPI_CLKCNT_H = ⌊ SPI_CLKCNT_N+1

2 –1⌋. It is only valid when
SPI_CLK_EQU_SYSCLK is 0. In slave mode, it should be set to 0. (R/W)

SPI_CLKCNT_L In master mode, it is equal to SPI_CLKCNT_N. It is only valid when

SPI_CLK_EQU_SYSCLK is 0. In slave mode, it should be set to 0. (R/W)

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7. SPI

Register 7.8: SPI_USER_REG (0x1C)

HP T
T
IG AR
AR
IS I E
_H P

SP ed) _OR ER
R
M I_H IDL
O GH
SP US _DU R D

DE
E RD

I_ _S G GE
I_ R D N

I_ _B _D D
R_ OS Y_

_ TE AL
SP US AD MA

SP US _MI MY

SP WR ITE UA

se BYT _O
SP FW TE IO
SP FW ITE IO

SP CS _ED ED
US M M

RD Y U

CS E E
_H TUP
I_ R_ SO

SP US _DU I
I_ R_ M

I_ RI _Q

I_ R _Q
I_ R M

I_ R S
I_ R_ M

I_ R _D

LD
I_ _I _

N
SP US MO
SP US _CO

SP CK UT

DI
SP FW ITE

UT
I_ _O
)

)
I_ R
ed

ed
I_ R

SP SIO
SP FW

DO
SP CK
SP US

rv

rv

rv
se

se
I_

I_
I_

I_

I_
SP

SP

SP
(re

(re

(re
31 30 29 28 27 26 25 24 23 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 1 0

1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 Reset

SPI_USR_COMMAND This bit enables the command phase of an SPI operation in SPI half-duplex
mode and QSPI mode. (R/W)

SPI_USR_ADDR This bit enables the address phase of an SPI operation in SPI half-duplex mode and
QSPI mode. (R/W)

SPI_USR_DUMMY This bit enables the dummy phase of an SPI operation in SPI half-duplex mode
and QSPI mode. (R/W)

SPI_USR_MISO This bit enables the read-data phase of an SPI operation in SPI half-duplex mode
and QSPI mode. (R/W)

SPI_USR_MOSI This bit enables the write-data phase of an SPI operation in SPI half-duplex mode
and QSPI mode. (R/W)

SPI_USR_DUMMY_IDLE The SPI clock signal is disabled in the dummy phase when the bit is set in
SPI half-duplex mode and QSPI mode. (R/W)

SPI_USR_MOSI_HIGHPART If set, MOSI data is stored in SPI_W8 ~ SPI_W15 of the SPI buffer.
(R/W)

SPI_USR_MISO_HIGHPART If set, MISO data is stored in SPI_W8 ~ SPI_W15 of the SPI buffer.
(R/W)

SPI_SIO Set this bit to enable three-line half-duplex communication. (R/W)

SPI_FWRITE_QIO Reserved.

SPI_FWRITE_DIO Reserved.

SPI_FWRITE_QUAD Reserved.

SPI_FWRITE_DUAL Reserved.

SPI_WR_BYTE_ORDER This bit determines the byte order of the command, address and data in
transmitted signal. 1: big-endian; 0: little-endian. (R/W)

SPI_RD_BYTE_ORDER This bit determines the byte order of received data in transmitted signal. 1:
big-endian; 0: little_endian. (R/W)

SPI_CK_OUT_EDGE This bit, combined with SPI_MOSI_DELAY_MODE, sets the MOSI signal delay
mode. It is only valid in master mode. (R/W)

SPI_CK_I_EDGE In slave mode, the bit is the same as SPI_CK_OUT_EDGE in master mode. It is
combined with SPI_MISO_DELAY_MODE. It is only valid in slave mode. (R/W)

Continued on the next page...

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7. SPI

Register 7.8: SPI_USER_REG (0x1C)

Continued from the previous page...

SPI_CS_SETUP Setting this bit enables a delay between CS active edge and the first clock edge,
in multiples of one SPI clock cycle. In full-duplex mode and QSPI mode, setting this bit results in
(SPI_SETUP_TIME + 1.5) SPI clock cycles delay. In full-duplex mode, there will be 1.5 SPI clock
cycles delay for mode0 and mode2, and 1 SPI clock cycle delay for mode1 and mode3. (R/W)

SPI_CS_HOLD Setting this bit enables a delay between the end of a transmission and CS being
inactive, as specified in SPI_HOLD_TIME. (R/W)

SPI_DOUTDIN Set the bit to enable full-duplex communication. (R/W)

Register 7.9: SPI_USER1_REG (0x20)

EN
EL
CL
N
LE

CY
IT

Y_
_B

M
DR

UM
AD

_D
R_

)
ed

SR
US

rv

U
se
I_

I_
SP

SP
(re

31 26 25 8 7 0

23 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 7 Reset

SPI_USR_ADDR_BITLEN It indicates the bit length of the transmitted address minus one in half-
duplex mode and QSPI mode, in multiples of one bit. It is only valid when SPI_USR_ADDR is set
to 1. (RO)

SPI_USR_DUMMY_CYCLELEN It indicates the number of SPI clock cycles for the dummy phase
minus one in SPI half-duplex mode and QSPI mode. It is only valid when SPI_USR_DUMMY is set
to 1. (R/W)

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7. SPI

Register 7.10: SPI_USER2_REG (0x24)

UE
E
TL

L
VA
BI
D_

D_
AN

AN
M

M
M

M
CO

O
_C
R_

)
ed

R
US

US
rv
se
I_

I_
SP

SP
(re
31 28 27 16 15 0

7 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Reset

SPI_USR_COMMAND_BITLEN It indicates the bit length of the command phase minus one in SPI
half-duplex mode and QSPI mode. It is only valid when SPI_USR_COMMAND is set to 1. (R/W)

SPI_USR_COMMAND_VALUE It indicates the value of the command to be transmitted in SPI half-

duplex mode and QSPI mode. It is only valid when SPI_USR_COMMAND is set to 1. (R/W)

Register 7.11: SPI_MOSI_DLEN_REG (0x28)

EN
TL
BI
_D
SI
O
M
R_
d)
ve

US
r
se

I_
SP
(re

31 24 23 0

0 0 0 0 0 0 0 0 0x0000000 Reset

SPI_USR_MOSI_DBITLEN It indicates the length of MOSI data minus one, in multiples of one bit. It
is only valid when SPI_USR_MOSI is set to 1 in master mode. (R/W)

Register 7.12: SPI_MISO_DLEN_REG (0x2C)

EN
TL
BI
_D
O
IS
_M
)
ed

SR
rv

_U
se

I
SP
(re

31 24 23 0

0 0 0 0 0 0 0 0 0x0000000 Reset

SPI_USR_MISO_DBITLEN It indicates the length of MISO data minus one, in multiples of one bit. It
is only valid when SPI_USR_MISO is set to 1 in master mode. (R/W)

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Register 7.13: SPI_SLV_WR_STATUS_REG (0x30)

31 0

0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Reset

SPI_SLV_WR_STATUS_REG In the slave mode this register is the status register for the master to
write the slave. In the master mode, if the address length is bigger than 32 bits, this register
contains the lower 32 bits. (R/W)

Register 7.14: SPI_PIN_REG (0x34)

L
G E

EL

O
ED IV
E

_S

_P
E_ CT

CK

CS
DL A
_I EP_

R_

R_

SP CS DIS

0_ IS
S
se DIS

DI
TE

TE
CK E

CS D
I_ _K

I_ 2_
I_ 1_
SP CS )

SP ed)
AS

AS
I_ d

ed

ed

K_
SP rve

SP CS
rv

rv

rv
M

C
se

se

se
I_

I_

I_

I_
SP

SP

SP
(re

(re

(re

(re
31 30 29 28 14 13 11 10 9 8 6 5 4 3 2 1 0

0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 0 Reset

SPI_CS_KEEP_ACTIVE This bit is only used in master mode where when it is set, the CS signal will
keep active. (R/W)

SPI_CK_IDLE_EDGE This bit is only used in master mode to configure the logicl level of SPI output
clock in idle state. (R/W)
1: the spi_clk line keeps high when idle;
0: the spi_clk line keeps low when idle.

SPI_MASTER_CK_SEL Reserved.

SPI_MASTER_CS_POL Reserved.

SPI_CK_DIS Reserved.

SPI_CS2_DIS This bit enables the SPI CS2 signal. 1: disables CS2; 0: enables CS2. (R/W)

SPI_CS1_DIS This bit enables the SPI CS1 signal. 1: disables CS1; 0: enables CS1. (R/W)

SPI_CS0_DIS This bit enables the SPI CS0 signal. 1: disables CS0; 0: enables CS0. (R/W)

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7. SPI

Register 7.15: SPI_SLAVE_REG (0x38)

D
DE TA_ N
FI EN

AN

I_ V_ D _I EN

_D NE
I_ V_ _ _IN EN

V_ R_ A_D NE
I_ V_ _ E N

NE
D_ _S _E

I_ AN _B _ N

_B F_ NE
SP SL WR ON NTE
SP TR RD BUF TE
NE

SP SL S_ UF INT

UF DO
CM RD UF

SP SL WR TA NT

T O
TE

O
RD BU O
M

I_ V_W _S _D
TA
V_ R_ _B

I_ V_ _S _I
O

I_ V_ _ N
I_ V_W _R E
I_ V_ M T

SP SL RD STA

SP SL RD STA
SP SL WR TE
_C
SP SL WR OD

_S
SP SL E_ E

DE
CN
I_ AV ES

I_ V_ IN
ST

ST

I_ _MO
SP SL C_R

S_

SP SL S_
LA

LA
AN

I_ AN
)
V_

V_

_I
ed
I_ N

CS
SP SY

TR

SP R
SL

SL

SL

SL
rv

T
se
I_

I_

I_

I_

I_
SP

SP

SP

SP

SP

SP
(re
31 30 29 28 27 26 23 22 20 19 17 16 12 11 10 9 8 7 6 5 4 3 2 1 0

0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Reset

SPI_SYNC_RESET When set, it resets the latched values of the SPI clock line, CS line and data line.
(R/W)

SPI_SLAVE_MODE This bit is used to set the mode of the SPI device. (R/W)
1: slave mode;
0: master mode.

SPI_SLV_WR_RD_BUF_EN This bit is only used in slave half-duplex mode, where when it is set, the
write and read data commands are enabled. (R/W)

SPI_SLV_WR_RD_STA_EN This bit is only used in slave half-duplex mode, where when it is set, the
write and read status commands are enabled. (R/W)

SPI_SLV_CMD_DEFINE Reserved.

SPI_TRANS_CNT The counter for operations in both the master mode and the slave mode. (RO)

SPI_SLV_LAST_STATE In slave mode, this contains the state of the SPI state machine. (RO)

SPI_SLV_LAST_COMMAND Reserved.

SPI_CS_I_MODE Reserved.

SPI_TRANS_INTEN The interrupt enable bit for the SPI_TRANS_DONE_INT interrupt. (R/W)

SPI_SLV_WR_STA_INTEN The interrupt enable bit for the SPI_SLV_WR_STA_INT interrupt. (R/W)

SPI_SLV_RD_STA_INTEN The interrupt enable bit for the SPI_SLV_RD_STA_INT interrupt. (R/W)

SPI_SLV_WR_BUF_INTEN The interrupt enable bit for the SPI_SLV_WR_BUF_INT interrupt. (R/W)

SPI_SLV_RD_BUF_INTEN The interrupt enable bit for the SPI_SLV_RD_BUF_INT interrupt. (R/W)

SPI_TRANS_DONE The raw interrupt status bit for the SPI_TRANS_DONE_INT interrupt. It is set by
hardware and cleared by software. (R/W)

SPI_SLV_WR_STA_DONE The raw interrupt status bit for the SPI_SLV_WR_STA_INT interrupt. It is
set by hardware and cleared by software, and only applicable to slave half-duplex mode. (R/W)

SPI_SLV_RD_STA_DONE The raw interrupt status bit for the SPI_SLV_RD_STA_INT interrupt. It is
set by hardware and cleared by software, and only applicable to slave half-duplex mode. (R/W)

Continued on the next page...

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7. SPI

Register 7.15: SPI_SLAVE_REG (0x38)

Continued from the previous page ...

SPI_SLV_WR_BUF_DONE The raw interrupt status bit for the SPI_SLV_WR_BUF_INT interrupt. It is
set by hardware and cleared by software, and only applicable to slave half-duplex mode. (R/W)

SPI_SLV_RD_BUF_DONE The raw interrupt status bit for the SPI_SLV_RD_BUF_INT interrupt. It is
set by hardware and cleared by software, and only applicable to slave half-duplex mode. (R/W)

Register 7.16: SPI_SLAVE1_REG (0x3C)

M N
K

BU _D MY EN

EN
DU M N
M Y_E
AC

F_ UM _E
EN
EA EN

RD UF UM Y_

Y_
LE
EN

DB

TL

V_ RB _D MM
_R T_

IT
TL

_B
US AS

_B

I_ V_W ST DU
BI

DR
AT _F

DR
S_

SP SL D A_
ST US

AD
D

A
U

I_ _R ST
_A
AT

V_ AT

R_

SP SL WR
RD
ST

SL T

_W
I_ V_S

)
V_

I_ _
ed

LV

LV

V
V
SL

SP SL

SP L

SL
rv

S
se
I_

I_

I_

I_

I_
SP

SP

SP

SP

SP
(re

31 27 26 25 24 16 15 10 9 4 3 2 1 0

0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0x00 0x00 0 0 0 0 Reset

SPI_SLV_STATUS_BITLEN It is only used in slave half-duplex mode to configure the length of the
master writing into the status register. (R/W)

SPI_SLV_STATUS_FAST_EN Reserved.

SPI_SLV_STATUS_READBACK Reserved.

SPI_SLV_RD_ADDR_BITLEN It indicates the address length in bits minus one for a slave-read oper-
ation. It is only valid in slave half-duplex mode. (R/W)

SPI_SLV_WR_ADDR_BITLEN It indicates the address length in bits minus one for a slave-write op-
eration. It is only valid in slave half-duplex mode. (R/W)

SPI_SLV_WRSTA_DUMMY_EN In slave mode, this bit enables the dummy phase for write-status
operations. It is only valid in slave half-duplex mode.(R/W)

SPI_SLV_RDSTA_DUMMY_EN In slave mode, this bit enables the dummy phase for read-status
operations. It is only valid in slave half-duplex mode. (R/W)

SPI_SLV_WRBUF_DUMMY_EN In slave mode, this bit enables the dummy phase for write-buffer
operations. It is only valid in slave half-duplex mode. (R/W)

SPI_SLV_RDBUF_DUMMY_EN In slave mode, this bit enables the dummy phase for read-buffer
operations. It is only valid in slave half-duplex mode. (R/W)

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7. SPI

Register 7.17: SPI_SLAVE2_REG (0x40)

EN
EN

N
E

LE
EL

EL
EL

E
CL

CL
CL

CL
CY

CY
CY

CY
Y_

Y_
Y_

Y_
M

M
M

M
UM

M
M

M
DU
DU

DU
_D

_
F_

A_
UF

TA
BU

ST
RB

RS
RD

RD
W

W
V_

V_

V_
LV
SL

SL

SL
S
I_

I_

I_

I_
SP

SP

SP

SP
31 24 23 16 15 8 7 0

0 0 0 0 0 0 0 0 0x000 0x000 0x000 Reset

SPI_SLV_WRBUF_DUMMY_CYCLELEN It indicates the number of SPI clock cycles minus one for
the dummy phase for write-data operations. It is only valid when SPI_SLV_WRBUF_DUMMY_EN
is set to 1 in slave half-duplex mode. (R/W)

SPI_SLV_RDBUF_DUMMY_CYCLELEN It indicates the number of SPI clock cycles minus one for
the dummy phase for read-data operations. It is only valid when SPI_SLV_RDBUF_DUMMY_EN is
set to 1 in slave half-duplex mode. (R/W)

SPI_SLV_WRSTA_DUMMY_CYCLELEN It indicates the number of SPI clock cycles minus

one for the dummy phase for write-status register operations. It is only valid when
SPI_SLV_WRSTA_DUMMY_EN is set to 1 in slave half-duplex mode. (R/W)

SPI_SLV_RDSTA_DUMMY_CYCLELEN It indicates the number of SPI clock cycles minus

one for the dummy phase for read-status register operations. It is only valid when
SPI_SLV_RDSTA_DUMMY_EN is set to 1 in slave half-duplex mode. (R/W)

Register 7.18: SPI_SLAVE3_REG (0x44)

E
UE

UE
UE

LU
L

L
L

VA
VA

VA
VA

D_
D_

D_
D_

M
CM

CM
CM

_C
_

F_
_

UF
TA

TA

BU
RB
RS

S
RD

RD
W

W
V_

V_

V_

V_
SL

SL

SL

SL
I_

I_

I_

I_
SP

SP

SP

SP

31 24 23 16 15 8 7 0

0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Reset

SPI_SLV_WRSTA_CMD_VALUE Reserved.

SPI_SLV_RDSTA_CMD_VALUE Reserved.

SPI_SLV_WRBUF_CMD_VALUE Reserved.

SPI_SLV_RDBUF_CMD_VALUE Reserved.

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7. SPI

Register 7.19: SPI_SLV_WRBUF_DLEN_REG (0x48)

N
LE
IT
DB
U F_
RB
W
)

V_
ed

SL
rv
se

I_
SP
(re

31 24 23 0

0 0 0 0 0 0 0 0 0x0000000 Reset

SPI_SLV_WRBUF_DBITLEN It indicates the length of written data minus one, in multiples of one bit.
It is only valid in slave half-duplex mode. (R/W)

Register 7.20: SPI_SLV_RDBUF_DLEN_REG (0x4C)

EN
TL
DBI
F_
BU
RD
d)

V_
ve

SL
r
se

I_
SP
(re

31 24 23 0

0 0 0 0 0 0 0 0 0x0000000 Reset

SPI_SLV_RDBUF_DBITLEN It indicates the length of read data minus one, in multiples of one bit. It
is only valid in slave half-duplex mode. (R/W)

Register 7.21: SPI_SLV_RD_BIT_REG (0x64)

T
BI
A_
AT
RD
)

_
d

LV
ve

_S
r
se

I
SP
(re

31 24 23 0

0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Reset

SPI_SLV_RDATA_BIT It indicates the bit length of data the master reads from the slave, minus one.
It is only valid in slave half-duplex mode. (R/W)

Register 7.22: SPI_Wn_REG (n: 0-15) (0x80+4*n)

31 0

0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Reset

SPI_Wn_REG Data buffer. (R/W)

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7. SPI

Register 7.23: SPI_TX_CRC_REG (0xC0)

31 0

0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Reset

SPI_TX_CRC_REG Reserved.

Register 7.24: SPI_EXT2_REG (0xF8)

d)
ve

ST
er

I_
s

SP
(re
31 3 2 0

0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Reset

SPI_ST The current state of the SPI state machine: (RO)

0: idle state
1: preparation state
2: send command state
3: send data state
4: read data state
5: write data state
6: wait state
7: done state

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7. SPI

Register 7.25: SPI_DMA_CONF_REG (0x100)

O BU _E N

N
_E R_ ST _E

DE E
F_ R N
O _
UT C R T

M ST
O S U S

T
SP rve _RX STO E

I_ TD _B UR

(re _RS ST _RS

se A _ U

P
I_ d _S P
TO
(re DM _TX TIN

SP OU R _B

IN R O
SP OU M_ T
I_ SC TA
I_ A ON

I_ B RS
I_ T_ FIF
SP IND _DA
SP DM _C

SP AH M_

T
d)

S P OU )

)
I_ A

ed

ed
I_ B
I_ T
SP DM
ve

SP AH
rv

rv
er

se

se
I_

I_
s

SP

SP
(re

(re
31 17 16 15 14 13 12 11 10 9 8 6 5 4 3 2 1 0

0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 Reset

SPI_DMA_CONTINUE This bit enables SPI DMA continuous data TX/RX mode. (R/W)

SPI_DMA_TX_STOP When in continuous TX/RX mode, setting this bit stops sending data. (R/W)

SPI_DMA_RX_STOP When in continuous TX/RX mode, setting this bit stops receiving data. (R/W)

SPI_OUT_DATA_BURST_EN SPI DMA reads data from memory in burst mode. (R/W)

SPI_INDSCR_BURST_EN SPI DMA reads inlink descriptor in burst mode. (R/W)

SPI_OUTDSCR_BURST_EN SPI DMA reads outlink descriptor in burst mode. (R/W)

SPI_OUT_EOF_MODE DMA out-EOF-flag generation mode. (R/W)

1: out-EOF-flag is generated when DMA has popped all data from the FIFO;
0: out-EOF-flag is generated when DMA has pushed all data to the FIFO.

SPI_AHBM_RST reset SPI DMA AHB master. (R/W)

SPI_AHBM_FIFO_RST This bit is used to reset SPI DMA AHB master FIFO pointer. (R/W)

SPI_OUT_RST The bit is used to reset DMA out-FSM and out-data FIFO pointer. (R/W)

SPI_IN_RST The bit is used to reset DMA in-DSM and in-data FIFO pointer. (R/W)

Register 7.26: SPI_DMA_OUT_LINK_REG (0x104)

_S RT T
NK TA R
LI _S TA

DR
P
TO
UT K S

D
O IN RE

_A
I_ TL K_

NK
SP OU IN

LI
I_ TL
SP OU )

)
I_ d

ed

UT
SP rve

rv

O
se

se

I_
SP
(re

(re

31 30 29 28 27 20 19 0

0 0 0 0 0 0 0 0 0 0 0 0 0x000000 Reset

SPI_OUTLINK_RESTART Set the bit to add new outlink descriptors. (R/W)

SPI_OUTLINK_START Set the bit to start to use outlink descriptor. (R/W)

SPI_OUTLINK_STOP Set the bit to stop to use outlink descriptor. (R/W)

SPI_OUTLINK_ADDR The address of the first outlink descriptor. (R/W)

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7. SPI

Register 7.27: SPI_DMA_IN_LINK_REG (0x108)

E T
_S RT T

_R
NK TA R
LI _S TA

DR
TO
P
TO
IN K S

D
I_ IN RE

_A

_A
SP INL K_

NK
I_ IN

IN
SP INL )

)
I_ d

ed

LI
L
SP rve

IN

IN
rv
se

se

I_

I_
SP

SP
(re

(re
31 30 29 28 27 21 20 19 0

0 0 0 0 0 0 0 0 0 0 0 0 0x000000 Reset

SPI_INLINK_RESTART Set the bit to add new inlink descriptors. (R/W)

SPI_INLINK_START Set the bit to start to use inlink descriptor. (R/W)

SPI_INLINK_STOP Set the bit to stop to use inlink descriptor. (R/W)

SPI_INLINK_AUTO_RET when the bit is set, inlink descriptor jumps to the next descriptor when a
packet is invalid. (R/W)

SPI_INLINK_ADDR The address of the first inlink descriptor. (R/W)

Register 7.28: SPI_DMA_STATUS_REG (0x10C)

N
RX N
_E
A_ X_E
DM T
I_ A_
d)

SP DM
e
rv
se

I_
SP
(re

31 2 1 0

0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Reset

SPI_DMA_TX_EN SPI DMA write-data status bit. (RO)

SPI_DMA_RX_EN SPI DMA read-data status bit. (RO)

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7. SPI

Register 7.29: SPI_DMA_INT_ENA_REG (0x110)

EN A
T_ EN
Y_ IN A

A
PT R_ _EN
I N T_
A

EM RO T
I_ E _E IN A EN

R_ _ER _IN
SP IN_ UC E_ EN T_

SP OU K_ INT T_ NA
IN IN C N A

SC R OR
SP INL ON OF NT_ A

I_ TL DS _E EN
I_ S N T_ IN

I_ D _E _I N
I_ IN E_ _IN E

_D SC RR
LI K R_ A
SP IN_ DO IN F_

SP IN_ RR OF T_E

NK _D E
I_ T_ F_ EO
SP OU _EO AL_
I_ T T
SP OU _TO
)
ed

I_ T
SP OU
rv
se

I_
SP
(re
31 9 8 7 6 5 4 3 2 1 0

0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Reset

SPI_OUT_TOTAL_EOF_INT_ENA The interrupt enable bit for the SPI_OUT_TOTAL_EOF_INT inter-

rupt. (R/W)

SPI_OUT_EOF_INT_ENA The interrupt enable bit for the SPI_OUT_EOF_INT interrupt. (R/W)

SPI_OUT_DONE_INT_ENA The interrupt enable bit for the SPI_OUT_DONE_INT interrupt. (R/W)

SPI_IN_SUC_EOF_INT_ENA The interrupt enable bit for the SPI_IN_SUC_EOF_INT interrupt. (R/W)

SPI_IN_ERR_EOF_INT_ENA The interrupt enable bit for the SPI_IN_ERR_EOF_INT interrupt. (R/W)

SPI_IN_DONE_INT_ENA The interrupt enable bit for the SPI_IN_DONE_INT interrupt. (R/W)

SPI_INLINK_DSCR_ERROR_INT_ENA The interrupt enable bit for the

SPI_INLINK_DSCR_ERROR_INT interrupt. (R/W)

SPI_OUTLINK_DSCR_ERROR_INT_ENA The interrupt enable bit for the

SPI_OUTLINK_DSCR_ERROR_INT interrupt. (R/W)

SPI_INLINK_DSCR_EMPTY_INT_ENA The interrupt enable bit for the

SPI_INLINK_DSCR_EMPTY_INT interrupt. (R/W)

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7. SPI

Register 7.30: SPI_DMA_INT_RAW_REG (0x114)

RA W
T_ RA
Y_ IN W

W
PT R_ _RA
IN T_
W

EM RO T
I_ E _E IN W RA

R_ _ER _IN
SP OU K_ INT T_ AW
IN IN C A W
SP IN_ UC E_ RA T_

SC R OR
SP INL ON OF NT_ W

I_ TL DS _R RA
I_ S N T_ IN

I_ D _E _I A
I_ IN E_ _IN R

LI K R_ W
_D SC RR
SP IN_ RR OF T_R
SP IN_ DO IN F_

NK _D E
I_ T_ F_ EO
SP OU _EO AL_
I_ T T
SP OU _TO
d)

I_ T
ve

SP OU
r
se

I_
SP
(re
31 9 8 7 6 5 4 3 2 1 0

0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Reset

SPI_OUT_TOTAL_EOF_INT_RAW The raw interrupt status bit for the SPI_OUT_TOTAL_EOF_INT in-
terrupt. (RO)

SPI_OUT_EOF_INT_RAW The raw interrupt status bit for the SPI_OUT_EOF_INT interrupt. (RO)

SPI_OUT_DONE_INT_RAW The raw interrupt status bit for the SPI_OUT_DONE_INT interrupt. (RO)

SPI_IN_SUC_EOF_INT_RAW The raw interrupt status bit for the SPI_IN_SUC_EOF_INT interrupt.
(RO)

SPI_IN_ERR_EOF_INT_RAW The raw interrupt status bit for the SPI_IN_ERR_EOF_INT interrupt.
(RO)

SPI_IN_DONE_INT_RAW The raw interrupt status bit for the SPI_IN_DONE_INT interrupt. (RO)

SPI_INLINK_DSCR_ERROR_INT_RAW The raw interrupt status bit for the

SPI_INLINK_DSCR_ERROR_INT interrupt. (RO)

SPI_OUTLINK_DSCR_ERROR_INT_RAW The raw interrupt status bit for the

SPI_OUTLINK_DSCR_ERROR_INT interrupt. (RO)

SPI_INLINK_DSCR_EMPTY_INT_RAW The raw interrupt status bit for the

SPI_INLINK_DSCR_EMPTY_INT interrupt. (RO)

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7. SPI

Register 7.31: SPI_DMA_INT_ST_REG (0x118)

T_ ST
PT R_ _ST

ST
IN T_
Y_ IN
EM RO T
R_ _ER _IN
ST
SP IN_ UC E_ ST T_

SC R OR
I_ IN E_ _IN ST
I_ TL DS _S ST
I_ S N T_ IN

I_ D E I T

_D SC RR
SP IN_ RR OF T_S
SP IN_ DO IN F_

SP INL ON OF NT_
SP OU K_ INT T_
IN IN C T
NK _D E
I_ T_ F_ EO

LI K R_
I_ E _E IN
_
SP OU _EO AL_
I_ T T

_
SP OU _TO
)
ed

I_ T
SP OU
rv
se

I_
SP
(re
31 9 8 7 6 5 4 3 2 1 0

0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Reset

SPI_OUT_TOTAL_EOF_INT_ST The masked interrupt status bit for the SPI_OUT_TOTAL_EOF_INT

interrupt. (RO)

SPI_OUT_EOF_INT_ST The masked interrupt status bit for the SPI_OUT_EOF_INT interrupt. (RO)

SPI_OUT_DONE_INT_ST The masked interrupt status bit for the SPI_OUT_DONE_INT interrupt.
(RO)

SPI_IN_SUC_EOF_INT_ST The masked interrupt status bit for the SPI_IN_SUC_EOF_INT interrupt.
(RO)

SPI_IN_ERR_EOF_INT_ST The masked interrupt status bit for the SPI_IN_ERR_EOF_INT interrupt.
(RO)

SPI_IN_DONE_INT_ST The masked interrupt status bit for the SPI_IN_DONE_INT interrupt. (RO)

SPI_INLINK_DSCR_ERROR_INT_ST The masked interrupt status bit for the

SPI_INLINK_DSCR_ERROR_INT interrupt. (RO)

SPI_OUTLINK_DSCR_ERROR_INT_ST The masked interrupt status bit for the

SPI_OUTLINK_DSCR_ERROR_INT interrupt. (RO)

SPI_INLINK_DSCR_EMPTY_INT_ST The masked interrupt status bit for the

SPI_INLINK_DSCR_EMPTY_INT interrupt. (RO)

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Register 7.32: SPI_DMA_INT_CLR_REG (0x11C)

CL R
T_ CL
Y_ IN R

R
PT R_ _CL
IN T_
R

EM RO T
I_ E _E IN R CL

R_ _ER _IN
SP IN_ C E_ L T_

SP OU K_ INT T_ LR
IN IN C L R

SC R OR
SP INL ON OF NT_ R

I_ TL DS _C CL
I_ SU N T_C IN

I_ IN E_ _IN C
I_ D _E _I L

_D SC RR
LI K R_ R
SP IN_ RR OF T_C
SP IN_ _DO _IN OF_

NK _D E
I_ T F E
SP OU _EO AL_
I_ T T
SP OU _TO
)
ed

I_ T
SP OU
rv
se

I_
SP
(re
31 9 8 7 6 5 4 3 2 1 0

0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Reset

SPI_OUT_TOTAL_EOF_INT_CLR Set this bit to clear the SPI_OUT_TOTAL_EOF_INT interrupt. (R/W)

SPI_OUT_EOF_INT_CLR Set this bit to clear the SPI_OUT_EOF_INT interrupt. (R/W)

SPI_OUT_DONE_INT_CLR Set this bit to clear the SPI_OUT_DONE_INT interrupt. (R/W)

SPI_IN_SUC_EOF_INT_CLR Set this bit to clear the SPI_IN_SUC_EOF_INT interrupt. (R/W)

SPI_IN_ERR_EOF_INT_CLR Set this bit to clear the SPI_IN_ERR_EOF_INT interrupt. (R/W)

SPI_IN_DONE_INT_CLR Set this bit to clear the SPI_IN_DONE_INT interrupt. (R/W)

SPI_INLINK_DSCR_ERROR_INT_CLR Set this bit to clear the SPI_INLINK_DSCR_ERROR_INT in-

terrupt. (R/W)

SPI_OUTLINK_DSCR_ERROR_INT_CLR Set this bit to clear the

SPI_OUTLINK_DSCR_ERROR_INT interrupt. (R/W)

SPI_INLINK_DSCR_EMPTY_INT_CLR Set this bit to clear the SPI_INLINK_DSCR_EMPTY_INT in-

terrupt. (R/W)

Register 7.33: SPI_IN_ERR_EOF_DES_ADDR_REG (0x120)

31 0

0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Reset

SPI_IN_ERR_EOF_DES_ADDR_REG The inlink descriptor address when SPI DMA encountered an

error in receiving data. (RO)

Register 7.34: SPI_IN_SUC_EOF_DES_ADDR_REG (0x124)

31 0

0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Reset

SPI_IN_SUC_EOF_DES_ADDR_REG The last inlink descriptor address when SPI DMA encountered
EOF. (RO)

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Register 7.35: SPI_INLINK_DSCR_REG (0x128)

31 0

0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Reset

SPI_INLINK_DSCR_REG The address of the current inlink descriptor. (RO)

Register 7.36: SPI_INLINK_DSCR_BF0_REG (0x12C)

31 0

0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Reset

SPI_INLINK_DSCR_BF0_REG The address of the next inlink descriptor. (RO)

Register 7.37: SPI_INLINK_DSCR_BF1_REG (0x130)

31 0

0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Reset

SPI_INLINK_DSCR_BF1_REG The address of the next inlink data buffer. (RO)

Register 7.38: SPI_OUT_EOF_BFR_DES_ADDR_REG (0x134)

31 0

0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Reset

SPI_OUT_EOF_BFR_DES_ADDR_REG The buffer address corresponding to the outlink descriptor

that produces EOF. (RO)

Register 7.39: SPI_OUT_EOF_DES_ADDR_REG (0x138)

31 0

0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Reset

SPI_OUT_EOF_DES_ADDR_REG The last outlink descriptor address when SPI DMA encountered
EOF. (RO)

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Register 7.40: SPI_OUTLINK_DSCR_REG (0x13C)

31 0

0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Reset

SPI_OUTLINK_DSCR_REG The address of the current outlink descriptor. (RO)

Register 7.41: SPI_OUTLINK_DSCR_BF0_REG (0x140)

31 0

0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Reset

SPI_OUTLINK_DSCR_BF0_REG The address of the next outlink descriptor. (RO)

Register 7.42: SPI_OUTLINK_DSCR_BF1_REG (0x144)

31 0

0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Reset

SPI_OUTLINK_DSCR_BF1_REG The address of the next outlink data buffer. (RO)

Register 7.43: SPI_DMA_RSTATUS_REG (0x148)

S
ES
UL Y
_F T

DR
L
O P
IF EM

AD
)
_F _

S_
ed
TX FIFO

E
rv

_D
se
_
TX

TX
(re

31 30 29 20 19 0

0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Reset

TX_FIFO_EMPTY The SPI DMA TX FIFO is empty. (RO)

TX_FIFO_FULL The SPI DMA TX FIFO is full. (RO)

TX_DES_ADDRESS The LSB of the SPI DMA outlink descriptor address. (RO)

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Register 7.44: SPI_DMA_TSTATUS_REG (0x14C)

S
ES
UL Y
_F T

DR
L
O P
IF EM

AD
_F O_

d)

S_
ve
RX FIF

E
r

_D
se
_
RX

RX
(re
31 30 29 20 19 0

0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Reset

RX_FIFO_EMPTY The SPI DMA RX FIFO is empty. (RO)

RX_FIFO_FULL The SPI DMA RX FIFO is full. (RO)

RX_DES_ADDRESS The LSB of the SPI DMA inlink descriptor address. (RO)

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8. SDIO Slave

8.1 Overview
The ESP32 features hardware support for the industry-standard Secure Digital (SD) device interface that
conforms to the SD Input/Output (SDIO) Specification Version 2.0. This allows a host controller to access the
ESP32 via an SDIO bus protocol, enabling high-speed data transfer.

The SDIO interface may be used to read ESP32 SDIO registers directly and access shared memory via Direct
Memory Access (DMA), thus reducing processing overhead while maintaining high performance.

8.2 Features
• Meets SDIO V2.0 specification

• Supports SDIO SPI, 1-bit, and 4-bit transfer modes

• Full host clock range of 0 ~ 50 MHz

• Configurable sample and drive clock edge

• Integrated, SDIO-accessible registers for information interaction

• Supports SDIO interrupt mechanism

• Automatic data padding

• Block size of up to 512 bytes

• Interrupt vector between Host and Slave for bidirectional interrupt

• Supports DMA for data transfer

8.3 Functional Description

8.3.1 SDIO Slave Block Diagram
The functional block diagram of the SDIO slave module is shown in Figure 22.

Figure 22: SDIO Slave Block Diagram

The Host System represents any SDIO specification V2.0-compatible host device. The Host System interacts
with the ESP32 (configured as the SDIO slave) via the standard SDIO bus implementation.

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The SDIO Device Interface block enables effective communication with the external Host by directly providing
SDIO interface registers and enabling DMA operation for high-speed data transfer over the Advanced
High-performance Bus (AHB) without engaging the CPU.

8.3.2 Sending and Receiving Data on SDIO Bus

Data is transmitted between Host and Slave through the SDIO bus I/O Function1. After the Host enables the I/O
Function1 in the Slave, according to the SDIO protocol, data transmission will begin.

ESP32 segregates data into packets sent to/from the Host. To achieve high bus utilization and data transfer
rates, we recommend the single block transmission mode. For detailed information on this mode, please refer to
the SDIO V2.0 protocol specification. When Host and Slave exchange data as blocks on the SDIO bus, the Slave
automatically pads data-when sending data out-and automatically strips padding data from the incoming data
block.

Whether the Slave pads or discards the data depends on the data address on the SDIO bus. When the data
address is equal to, or greater than, 0x1F800, the Slave will start padding or discarding data. Therefore, the
starting data address should be 0x1F800 - Packet_length, where Packet_length is measured in bytes. Data flow
on the SDIO bus is shown in Figure 23.

Figure 23: SDIO Bus Packet Transmission

The standard IO_RW_EXTENDED (CMD53) command is used to initiate a packet transfer of an arbitrary length.
The content of the CMD53 command used in data transmission is as illustrated in Figure 24 below. For detailed
information on CMD53, please refer to the SDIO protocol specifications.

Figure 24: CMD53 Content

8.3.3 Register Access

For effective interaction between Host and Slave, the Host can access certain registers in the Slave via the SDIO
bus I/O Function1. These registers are in continuous address fields from SLC0HOST_TOKEN_RDATA to
SLCHOST_INF_ST. The Host device can access these registers by simply setting the register addresses of
CMD52 or CMD53 to the low 10 bits of the corresponding register address. The Host can access several
consecutive registers at one go with CMD53, thus achieving a higher effective transfer rate.

There are 54 bytes of field between SLCHOST_CONF_W0_REG and SLCHOST_CONF_W15_REG. Host and
Slave can access and change these fields, thus facilitating the information interaction between Host and

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8. SDIO Slave

Slave.

8.3.4 DMA
The SDIO Slave module uses dedicated DMA to access data residing in the RAM. As shown in Figure 22, the
RAM is accessed over the AHB. DMA accesses RAM through a linked-list descriptor. Every linked list is
composed of three words, as shown in Figure 25.

Figure 25: SDIO Slave DMA Linked List Structure

• Owner: The allowed operator of the buffer that corresponds to the current linked list. 0: CPU is the allowed
operator; 1: DMA is the allowed operator.

• Eof: End-of-file marker, indicating that this linked-list element is the last element of the data packet.

• Length: The number of valid bytes in the buffer, i.e., the number of bytes that should be accessed from the
buffer for reading/writing.

• Size: The maximum number of available buffers.

• Buffer Address Pointer: The address of the data buffer as seen by the CPU (according to the RAM address
space).

• Next Descriptor Address: The address of the next linked-list element in the CPU RAM address space. If the
current linked list is the last one, the Eof bit should be 1, and the last descriptor address should be 0.

The Slave’s linked-list chain is shown in Figure 26:

Figure 26: SDIO Slave Linked List

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8.3.5 Packet-Sending/-Receiving Procedure

The SDIO Host and Slave devices need to follow specific data transfer procedures to successfully exchange data
over the SDIO interface.

8.3.5.1 Sending Packets to SDIO Host

The transmission of packets from Slave to Host is initiated by the Slave. The Host will be notified with an interrupt
(for detailed information on interrupts, please refer to SDIO protocol). After the Host reads the relevant
information from the Slave, it will initiate an SDIO bus transaction accordingly. The whole procedure is illustrated
in Figure 27.

Figure 27: Packet Sending Procedure (Initiated by Slave)

When the Host is interrupted, it reads relevant information from the Slave by visiting registers SLC0HOST_INT
and SLCHOST_PKT_LEN.

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• SLC0HOST_INT: Interrupt status register. If the value of SLC0_RX_NEW_PACKET_INT_ST is 1, this

indicates that the Slave has a packet to send.

• SLCHOST_PKT_LEN: Packet length accumulator register. The current value minus the value of last time
equals the packet length sent this time.

In order to start DMA, the CPU needs to write the low 20 bits of the address of the first linked-list element to the
SLC0_RXLINK_ADDR bit of SLC0RX_LINK, then set the SLC0_RXLINK_START bit of SLC0RX_LINK. The DMA
will automatically complete the data transfer. Upon completion of the operation, DMA will interrupt the CPU so
that the buffer space can be freed or reused.

8.3.5.2 Receiving Packets from SDIO Host

Transmission of packets from Host to Slave is initiated by the Host. The Slave receives data via DMA and stores it
in RAM. After transmission is completed, the CPU will be interrupted to process the data. The whole procedure is
demonstrated in Figure 28.

Figure 28: Packet Receiving Procedure (Initiated by Host)

The Host obtains the number of available receiving buffers from the Slave by accessing register
SLC0HOST_TOKEN_RDATA. The Slave CPU should update this value after the receiving DMA linked list is
prepared.

HOSTREG_SLC0_TOKEN1 in SLC0HOST_TOKEN_RDATA stores the accumulated number of available

buffers.

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The Host can figure out the available buffer space, using HOSTREG_SLC0_TOKEN1 minus the number of
buffers already used.

If the buffers are not enough, the Host needs to constantly poll the register until there are enough buffers
available.

To ensure sufficient receiving buffers, the Slave CPU must constantly load buffers on the receiving linked list. The
process is shown in Figure 29.

Figure 29: Loading Receiving Buffer

The CPU first needs to append new buffer segments at the end of the linked list that is being used by DMA and is
available for receiving data.

The CPU then needs to notify the DMA that the linked list has been modified. This can be done by setting bit
SLC0_TXLINK_RESTART of the SLC0TX_LINK register. Please note that when the CPU initiates DMA to receive
packets for the first time, SLC0_TXLINK_RESTART should be set to 1.

Lastly, the CPU refreshes any available buffer information by writing to the SLC0TOKEN1 register.

8.3.6 SDIO Bus Timing

The SDIO bus operates at a very high speed and the PCB trace length usually affects signal integrity by
introducing latency. To ensure that the timing characteristics conform to the desired bus timing, the SDIO Slave
module supports configuration of input sampling clock edge and output driving clock edge.

When the incoming data changes near the rising edge of the clock, the Slave will perform sampling on the falling
edge of the clock, or vice versa, as Figure 30 shows.

Figure 30: Sampling Timing Diagram

Sampling edges are configured via the FRC_POS_SAMP and FRC_NEG_SAMP bitfields in the SLCHOST_CONF
register. Each field is five bits wide, with bits corresponding to the CMD line and four DATA lines (0-3). Setting a

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8. SDIO Slave

bit in FRC_POS_SAMP causes the corresponding line to be sampled for input at the rising clock edge, whereas
setting a bit in FRC_NEG_SAMP causes the corresponding line to be sampled for input at the falling clock
edge.

The Slave can also select the edge at which data output lines are driven to accommodate for any latency caused
by the physical signal path, as shown in Figure 31.

Figure 31: Output Timing Diagram

Driving edges are configured via the FRC_SDIO20 and FRC_SDIO11 bitfields in the SLCHOST_CONF register.
Each field is five bits wide, with bits corresponding to the CMD line and four DATA lines (0-3). Setting a bit in
FRC_SDIO20 causes the corresponding line to output at the rising clock edge, whereas setting a bit in
FRC_SDIO11 causes the corresponding line to output at the falling clock edge.

8.3.7 Interrupt
Host and Slave can interrupt each other via the interrupt vector. Both Host and Slave have eight interrupt
vectors. The interrupt is enabled by configuring the interrupt vector register (setting the enable bit to 1). The
interrupt vector registers can clear themselves automatically, which means one interrupt at a time and no other
configuration is required.

8.3.7.1 Host Interrupt

• SLC0HOST_SLC0_RX_NEW_PACKET_INT Slave has a packet to send.

• SLC0HOST_SLC0_TX_OVF_INT Slave receiving buffer overflow interrupt.

• SLC0HOST_SLC0_RX_UDF_INT Slave sending buffer underflow interrupt.

• SLC0HOST_SLC0_TOHOST_BITn_INT (n: 0 ~ 7) Slave interrupts Host.

8.3.7.2 Slave Interrupt

• SLC0INT_SLC0_RX_DSCR_ERR_INT Slave sending descriptor error.

• SLC0INT_SLC0_TX_DSCR_ERR_INT Slave receiving descriptor error.

• SLC0INT_SLC0_RX_EOF_INT Slave sending operation is finished.

• SLC0INT_SLC0_RX_DONE_INT A single buffer is sent by Slave.

• SLC0INT_SLC0_TX_SUC_EOF_INT Slave receiving operation is finished.

• SLC0INT_SLC0_TX_DONE_INT A single buffer is finished during receiving operation.

• SLC0INT_SLC0_TX_OVF_INT Slave receiving buffer overflow interrupt.

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• SLC0INT_SLC0_RX_UDF_INT Slave sending buffer underflow interrupt.

• SLC0INT_SLC0_TX_START_INT Slave receiving interrupt initialization.

• SLC0INT_SLC0_RX_START_INT Slave sending interrupt initialization.

• SLC0INT_SLC_FRHOST_BITn_INT (n: 0 ~ 7) Host interrupts Slave.

8.4 Register Summary

Name Description Address Access

SDIO DMA (SLC) configuration registers
SLCCONF0_REG SLCCONF0_SLC configuration 0x3FF58000 R/W
SLC0INT_RAW_REG Raw interrupt status 0x3FF58004 RO
SLC0INT_ST_REG Interrupt status 0x3FF58008 RO
SLC0INT_ENA_REG Interrupt enable 0x3FF5800C R/W
SLC0INT_CLR_REG Interrupt clear 0x3FF58010 WO
SLC0RX_LINK_REG Transmitting linked list configuration 0x3FF5803C R/W
SLC0TX_LINK_REG Receiving linked list configuration 0x3FF58040 R/W
SLCINTVEC_TOHOST_REG Interrupt sector for Slave to interrupt Host 0x3FF5804C WO
SLC0TOKEN1_REG Number of receiving buffer 0x3FF58054 WO
SLCCONF1_REG Control register 0x3FF58060 R/W
SLC_RX_DSCR_CONF_REG DMA transmission configuration 0x3FF58098 R/W
SLC0_LEN_CONF_REG Length control of the transmitting packets 0x3FF580E4 R/W
SLC0_LENGTH_REG Length of the transmitting packets 0x3FF580E8 R/W

Name Description Address Access

SDIO SLC Host registers
SLC0HOST_INT_RAW_REG Raw interrupt 0x3FF55000 RO
The accumulated number of Slave’s receiving
SLC0HOST_TOKEN_RDATA 0x3FF55044 RO
buffers
SLC0HOST_INT_ST_REG Masked interrupt status 0x3FF55058 RO
SLCHOST_PKT_LEN_REG Length of the transmitting packets 0x3FF55060 RO
SLCHOST_CONF_W0_REG Host and Slave communication register0 0x3FF5506C R/W
SLCHOST_CONF_W1_REG Host and Slave communication register1 0x3FF55070 R/W
SLCHOST_CONF_W2_REG Host and Slave communication register2 0x3FF55074 R/W
SLCHOST_CONF_W3_REG Host and Slave communication register3 0x3FF55078 R/W
SLCHOST_CONF_W4_REG Host and Slave communication register4 0x3FF5507C R/W
SLCHOST_CONF_W6_REG Host and Slave communication register6 0x3FF55088 R/W
SLCHOST_CONF_W7_REG Interrupt vector for Host to interrupt Slave 0x3FF5508C WO
SLCHOST_CONF_W8_REG Host and Slave communication register8 0x3FF5509C R/W
SLCHOST_CONF_W9_REG Host and Slave communication register9 0x3FF550A0 R/W
SLCHOST_CONF_W10_REG Host and Slave communication register10 0x3FF550A4 R/W
SLCHOST_CONF_W11_REG Host and Slave communication register11 0x3FF550A8 R/W
SLCHOST_CONF_W12_REG Host and Slave communication register12 0x3FF550AC R/W

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8. SDIO Slave

SLCHOST_CONF_W13_REG Host and Slave communication register13 0x3FF550B0 R/W

SLCHOST_CONF_W14_REG Host and Slave communication register14 0x3FF550B4 R/W
SLCHOST_CONF_W15_REG Host and Slave communication register15 0x3FF550B8 R/W
SLC0HOST_INT_CLR_REG Interrupt clear 0x3FF550D4 WO
SLC0HOST_FUNC1_INT_ENA_REG Interrupt enable 0x3FF550DC R/W
SLCHOST_CONF_REG Edge configuration 0x3FF551F0 R/W

Name Description Address Access

SDIO HINF registers
HINF_CFG_DATA1_REG SDIO specification configuration 0x3FF4B004 R/W

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8. SDIO Slave

8.5 SLC Registers

The first block of SDIO control registers starts at 0x3FF5_8000.

Register 8.1: SLCCONF0_REG (0x0)

P_ S K
LR

O TE AC
_C

TE T
ST
LO P_ B
X_ O WR
TO
AU

_T LO _
SL ed) LC0 RX_ UTO
N_

X_ T
T
_T RS
RS
KE

S _ A
se F0_ LC0 RX_

C0 X_
TO

SL _R
0_

N S _
O 0_ C0

0_ C0
LC

CC NF SL

NF SL
_S

SL CO F0_

O 0_
0
NF

CC NF
d)

C N
ed
ve

SL CO

SL CO
rv

rv
CC
er

se

C
s

SL

SL
(re

(re

(re
31 15 14 13 7 6 5 4 3 2 1 0

0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 1 1 0 0 0 0 Reset

SLCCONF0_SLC0_TOKEN_AUTO_CLR Please initialize to 0. Do not modify it. (R/W)

SLCCONF0_SLC0_RX_AUTO_WRBACK Allows changing the owner bit of the transmitting buffer’s

linked list when transmitting data. (R/W)

SLCCONF0_SLC0_RX_LOOP_TEST Loop around when the slave buffer finishes sending packets.
When set to 1, hardware will not change the owner bit in the linked list. (R/W)

SLCCONF0_SLC0_TX_LOOP_TEST Loop around when the slave buffer finishes receiving packets.
When set to 1, hardware will not change the owner bit in the linked list. (R/W)

SLCCONF0_SLC0_RX_RST Set this bit to reset the transmitting FSM. (R/W)

SLCCONF0_SLC0_TX_RST Set this bit to reset the receiving FSM. (R/W)

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8. SDIO Slave

Register 8.2: SLC0INT_RAW_REG (0x4)

_R W
AW

AW W
NT A

C0 T_ C_ HO T_ 5_ T_R W
IN SL FR S BIT INT AW

C_ H T_ T3_ T_ W
HO T_ 2_ T_ W
ST BIT INT AW
IT NT AW
T_ W
W
_I _R

_R RA

SL 0IN _SL _FR OS BIT _IN RA

SL FR OS BI IN RA
FR OS BIT IN RA

IN RA
RA
SL 0IN _SL _FR OS BIT _IN W
SL 0IN _SL _FR OS BIT T_ W
NE OF_ RAW

R
_ B 1_I _R
RR INT

NT T_

C T C H T_ 7 RA
C T C H T_ IN A
C T C H A IN W
X_ C IN W

C T C H T_ 6 T_

T_ C_ H T_ 4_ _

0_ _
C T C X AR T_ W

SL 0IN _SL _FR OS RT_ T_R

_I IN

SL 0IN _SL _FR _ST T_ RA

_T SU _ A
_E R_

SL 0IN _SL 0_R ST _IN RA

DO _E T_
R
CR ER

C T C X_ F T_
T
se _SL 0_T _DO _IN
DS R_

SL IN SL _T UD IN
E

C0 T_ C0 X_ F_
N
X_ C

T C X F
IN L R O
SL 0IN ) 0_T _DS

SL IN SL _R V O
E
C0 T_ C0 X_

C0 T_ C0 X_
C d C X

X
SL rve _SL 0_R

SL IN SL _R

SL IN L T
_

_
C0 _ 0

C0 T_ C0
se T C

C
(re 0IN _SL

SL IN SL

SL IN SL
S

S
C0 T_

C0 T_
)

C0 )
ed

ed

d
C T

e
SL 0IN

SL IN
rv

rv
er
se

C
s

SL

SL
(re

(re

(re
31 27 26 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

0x00 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Reset

SLC0INT_SLC0_RX_DSCR_ERR_INT_RAW The raw interrupt bit for Slave sending descriptor error
(RO)

SLC0INT_SLC0_TX_DSCR_ERR_INT_RAW The raw interrupt bit for Slave receiving descriptor error.
(RO)

SLC0INT_SLC0_RX_EOF_INT_RAW The interrupt mark bit when Slave sending operation is finished.
(RO)

SLC0INT_SLC0_RX_DONE_INT_RAW The raw interrupt bit to mark single buffer as sent by Slave.
(RO)

SLC0INT_SLC0_TX_SUC_EOF_INT_RAW The raw interrupt bit to mark Slave receiving operation as

finished. (RO)

SLC0INT_SLC0_TX_DONE_INT_RAW The raw interrupt bit to mark a single buffer as finished during
Slave receiving operation. (RO)

SLC0INT_SLC0_TX_OVF_INT_RAW The raw interrupt bit to mark Slave receiving buffer overflow.
(RO)

SLC0INT_SLC0_RX_UDF_INT_RAW The raw interrupt bit for Slave sending buffer underflow. (RO)

SLC0INT_SLC0_TX_START_INT_RAW The raw interrupt bit for registering Slave receiving initializa-
tion interrupt. (RO)

SLC0INT_SLC0_RX_START_INT_RAW The raw interrupt bit to mark Slave sending initialization in-
terrupt. (RO)

SLC0INT_SLC_FRHOST_BIT7_INT_RAW The interrupt mark bit 7 for Host to interrupt Slave. (RO)

SLC0INT_SLC_FRHOST_BIT6_INT_RAW The interrupt mark bit 6 for Host to interrupt Slave. (RO)

SLC0INT_SLC_FRHOST_BIT5_INT_RAW The interrupt mark bit 5 for Host to interrupt Slave. (RO)

SLC0INT_SLC_FRHOST_BIT4_INT_RAW The interrupt mark bit 4 for Host to interrupt Slave. (RO)

SLC0INT_SLC_FRHOST_BIT3_INT_RAW The interrupt mark bit 3 for Host to interrupt Slave. (RO)

SLC0INT_SLC_FRHOST_BIT2_INT_RAW The interrupt mark bit 2 for Host to interrupt Slave. (RO)

SLC0INT_SLC_FRHOST_BIT1_INT_RAW The interrupt mark bit 1 for Host to interrupt Slave. (RO)

SLC0INT_SLC_FRHOST_BIT0_INT_RAW The interrupt mark bit 0 for Host to interrupt Slave. (RO)
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8. SDIO Slave

Register 8.3: SLC0INT_ST_REG (0x8)

NT T
T
_I _S
_S

_S ST

SL 0IN _SL _FR OS BIT _IN ST

IN SL FR S BIT INT T
SL FR OS BI IN ST
FR OS BIT IN ST
ST BIT INT T
IT NT T
IN ST
ST
C0 T_ C_ HO T_ 5_ T_S

S
_B 1_I _S
RR INT

NT T_

C T C H T_ 7 ST
C T C H T_ IN T

C T C H T_ 6 T_

T_ C_ H T_ 4_ _
C_ H T_ T3_ T_
HO T_ 2_ T_

0_ _
T_
NE OF_ ST

SL IN SL FR S T_ T_S
_I IN
_E R_

SL 0IN _SL _FR _ST T_ ST

SL ed) 0_T SU E_ ST

SL 0IN _SL _FR OS BIT _IN

SL 0IN _SL _FR OS BIT T_
SL 0IN _SL 0_R ST _IN ST
DO _E T_
CR ER

C T C X AR T_
_

C0 T_ C_ HO AR IN
C T C X_ F T_
X_ C IN
T
se _SL 0_T _DO _IN
DS R_

SL IN SL _T UD IN
C0 T_ C0 X_ F_
N
X_ C

T C X F
IN L R O
SL 0IN ) 0_T _DS

SL IN SL _R V O
E
C0 T_ C0 X_

C0 T_ C0 X_
C d C X

X
SL rve _SL 0_R

SL IN SL _R

SL IN L T
_

_
C0 _ 0

C0 T_ C0
se T C

C
(re 0IN _SL

SL IN SL

SL IN SL
S

S
C0 T_

C0 T_
)

d)
ed

C T

T
ve

SL 0IN

SL IN
rv

rv
er

C0
se

C
s

SL
(re

(re

(re
31 27 26 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

0x00 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Reset

SLC0INT_SLC0_RX_DSCR_ERR_INT_ST The interrupt status bit for Slave sending descriptor error.
(RO)

SLC0INT_SLC0_TX_DSCR_ERR_INT_ST The interrupt status bit for Slave receiving descriptor error.
(RO)

SLC0INT_SLC0_RX_EOF_INT_ST The interrupt status bit for finished Slave sending operation. (RO)

SLC0INT_SLC0_RX_DONE_INT_ST The interrupt status bit for finished Slave sending operation.
(RO)

SLC0INT_SLC0_TX_SUC_EOF_INT_ST The interrupt status bit for marking Slave receiving opera-
tion as finished. (RO)

SLC0INT_SLC0_TX_DONE_INT_ST The interrupt status bit for marking a single buffer as finished
during the receiving operation. (RO)

SLC0INT_SLC0_TX_OVF_INT_ST The interrupt status bit for Slave receiving overflow interrupt. (RO)

SLC0INT_SLC0_RX_UDF_INT_ST The interrupt status bit for Slave sending buffer underflow. (RO)

SLC0INT_SLC0_TX_START_INT_ST The interrupt status bit for Slave receiving interrupt initialization.
(RO)

SLC0INT_SLC0_RX_START_INT_ST The interrupt status bit for Slave sending interrupt initialization.
(RO)

SLC0INT_SLC_FRHOST_BIT7_INT_ST The interrupt status bit 7 for Host to interrupt Slave. (RO)

SLC0INT_SLC_FRHOST_BIT6_INT_ST The interrupt status bit 6 for Host to interrupt Slave. (RO)

SLC0INT_SLC_FRHOST_BIT5_INT_ST The interrupt status bit 5 for Host to interrupt Slave. (RO)

SLC0INT_SLC_FRHOST_BIT4_INT_ST The interrupt status bit 4 for Host to interrupt Slave. (RO)

SLC0INT_SLC_FRHOST_BIT3_INT_ST The interrupt status bit 3 for Host to interrupt Slave. (RO)

SLC0INT_SLC_FRHOST_BIT2_INT_ST The interrupt status bit 2 for Host to interrupt Slave. (RO)

SLC0INT_SLC_FRHOST_BIT1_INT_ST The interrupt status bit 1 for Host to interrupt Slave. (RO)

SLC0INT_SLC_FRHOST_BIT0_INT_ST The interrupt status bit 0 for Host to interrupt Slave. (RO)

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8. SDIO Slave

Register 8.4: SLC0INT_ENA_REG (0xC)

_E A
NA
NT N

NA A

C0 T_ C_ HO T_ 5_ T_E A
IN SL FR S BIT INT NA

C_ H T_ T3_ T_ A
HO T_ 2_ T_ A
ST BIT INT NA
IT NT NA
T_ A
A
_I _E

_E EN

SL 0IN _SL _FR OS BIT _IN EN

SL FR OS BI IN EN
FR OS BIT IN EN

IN EN
EN
SL 0IN _SL _FR OS BIT _IN A
SL 0IN _SL _FR OS BIT T_ A
NE OF_ ENA

E
_ B 1_I _E
RR INT

NT T_

C T C H T_ 7 EN
C T C H T_ IN N

C T C H T_ 6 T_

T_ C_ H T_ 4_ _

0_ _
C T C H A IN A
X_ C IN A

C T C X AR T_ A

SL 0IN _SL _FR OS RT_ T_E

_I IN

SL 0IN _SL _FR _ST T_ EN

_T SU _ N
_E R_

SL 0IN _SL 0_R ST _IN EN

DO _E T_
E
CR ER

C T C X_ F T_
T
se _SL 0_T _DO _IN
DS R_

SL IN SL _T UD IN
E

C0 T_ C0 X_ F_
N
X_ C

T C X F
IN L R O
SL 0IN ) 0_T _DS

SL IN SL _R V O
E
C0 T_ C0 X_

C0 T_ C0 X_
C d C X

X
SL rve _SL 0_R

SL IN SL _R

SL IN L T
_

_
C0 _ 0

C0 T_ C0
se T C

C
(re 0IN _SL

SL IN SL

SL IN SL
S

S
C0 T_

C0 T_
)

d)

C0 )
ed

d
C T

T
ve

e
SL 0IN

SL IN
rv

rv
er
se

C
s

SL

SL
(re

(re

(re
31 27 26 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

0x00 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Reset

SLC0INT_SLC0_RX_DSCR_ERR_INT_ENA The interrupt enable bit for Slave sending linked list de-
scriptor error. (R/W)

SLC0INT_SLC0_TX_DSCR_ERR_INT_ENA The interrupt enable bit for Slave receiving linked list de-
scriptor error. (R/W)

SLC0INT_SLC0_RX_EOF_INT_ENA The interrupt enable bit for Slave sending operation completion.
(R/W)

SLC0INT_SLC0_RX_DONE_INT_ENA The interrupt enable bit for single buffer’s sent interrupt, in
Slave sending mode. (R/W)

SLC0INT_SLC0_TX_SUC_EOF_INT_ENA The interrupt enable bit for Slave receiving operation com-
pletion. (R/W)

SLC0INT_SLC0_TX_DONE_INT_ENA The interrupt enable bit for single buffer’s full event, in Slave
receiving mode. (R/W)

SLC0INT_SLC0_TX_OVF_INT_ENA The interrupt enable bit for Slave receiving buffer overflow. (R/W)

SLC0INT_SLC0_RX_UDF_INT_ENA The interrupt enable bit for Slave sending buffer underflow.
(R/W)

SLC0INT_SLC0_TX_START_INT_ENA The interrupt enable bit for Slave receiving operation initial-
ization. (R/W)

SLC0INT_SLC0_RX_START_INT_ENA The interrupt enable bit for Slave sending operation initializa-
tion. (R/W)

SLC0INT_SLC_FRHOST_BIT7_INT_ENA The interrupt enable bit 7 for Host to interrupt Slave. (R/W)

SLC0INT_SLC_FRHOST_BIT6_INT_ENA The interrupt enable bit 6 for Host to interrupt Slave. (R/W)

SLC0INT_SLC_FRHOST_BIT5_INT_ENA The interrupt enable bit 5 for Host to interrupt Slave. (R/W)

SLC0INT_SLC_FRHOST_BIT4_INT_ENA The interrupt enable bit 4 for Host to interrupt Slave. (R/W)

SLC0INT_SLC_FRHOST_BIT3_INT_ENA The interrupt enable bit 3 for Host to interrupt Slave. (R/W)

SLC0INT_SLC_FRHOST_BIT2_INT_ENA The interrupt enable bit 2 for Host to interrupt Slave. (R/W)

SLC0INT_SLC_FRHOST_BIT1_INT_ENA The interrupt enable bit 1 for Host to interrupt Slave. (R/W)

SLC0INT_SLC_FRHOST_BIT0_INT_ENA The interrupt enable bit 0 for Host to interrupt Slave. (R/W)
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8. SDIO Slave

Register 8.5: SLC0INT_CLR_REG (0x10)

_C R
LR
NT L

LR R

C0 T_ C_ HO T_ 5_ T_C R
IN SL FR S BIT INT LR

C_ H T_ T3_ T_ R
HO T_ 2_ T_ R
ST BIT INT LR
IT NT LR
T_ R
R
_I _C

_C CL

SL 0IN _SL _FR OS BIT _IN CL

SL FR OS BI IN CL
FR OS BIT IN CL

IN CL
CL
SL 0IN _SL _FR OS BIT _IN R
SL IN SL FR S BIT T_ R

C
_ B 1_I _C
NE OF_ CLR
RR INT

NT T_

C T C H T_ 7 CL
C0 T_ C_ HO T_ IN L

C T C H T_ 6 T_

T_ C_ H T_ 4_ _

0_ _
C T C H A IN R
X_ C IN R

C T C X AR T_ R

SL 0IN _SL _FR OS RT_ T_C

_I IN

SL 0IN _SL _FR _ST T_ CL

_E R_

_T SU _ L

SL 0IN _SL 0_R ST _IN CL

DO _E T_
C
CR ER

C T C X_ F T_
T
se _SL 0_T _DO _IN
DS R_

SL IN SL _T UD IN
E

C0 T_ C0 X_ F_
N
X_ C

T C X F
IN L R O
SL 0IN ) 0_T _DS

SL IN SL _R V O
E
C0 T_ C0 X_

C0 T_ C0 X_
C d C X

X
SL rve _SL 0_R

SL IN SL _R

SL IN L T
_

_
C0 _ 0

C0 T_ C0
se T C

C
(re 0IN _SL

SL IN SL

SL IN SL
S

S
C0 T_

C0 T_
d)

C0 )
ed

d
C T

T
ve

e
SL 0IN

SL IN
rv

rv
er

se

C
s

SL

SL
(re

(re

(re
31 27 26 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

0x00 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Reset

SLC0INT_SLC0_RX_DSCR_ERR_INT_CLR Interrupt clear bit for Slave sending linked list descriptor
error. (WO)

SLC0INT_SLC0_TX_DSCR_ERR_INT_CLR Interrupt clear bit for Slave receiving linked list descriptor
error. (WO)

SLC0INT_SLC0_RX_EOF_INT_CLR Interrupt clear bit for Slave sending operation completion. (WO)

SLC0INT_SLC0_RX_DONE_INT_CLR Interrupt clear bit for single buffer’s sent interrupt, in Slave
sending mode. (WO)

SLC0INT_SLC0_TX_SUC_EOF_INT_CLR Interrupt clear bit for Slave receiving operation comple-

tion. (WO)

SLC0INT_SLC0_TX_DONE_INT_CLR Interrupt clear bit for single buffer’s full event, in Slave receiving
mode. (WO)

SLC0INT_SLC0_TX_OVF_INT_CLR Set this bit to clear the Slave receiving overflow interrupt. (WO)

SLC0INT_SLC0_RX_UDF_INT_CLR Set this bit to clear the Slave sending underflow interrupt. (WO)

SLC0INT_SLC0_TX_START_INT_CLR Set this bit to clear the interrupt for Slave receiving operation
initialization. (WO)

SLC0INT_SLC0_RX_START_INT_CLR Set this bit to clear the interrupt for Slave sending operation
initialization. (WO)

SLC0INT_SLC_FRHOST_BIT7_INT_CLR Set this bit to clear the SLC0INT_SLC_FRHOST_BIT7_INT

interrupt. (WO)

SLC0INT_SLC_FRHOST_BIT6_INT_CLR Set this bit to clear the SLC0INT_SLC_FRHOST_BIT6_INT

interrupt. (WO)

SLC0INT_SLC_FRHOST_BIT5_INT_CLR Set this bit to clear the SLC0INT_SLC_FRHOST_BIT5_INT

interrupt. (WO)

SLC0INT_SLC_FRHOST_BIT4_INT_CLR Set this bit to clear the SLC0INT_SLC_FRHOST_BIT4_INT

interrupt. (WO)

Continued on the next page...

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8. SDIO Slave

Register 8.5: SLC0INT_CLR_REG (0x10)

Continued from the previous page...

SLC0INT_SLC_FRHOST_BIT3_INT_CLR Set this bit to clear SLC0INT_SLC_FRHOST_BIT3_INT in-

terrupt. (WO)

SLC0INT_SLC_FRHOST_BIT2_INT_CLR Set this bit to clear SLC0INT_SLC_FRHOST_BIT2_INT in-

terrupt. (WO)

SLC0INT_SLC_FRHOST_BIT1_INT_CLR Set this bit to clear SLC0INT_SLC_FRHOST_BIT1_INT in-

terrupt. (WO)

SLC0INT_SLC_FRHOST_BIT0_INT_CLR Set this bit to clear SLC0INT_SLC_FRHOST_BIT0_INT in-

terrupt. (WO)

Register 8.6: SLC0RX_LINK_REG (0x3C)

_S RT T
NK TA R
LI _S TA

R
P

DD
TO
RX NK ES
0_ LI _R

_A
LC RX NK

NK
_S 0_ XLI

LI
RX
RX LC _R

0_
C0 X_S C0

LC
SL 0R SL

_S
SL 0R )

)
C X_
C d

ed

RX
SL rve

rv

C0
se

se

SL
(re

(re

31 30 29 28 27 20 19 0

0 0 0 0 0 0 0 0 0 0 0 0 0x000000 Reset

SLC0RX_SLC0_RXLINK_RESTART Set this bit to restart and continue the linked list operation for
sending packets. (R/W)

SLC0RX_SLC0_RXLINK_START Set this bit to start the linked list operation for sending packets.
Sending will start from the address indicated by SLC0_RXLINK_ADDR. (R/W)

SLC0RX_SLC0_RXLINK_STOP Set this bit to stop the linked list operation. (R/W)

SLC0RX_SLC0_RXLINK_ADDR The lowest 20 bits in the initial address of Slave’s sending linked list.
(R/W)

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8. SDIO Slave

Register 8.7: SLC0TX_LINK_REG (0x40)

_S RT T
NK TA R
LI _S TA

R
P

DD
TO
TX K ES
0_ LIN _R

_A
LC TX NK

NK
_S 0_ LI

LI
TX LC _TX

TX
0_
C0 _S 0
SL 0TX SLC

SLC
SL 0TX )

)
C _

X_
C d

ed
SL rve

T
rv

C0
se

se

SL
(re

(re
31 30 29 28 27 20 19 0

0 0 0 0 0 0 0 0 0 0 0 0 0x000000 Reset

SLC0TX_SLC0_TXLINK_RESTART Set this bit to restart and continue the linked list operation for
receiving packets. (R/W)

SLC0TX_SLC0_TXLINK_START Set this bit to start the linked list operation for receiving packets.
Receiving will start from the address indicated by SLC0_TXLINK_ADDR. (R/W)

SLC0TX_SLC0_TXLINK_STOP Set this bit to stop the linked list operation for receiving packets.
(R/W)

SLC0TX_SLC0_TXLINK_ADDR The lowest 20 bits in the initial address of Slave’s receiving linked
list. (R/W)

Register 8.8: SLCINTVEC_TOHOST_REG (0x4C)

EC
TV
N
_I
ST
HO
O
_T
C0
SL
C_
VE
)

d)
ed

ed

NT
rv

rv

rv
se

se

se

CI
SL
(re

(re

(re

31 24 23 16 15 8 7 0

0x000 0 0 0 0 0 0 0 0 0x000 0x000 Reset

SLCINTVEC_SLC0_TOHOST_INTVEC The interrupt vector for Slave to interrupt Host. (WO)

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8. SDIO Slave

Register 8.9: SLC0TOKEN1_REG (0x54)

RE
O

TA
M

DA
C_
IN

W
_

_
N1

N1

N1
KE

KE

KE
TO

TO

TO
0_

0_

0_
LC

LC

LC
_S

_S

_S
N1

rv N1

N1
KE

KE
(re OK
)

C0 d)

)
ed

ed
TO

TO
SL rve
T
rv

C0

C0
se

se

se
SL

SL
(re

(re
31 28 27 16 15 14 13 12 11 0

0x00 0x0000 0 0 0 0 0x0000 Reset

SLC0TOKEN1_SLC0_TOKEN1 The accumulated number of buffers for receiving packets. (RO)

SLC0TOKEN1_SLC0_TOKEN1_INC_MORE Set this bit to add the value of

SLC0TOKEN1_SLC0_TOKEN1_WDATA to that of SLC0TOKEN1_SLC0_TOKEN1. (WO)

SLC0TOKEN1_SLC0_TOKEN1_WDATA The number of available receiving buffers. (WO)

Register 8.10: SLCCONF1_REG (0x60)

LR
_A CH N
O N
EN IT _E

_C
UT _E
_L ST CH
C0 X_ TIT
SL _T S
1_ C0 X_
NF SL _R
O 1_ C0
CC NF SL
SL O 1_
CC NF
)

)
ed

ed
ve

SL CO
rv

rv
er
se

se

C
s

SL
(re

(re

(re

31 23 22 16 15 7 6 5 4

0x000 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 Reset

SLCCONF1_SLC0_RX_STITCH_EN Please initialize to 0. Do not modify it. (R/W)

SLCCONF1_SLC0_TX_STITCH_EN Please initialize to 0. Do not modify it. (R/W)

SLCCONF1_SLC0_LEN_AUTO_CLR Please initialize to 0. Do not modify it. (R/W)

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8. SDIO Slave

Register 8.11: SLC_RX_DSCR_CONF_REG (0x98)

E
AC
L
EP
_R
NO
N_
KE
TO
0_
LC
)
ed

S
rv

C_
se

SL
(re
31 1 0

0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Reset

SLC_SLC0_TOKEN_NO_REPLACE Please initialize to 1. Do not modify it. (R/W)

Register 8.12: SLC0_LEN_CONF_REG (0xE4)

RE
O

TA
_M

DA
NC

W
_I

N_
EN
d)

d)

E
ed

_L

_L
ve

e
rv

rv
r

C0

C0
se

se

se
SL

SL
(re

(re

(re

31 29 28 23 22 21 20 19 0

0x0 0 0 0 0 0 0 0 0 0 0x000000 Reset

SLC0_LEN_INC_MORE Set this bit to add the value of SLC0_LEN to that of SLC0_LEN_WDATA.
(WO)

SLC0_LEN_WDATA The packet length sent. (WO)

Register 8.13: SLC0_LENGTH_REG (0xE8)

EN
)
ed

_L
rv

C0
se

SL
(re

31 20 19 0

0x0000 0x000000 Reset

SLC0_LEN Indicates the packet length sent by the Slave. (RO)

8.6 SLC Host Registers

The second block of SDIO control registers starts at 0x3FF5_5000.

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8. SDIO Slave

Register 8.14: SLC0HOST_TOKEN_RDATA (0x44)

N1
KE
O
_T
C0
L
_S
G
d)

)
ed
RE
ve

rv
ST
er

se
s

HO
(re

(re
31 28 27 16 15 0

0x000 0x000 0x000 Reset

HOSTREG_SLC0_TOKEN1 The accumulated number of Slave’s receiving buffers. (RO)

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8. SDIO Slave

Register 8.15: SLC0HOST_INT_RAW_REG (0x50)

W
RA

C0 S LC TO ST IT5 T_ W
ST LC TO ST IT4 T_ W
LC TO ST IT3 T_ W
T W
ST IT1 T_ W

0_ T_R W
IN AW

W
T_

SL 0HO T_S 0_ HO T_B _IN _RA

HO T_S 0_ HO _B _IN RA
_S 0_ HO _B _IN RA
0_ HO _B _IN RA
HO T_B 2_I _RA
_B _IN RA

RA
IN

T_
T_

S LC TO S IT6 T
W
T_ W

SL 0HO T_S 0_ HO T_B _IN

N
KE

RA
_IN RA

S LC TO S IT7
AC

DF T_

TO S IT

IT
SL HO T_S 0_ HO _B
_P

_U _IN
W

C0 S LC TO ST
RX VF
E

SL 0HO T_S 0_ HO
_N

0_ _O

S LC TO
X

LC TX
_R

_S 0_

SL HO T_S 0_
0
LC

ST LC

C0 S LC
_S

HO _S

SL 0HO T_S
ST

T
C0 S

S
)

d)

)
ed

ed

ed
HO

SL 0HO

SL 0HO
ve
rv

rv

rv
r
C0
se

se

se

se
C

C
C

C
C
SL

SL

SL
(re

(re

(re

(re
31 26 25 24 23 22 18 17 16 15 8 7 6 5 4 3 2 1 0

0x00 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Reset

SLC0HOST_SLC0_RX_NEW_PACKET_INT_RAW The raw interrupt status bit for the

SLC0HOST_SLC0_RX_NEW_PACKET_INT interrupt. (RO)

SLC0HOST_SLC0_TX_OVF_INT_RAW The raw interrupt status bit for the

SLC0HOST_SLC0_TX_OVF_INT interrupt. (RO)

SLC0HOST_SLC0_RX_UDF_INT_RAW The raw interrupt status bit for the

SLC0HOST_SLC0_RX_UDF_INT interrupt. (RO)

SLC0HOST_SLC0_TOHOST_BIT7_INT_RAW The raw interrupt status bit for the

SLC0HOST_SLC0_TOHOST_BIT7_INT interrupt. (RO)

SLC0HOST_SLC0_TOHOST_BIT6_INT_RAW The raw interrupt status bit for the

SLC0HOST_SLC0_TOHOST_BIT6_INT interrupt. (RO)

SLC0HOST_SLC0_TOHOST_BIT5_INT_RAW The raw interrupt status bit for the

SLC0HOST_SLC0_TOHOST_BIT5_INT interrupt. (RO)

SLC0HOST_SLC0_TOHOST_BIT4_INT_RAW The raw interrupt status bit for the

SLC0HOST_SLC0_TOHOST_BIT4_INT interrupt. (RO)

SLC0HOST_SLC0_TOHOST_BIT3_INT_RAW The raw interrupt status bit for the

SLC0HOST_SLC0_TOHOST_BIT3_INT interrupt. (RO)

SLC0HOST_SLC0_TOHOST_BIT2_INT_RAW The raw interrupt status bit for the

SLC0HOST_SLC0_TOHOST_BIT2_INT interrupt. (RO)

SLC0HOST_SLC0_TOHOST_BIT1_INT_RAW The raw interrupt status bit for the

SLC0HOST_SLC0_TOHOST_BIT1_INT interrupt. (RO)

SLC0HOST_SLC0_TOHOST_BIT0_INT_RAW The raw interrupt status bit for the

SLC0HOST_SLC0_TOHOST_BIT0_INT interrupt. (RO)

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8. SDIO Slave

Register 8.16: SLC0HOST_INT_ST_REG (0x58)

ST
T_

HO T_ C0 OH ST IT5 T_ T
ST SLC _TO OS _BI _IN ST
LC TO OS BI IN ST
TO OS BI IN ST
ST BIT INT T
IT NT T
IN ST
ST
IN

C0 OS SL _T O _B _IN _S

S
_B 1_I _S
_S 0_ H T_ T4_ T_
0_ H T_ T3_ T_
HO T_ T2_ T_

0_ _
T_
T_

SL 0H T_ LC0 TOH ST IT6 INT

KE

T
_I _ST

C OS S _ O _B _
_S

SL 0H T_ LC0 TOH ST IT7

AC

NT
DF T

C OS S _ O _B
_P

_U _IN
W

SL 0H T_ LC0 TOH ST
RX VF
NE

C OS S _ O
0 _ _O

SL 0H T_ LC0 TOH
X_

LC TX
R
0_

_S 0_

C OS S _
SL 0H T_ LC0
LC

ST LC
_S

C OS S
HO T_

SL 0H T_
ST

C0 OS

C OS
)

SL ed)

)
ed

ed

ed
HO

SL H

SL 0H
rv

rv

rv

rv
C0

C0
se

se

se

se

C
SL

SL
(re

(re

(re

(re
31 26 25 24 23 22 18 17 16 15 8 7 6 5 4 3 2 1 0

0x00 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Reset

SLC0HOST_SLC0_RX_NEW_PACKET_INT_ST The masked interrupt status bit for the

SLC0HOST_SLC0_RX_NEW_PACKET_INT interrupt. (RO)

SLC0HOST_SLC0_TX_OVF_INT_ST The masked interrupt status bit for the

SLC0HOST_SLC0_TX_OVF_INT interrupt. (RO)

SLC0HOST_SLC0_RX_UDF_INT_ST The masked interrupt status bit for the

SLC0HOST_SLC0_RX_UDF_INT interrupt. (RO)

SLC0HOST_SLC0_TOHOST_BIT7_INT_ST The masked interrupt status bit for the

SLC0HOST_SLC0_TOHOST_BIT7_INT interrupt. (RO)

SLC0HOST_SLC0_TOHOST_BIT6_INT_ST The masked interrupt status bit for the

SLC0HOST_SLC0_TOHOST_BIT6_INT interrupt. (RO)

SLC0HOST_SLC0_TOHOST_BIT5_INT_ST The masked interrupt status bit for the

SLC0HOST_SLC0_TOHOST_BIT5_INT interrupt. (RO)

SLC0HOST_SLC0_TOHOST_BIT4_INT_ST The masked interrupt status bit for the

SLC0HOST_SLC0_TOHOST_BIT4_INT interrupt. (RO)

SLC0HOST_SLC0_TOHOST_BIT3_INT_ST The masked interrupt status bit for the

SLC0HOST_SLC0_TOHOST_BIT3_INT interrupt. (RO)

SLC0HOST_SLC0_TOHOST_BIT2_INT_ST The masked interrupt status bit for the

SLC0HOST_SLC0_TOHOST_BIT2_INT interrupt. (RO)

SLC0HOST_SLC0_TOHOST_BIT1_INT_ST The masked interrupt status bit for the

SLC0HOST_SLC0_TOHOST_BIT1_INT interrupt. (RO)

SLC0HOST_SLC0_TOHOST_BIT0_INT_ST The masked interrupt status bit for the

SLC0HOST_SLC0_TOHOST_BIT0_INT interrupt. (RO)

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8. SDIO Slave

Register 8.17: SLCHOST_PKT_LEN_REG (0x60)

K
H EC
N_C

N
LE

LE
0_

_
C0
LC

L
_S

_S
G

G
RE

RE
ST

ST
O

O
_H

_H
ST

ST
O

O
CH

CH
SL

SL
31 20 19 0

0x000 0x000 Reset

SLCHOST_HOSTREG_SLC0_LEN_CHECK Its value is HOSTREG_SLC0_LEN[9:0] plus

HOSTREG_SLC0_LEN[19:10]. (RO)

SLCHOST_HOSTREG_SLC0_LEN The accumulated value of the data length sent by the Slave. The
value gets updated only when the Host reads it.

Register 8.18: SLCHOST_CONF_W0_REG (0x6C)

3

0
NF

NF

NF

NF
O

O
_C

_C

_C

_C
ST

ST

ST

ST
O

O
CH

CH

CH

CH
SL

SL

SL

SL
31 24 23 16 15 8 7 0

0x000 0x000 0x000 0x000 Reset

SLCHOST_CONF3 The information interaction register between Host and Slave. Both Host and Slave
can access it. (R/W)

SLCHOST_CONF2 The information interaction register between Host and Slave. Both Host and Slave
can access it. (R/W)

SLCHOST_CONF1 The information interaction register between Host and Slave. Both Host and Slave
can access it. (R/W)

SLCHOST_CONF0 The information interaction register between Host and Slave. Both Host and Slave
can access it. (R/W)

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8. SDIO Slave

Register 8.19: SLCHOST_CONF_W1_REG (0x70)

4
NF

NF

NF

NF
O

O
_C

_C

_C

_C
ST

ST

ST

ST
O

O
CH

CH

CH

CH
SL

SL

SL

SL
31 24 23 16 15 8 7 0

0x000 0x000 0x000 0x000 Reset

SLCHOST_CONF7 The information interaction register between Host and Slave. Both Host and Slave
can access it. (R/W)

SLCHOST_CONF6 The information interaction register between Host and Slave. Both Host and Slave
can access it. (R/W)

SLCHOST_CONF5 The information interaction register between Host and Slave. Both Host and Slave
can access it. (R/W)

SLCHOST_CONF4 The information interaction register between Host and Slave. Both Host and Slave
can access it. (R/W)

Register 8.20: SLCHOST_CONF_W2_REG (0x74)

11

10

8
NF

NF

NF

NF
O

O
_C

_C

_C

_C
ST

ST

ST

ST
O

O
CH

CH

CH

CH
SL

SL

SL

SL
31 24 23 16 15 8 7 0

0x000 0x000 0x000 0x000 Reset

SLCHOST_CONF11 The information interaction register between Host and Slave. Both Host and
Slave can access it. (R/W)

SLCHOST_CONF10 The information interaction register between Host and Slave. Both Host and
Slave can access it. (R/W)

SLCHOST_CONF9 The information interaction register between Host and Slave. Both Host and Slave
can access it. (R/W)

SLCHOST_CONF8 The information interaction register between Host and Slave. Both Host and Slave
can access it. (R/W)

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8. SDIO Slave

Register 8.21: SLCHOST_CONF_W3_REG (0x78)

15

4
1
NF

NF
O

O
_C

_C
ST

ST
O

O
CH

CH
SL

SL
31 24 23 16

0x000 0x000 Reset

SLCHOST_CONF15 The information interaction register between Host and Slave. Both Host and
Slave can be read from and written to this. (R/W)

SLCHOST_CONF14 The information interaction register between Host and Slave. Both Host and
Slave can be read from and written to this. (R/W)

Register 8.22: SLCHOST_CONF_W4_REG (0x7C)

19

18
NF

NF
O

O
_C

_C
ST

ST
O

O
CH

CH
SL

SL

31 24 23 16

0x000 0x000 Reset

SLCHOST_CONF19 The information interaction register between Host and Slave. Both Host and
Slave can access it. (R/W)

SLCHOST_CONF18 The information interaction register between Host and Slave. Both Host and
Slave can access it. (R/W)

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8. SDIO Slave

Register 8.23: SLCHOST_CONF_W6_REG (0x88)

27

26

24
2
NF

NF

NF

NF
O

O
_C

_C

_C

_C
ST

ST

ST

ST
O

O
CH

CH

CH

CH
SL

SL

SL

SL
31 24 23 16 15 8 7 0

0x000 0x000 0x000 0x000 Reset

SLCHOST_CONF27 The information interaction register between Host and Slave. Both Host and
Slave can access it. (R/W)

SLCHOST_CONF26 The information interaction register between Host and Slave. Both Host and
Slave can access it. (R/W)

SLCHOST_CONF25 The information interaction register between Host and Slave. Both Host and
Slave can access it. (R/W)

SLCHOST_CONF24 The information interaction register between Host and Slave. Both Host and
Slave can access it. (R/W)

Register 8.24: SLCHOST_CONF_W7_REG (0x8C)

31

29
NF

NF
O

O
_C

_C
ST

ST
)

)
ed

ed
O

O
rv

rv
CH

CH
se

se
SL

SL
(re

(re
31 24 23 16 15 8 7 0

0 0 0 0 0 0 0 0 0x000 0 0 0 0 0 0 0 0 0x000 Reset

SLCHOST_CONF31 The interrupt vector used by Host to interrupt Slave. This bit will not be cleared
automatically. (WO)

SLCHOST_CONF29 The interrupt vector used by Host to interrupt Slave. This bit will not be cleared
automatically. (WO)

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8. SDIO Slave

Register 8.25: SLCHOST_CONF_W8_REG (0x9C)

35

34

32
3
NF

NF

NF

NF
O

O
_C

_C

_C

_C
ST

ST

ST

ST
O

O
CH

CH

CH

CH
SL

SL

SL

SL
31 24 23 16 15 8 7 0

0x000 0x000 0x000 0x000 Reset

SLCHOST_CONF35 The information interaction register between Host and Slave. Both Host and
Slave can access it. (R/W)

SLCHOST_CONF34 The information interaction register between Host and Slave. Both Host and
Slave can access it. (R/W)

SLCHOST_CONF33 The information interaction register between Host and Slave. Both Host and
Slave can access it. (R/W)

SLCHOST_CONF32 The information interaction register between Host and Slave. Both Host and
Slave can access it. (R/W)

Register 8.26: SLCHOST_CONF_W9_REG (0xA0)

39

38

37

36
NF

NF

NF

NF
O

O
_C

_C

_C

_C
ST

ST

ST

ST
O

O
CH

CH

CH

CH
SL

SL

SL

SL
31 24 23 16 15 8 7 0

0x000 0x000 0x000 0x000 Reset

SLCHOST_CONF39 The information interaction register between Host and Slave. Both Host and
Slave can access it. (R/W)

SLCHOST_CONF38 The information interaction register between Host and Slave. Both Host and
Slave can access it. (R/W)

SLCHOST_CONF37 The information interaction register between Host and Slave. Both Host and
Slave can access it. (R/W)

SLCHOST_CONF36 The information interaction register between Host and Slave. Both Host and
Slave can access it. (R/W)

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8. SDIO Slave

Register 8.27: SLCHOST_CONF_W10_REG (0xA4)

43

42

40
4
NF

NF

NF

NF
O

O
_C

_C

_C

_C
ST

ST

ST

ST
O

O
CH

CH

CH

CH
SL

SL

SL

SL
31 24 23 16 15 8 7 0

0x000 0x000 0x000 0x000 Reset

SLCHOST_CONF43 The information interaction register between Host and Slave. Both Host and
Slave can access it. (R/W)

SLCHOST_CONF42 The information interaction register between Host and Slave. Both Host and
Slave can access it. (R/W)

SLCHOST_CONF41 The information interaction register between Host and Slave. Both Host and
Slave can access it. (R/W)

SLCHOST_CONF40 The information interaction register between Host and Slave. Both Host and
Slave can access it. (R/W)

Register 8.28: SLCHOST_CONF_W11_REG (0xA8)

47

46

45

44
NF

NF

NF

NF
O

O
_C

_C

_C

_C
ST

ST

ST

ST
O

O
CH

CH

CH

CH
SL

SL

SL

SL
31 24 23 16 15 8 7 0

0x000 0x000 0x000 0x000 Reset

SLCHOST_CONF47 The information interaction register between Host and Slave. Both Host and
Slave can access it. (R/W)

SLCHOST_CONF46 The information interaction register between Host and Slave. Both Host and
Slave can access it. (R/W)

SLCHOST_CONF45 The information interaction register between Host and Slave. Both Host and
Slave can access it. (R/W)

SLCHOST_CONF44 The information interaction register between Host and Slave. Both Host and
Slave can access it. (R/W)

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8. SDIO Slave

Register 8.29: SLCHOST_CONF_W12_REG (0xAC)

51

50

48
4
NF

NF

NF

NF
O

O
_C

_C

_C

_C
ST

ST

ST

ST
O

O
CH

CH

CH

CH
SL

SL

SL

SL
31 24 23 16 15 8 7 0

0x000 0x000 0x000 0x000 Reset

SLCHOST_CONF51 The information interaction register between Host and Slave. Both Host and
Slave can access it. (R/W)

SLCHOST_CONF50 The information interaction register between Host and Slave. Both Host and
Slave can access it. (R/W)

SLCHOST_CONF49 The information interaction register between Host and Slave. Both Host and
Slave can access it. (R/W)

SLCHOST_CONF48 The information interaction register between Host and Slave. Both Host and
Slave can access it. (R/W)

Register 8.30: SLCHOST_CONF_W13_REG (0xB0)

55

54

53

52
NF

NF

NF

NF
O

O
_C

_C

_C

_C
ST

ST

ST

ST
O

O
CH

CH

CH

CH
SL

SL

SL

SL
31 24 23 16 15 8 7 0

0x000 0x000 0x000 0x000 Reset

SLCHOST_CONF55 The information interaction register between Host and Slave. Both Host and
Slave can access it. (R/W)

SLCHOST_CONF54 The information interaction register between Host and Slave. Both Host and
Slave can access it. (R/W)

SLCHOST_CONF53 The information interaction register between Host and Slave. Both Host and
Slave can access it. (R/W)

SLCHOST_CONF52 The information interaction register between Host and Slave. Both Host and
Slave can access it. (R/W)

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8. SDIO Slave

Register 8.31: SLCHOST_CONF_W14_REG (0xB4)

59

58

56
5
NF

NF

NF

NF
O

O
_C

_C

_C

_C
ST

ST

ST

ST
O

O
CH

CH

CH

CH
SL

SL

SL

SL
31 24 23 16 15 8 7 0

0x000 0x000 0x000 0x000 Reset

SLCHOST_CONF59 The information interaction register between Host and Slave. Both Host and
Slave can access it. (R/W)

SLCHOST_CONF58 The information interaction register between Host and Slave. Both Host and
Slave can access it. (R/W)

SLCHOST_CONF57 The information interaction register between Host and Slave. Both Host and
Slave can access it. (R/W)

SLCHOST_CONF56 The information interaction register between Host and Slave. Both Host and
Slave can access it. (R/W)

Register 8.32: SLCHOST_CONF_W15_REG (0xB8)

63

62

61

60
NF

NF

NF

NF
O

O
_C

_C

_C

_C
ST

ST

ST

ST
O

O
CH

CH

CH

CH
SL

SL

SL

SL
31 24 23 16 15 8 7 0

0x000 0x000 0x000 0x000 Reset

SLCHOST_CONF63 The information interaction register between Host and Slave. Both Host and
Slave can access it. (R/W)

SLCHOST_CONF62 The information interaction register between Host and Slave. Both Host and
Slave can access it. (R/W)

SLCHOST_CONF61 The information interaction register between Host and Slave. Both Host and
Slave can access it. (R/W)

SLCHOST_CONF60 The information interaction register between Host and Slave. Both Host and
Slave can access it. (R/W)

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8. SDIO Slave

Register 8.33: SLC0HOST_INT_CLR_REG (0xD4)

R
CL

HO T_ C0 OH T_ T5_ T_C R
ST SLC _TO OS BIT INT LR
LC TO S IT INT LR
TO S IT INT LR
ST BIT INT LR
IT NT LR
T_ R
R
T_

C0 OS SL _T OS BI IN CL

IN L
CL
_S 0_ HO T_B 4_ _C
0_ HO T_B 3_ _C
HO T_ 2_ _C
_B 1_I _C
0_ _C
IN

SL 0H T_ C0 OH ST_ IT6_ T_
T_

R
T_ R

C OS SL _T O B IN
KE

CL
_IN CL

SL 0H T_ C0 OH ST_ IT7_
AC

DF T_

C OS SL _T O B
_P

_U _IN

SL H T_ C0 OH T_
W

RX VF

C0 OS SL _T OS
NE

0_ _O

SL 0H T_ C0 OH
X_

LC TX
_R

C OS SL _T
_S 0_
0

SL 0H T_ C0
LC

ST SLC

C OS SL
_S

HO T_

SL 0H T_
ST

C0 OS

C OS
)

)
ed

ed

ed

ed
O
0H

SL 0H

SL 0H
rv

rv

rv

rv
se

se

se

se
C

C
SL

SL

SL
(re

(re

(re

(re
31 26 25 24 23 22 18 17 16 15 8 7 6 5 4 3 2 1 0

0x00 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Reset

SLC0HOST_SLC0_RX_NEW_PACKET_INT_CLR Set this bit to clear the

SLC0HOST_SLC0_RX_NEW_PACKET_INT interrupt. (WO)

SLC0HOST_SLC0_TX_OVF_INT_CLR Set this bit to clear the SLC0HOST_SLC0_TX_OVF_INT in-

terrupt. (WO)

SLC0HOST_SLC0_RX_UDF_INT_CLR Set this bit to clear the SLC0HOST_SLC0_RX_UDF_INT in-

terrupt. (WO)

SLC0HOST_SLC0_TOHOST_BIT7_INT_CLR Set this bit to clear the

SLC0HOST_SLC0_TOHOST_BIT7_INT interrupt. (WO)

SLC0HOST_SLC0_TOHOST_BIT6_INT_CLR Set this bit to clear the

SLC0HOST_SLC0_TOHOST_BIT6_INT interrupt. (WO)

SLC0HOST_SLC0_TOHOST_BIT5_INT_CLR Set this bit to clear the

SLC0HOST_SLC0_TOHOST_BIT5_INT interrupt. (WO)

SLC0HOST_SLC0_TOHOST_BIT4_INT_CLR Set this bit to clear the

SLC0HOST_SLC0_TOHOST_BIT4_INT interrupt. (WO)

SLC0HOST_SLC0_TOHOST_BIT3_INT_CLR Set this bit to clear the

SLC0HOST_SLC0_TOHOST_BIT3_INT interrupt. (WO)

SLC0HOST_SLC0_TOHOST_BIT2_INT_CLR Set this bit to clear the

SLC0HOST_SLC0_TOHOST_BIT2_INT interrupt. (WO)

SLC0HOST_SLC0_TOHOST_BIT1_INT_CLR Set this bit to clear the

SLC0HOST_SLC0_TOHOST_BIT1_INT interrupt. (WO)

SLC0HOST_SLC0_TOHOST_BIT0_INT_CLR Set this bit to clear the

SLC0HOST_SLC0_TOHOST_BIT0_INT interrupt. (WO)

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8. SDIO Slave

Register 8.34: SLC0HOST_FUNC1_INT_ENA_REG (0xDC)

A
EN

HO _F SL _TO S IT5 T_ A
T A
_S 0_T OS BIT NT A
0_ HO _BI _INT ENA
HO _B _IN ENA

I T 0 T_ A
T_ A
A
T_

C0 ST 1_ C0 HO _B _IN N
ST N1_ C0 HO T_B _IN EN
N1 C OH ST_ T4_I _EN

_B _IN N
_IN EN
EN
IN

SL HO _FN SL _TO ST IT6 T_E

ST IT1 T_E
_
_
T_

A
T_ A

C0 ST 1_ C0 HO _B _IN
KE

EN
_IN EN

SL 0HO _FN _SL _TO OST IT7

3
TO ST T2
AC

DF T_

I
_B
_P

_U IN
RX F_
W

SL HO _FN SL _TO ST

T
NE

0 _ OV

C0 ST 1_ C0 HO
ST 1 C0 H
X_

LC X_

SL 0HO _FN _SL _TO

LC O
_R

_S 0_T

_F SL _T
0

ST 1 C0
LC

N1 C
_F SL

SL HO _FN SL
_S

ST N1_

C0 ST 1_
N1

SL 0HO _FN
_F

HO _F
ST

C0 OST

ST
d)

d)

d)

d)
HO

SL 0HO
rve

rve

rve

rve
H
C0

C0
se

se

se

se

C
C

C
SL

SL
SL

SL
(re

(re

(re

(re
31 26 25 24 23 22 18 17 16 15 8 7 6 5 4 3 2 1 0

0x00 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Reset

SLC0HOST_FN1_SLC0_RX_NEW_PACKET_INT_ENA The interrupt enable bit for the

SLC0HOST_FN1_SLC0_RX_NEW_PACKET_INT interrupt. (R/W)

SLC0HOST_FN1_SLC0_TX_OVF_INT_ENA The interrupt enable bit for the

SLC0HOST_FN1_SLC0_TX_OVF_INT interrupt. (R/W)

SLC0HOST_FN1_SLC0_RX_UDF_INT_ENA The interrupt enable bit for the

SLC0HOST_FN1_SLC0_RX_UDF_INT interrupt. (R/W)

SLC0HOST_FN1_SLC0_TOHOST_BIT7_INT_ENA The interrupt enable bit for the

SLC0HOST_FN1_SLC0_TOHOST_BIT7_INT interrupt. (R/W)

SLC0HOST_FN1_SLC0_TOHOST_BIT6_INT_ENA The interrupt enable bit for the

SLC0HOST_FN1_SLC0_TOHOST_BIT6_INT interrupt. (R/W)

SLC0HOST_FN1_SLC0_TOHOST_BIT5_INT_ENA The interrupt enable bit for the

SLC0HOST_FN1_SLC0_TOHOST_BIT5_INT interrupt. (R/W)

SLC0HOST_FN1_SLC0_TOHOST_BIT4_INT_ENA The interrupt enable bit for the

SLC0HOST_FN1_SLC0_TOHOST_BIT4_INT interrupt. (R/W)

SLC0HOST_FN1_SLC0_TOHOST_BIT3_INT_ENA The interrupt enable bit for the

SLC0HOST_FN1_SLC0_TOHOST_BIT3_INT interrupt. (R/W)

SLC0HOST_FN1_SLC0_TOHOST_BIT2_INT_ENA The interrupt enable bit for the

SLC0HOST_FN1_SLC0_TOHOST_BIT2_INT interrupt. (R/W)

SLC0HOST_FN1_SLC0_TOHOST_BIT1_INT_ENA The interrupt enable bit for the

SLC0HOST_FN1_SLC0_TOHOST_BIT1_INT interrupt. (R/W)

SLC0HOST_FN1_SLC0_TOHOST_BIT0_INT_ENA The interrupt enable bit for the

SLC0HOST_FN1_SLC0_TOHOST_BIT0_INT interrupt. (R/W)

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8. SDIO Slave

Register 8.35: SLCHOST_CONF_REG (0x1F0)

P
P

M
M

A
SA

20

11
_S
S_

IO

O
G

DI
O

SD
NE
_P

_S
_

_
RC

RC

RC

RC
_F

_F

_F

_F
ST

ST

ST

ST
d)

)
ed
ve

O
rv

CH

CH

CH

CH
er

se
s

SL

SL

SL

SL
(re

(re
31 28 27 20 19 15 14 10 9 5 4 0

0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Reset

SLCHOST_FRC_POS_SAMP Set this bit to sample the corresponding signal at the rising clock edge.
(R/W)

SLCHOST_FRC_NEG_SAMP Set this bit to sample the corresponding signal at the falling clock edge.
(R/W)

SLCHOST_FRC_SDIO20 Set this bit to output the corresponding signal at the rising clock edge.
(R/W)

SLCHOST_FRC_SDIO11 Set this bit to output the corresponding signal at the falling clock edge.
(R/W)

8.7 HINF Registers

The third block of SDIO control registers starts at 0x3FF4_B000.

Register 8.36: HINF_CFG_DATA1_REG (0x4)

Y1 LE
AD AB
RE N
O _E
_I D
O E
DI PE
_S HS
NF IG
d )
ve

HI F_H
r
se

N
(re

HI

31 3 2 1

0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Reset

HINF_HIGHSPEED_ENABLE Please initialize to 1. Do not modify it. (R/W)

HINF_SDIO_IOREADY1 Please initialize to 1. Do not modify it. (R/W)

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9. SD/MMC Host Controller

9.1 Overview
The ESP32 memory card interface controller provides a hardware interface between the Advanced Peripheral
Bus (APB) and an external memory device. The memory card interface allows the ESP32 to be connected to
SDIO memory cards, MMC cards and devices with a CE-ATA interface. It supports two external cards (Card0
and Card1).

9.2 Features
This module has the following features:

• Two external cards

• Supports SD Memory Card standard: versions 3.0 and 3.01

• Supports MMC: versions 4.41, 4.5, and 4.51

• Supports CE-ATA: version 1.1

• Supports 1-bit, 4-bit, and 8-bit (Card0 only) modes

The SD/MMC controller topology is shown in Figure 32. The controller supports two peripherals which cannot be
functional at the same time.

Figure 32: SD/MMC Controller Topology

9.3 SD/MMC External Interface Signals

The primary external interface signals, which enable the SD/MMC controller to communicate with an external
device, are clock (clk), command (cmd) and data signals. Additional signals include the card interrupt, card
detect, and write-protect signals. The direction of each signal is shown in Figure 33. The direction and
description of each pin are listed in Table 33.

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Figure 33: SD/MMC Controller External Interface Signals

Table 33: SD/MMC Signal Description

Pin Direction Description

cclk_out Output Clock signals for slave device
ccmd Duplex Duplex command/response lines
cdata Duplex Duplex data read/write lines
card_detect_n Input Card detection input line
card_write_prt Input Card write protection status input

9.4 Functional Description

9.4.1 SD/MMC Host Controller Architecture
The SD/MMC host controller consists of two main functional blocks, as shown in Figure 34:

• Bus Interface Unit (BIU): It provides APB interfaces for registers, data read and write operation by FIFO and
DMA.

• Card Interface Unit (CIU): It handles external memory card interface protocols. It also provides clock control.

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Figure 34: SDIO Host Block Diagram

9.4.1.1 BIU

The BIU provides the access to registers and FIFO data through the Host Interface Unit (HIU). Additionally, it
provides FIFO access to independent data through a DMA interface. The host interface can be configured as an
APB interface. Figure 34 illustrates the internal components of the BIU. The BIU provides the following
functions:

• Host interface

• DMA interface

• Interrupt control

• Register access

• FIFO access

• Power/pull-up control and card detection

9.4.1.2 CIU

The CIU module implements the card-specific protocols. Within the CIU, the command path control unit and
data path control unit prompt the controller to interface with the command and data ports, respectively, of the
SD/MMC/CE-ATA cards. The CIU also provides clock control. Figure 34 illustrates the internal structure of the
CIU, which consists of the following primary functional blocks:

• Command path

• Data path

• SDIO interrupt control

• Clock control

• Mux/demux unit

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9.4.2 Command Path

The command path performs the following functions:

• Configures clock parameters

• Configures card command parameters

• Sends commands to card bus (ccmd_out line)

• Receives responses from card bus (ccmd_in line)

• Sends responses to BIU

• Drives the P-bit on the command line

The command path State Machine is shown in Figure 35.

Figure 35: Command Path State Machine

9.4.3 Data Path

The data path block pops FIFO data and transmits them on cdata_out during a write-data transfer, or it receives
data on cdata_in and pushes them into FIFO during a read-data transfer. The data path loads new data
parameters, i.e., expected data, read/write data transfer, stream/block transfer, block size, byte count, card type,
timeout registers, etc., whenever a data transfer command is not in progress.

If the data_expected bit is set in the Command register, the new command is a data-transfer command and the
data path starts one of the following operations:

• Transmitting data if the read/write bit = 1

• Receiving data if read/write bit = 0

9.4.3.1 Data Transmit Operation

The data transmit state machine is illustrated in Figure 36. The module starts data transmission two clock cycles
after a response for the data-write command is received. This occurs even if the command path detects a
response error or a cyclic redundancy check (CRC) error in a response. If no response is received from the card
until the response timeout, no data are transmitted. Depending on the value of the transfer_mode bit in the
Command register, the data-transmit state machine adds data to the card’s data bus in a stream or in block(s).
The data transmit state machine is shown in Figure 36.

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Figure 36: Data Transmit State Machine

9.4.3.2 Data Receive Operation

The data-receive state machine is illustrated in Figure 37. The module receives data two clock cycles after the
end bit of a data-read command, even if the command path detects a response error or a CRC error. If no
response is received from the card and a response timeout occurs, the BIU does not receive a signal about the
completion of the data transfer. If the command sent by the CIU is an illegal operation for the card, it would
prevent the card from starting a read-data transfer, and the BIU will not receive a signal about the completion of
the data transfer.

If no data are received by the data timeout, the data path signals a data timeout to the BIU, which marks an end
to the data transfer. Based on the value of the transfer_mode bit in the Command register, the data-receive state
machine gets data from the card’s data bus in a stream or block(s). The data receive state machine is shown in
Figure 37.

Figure 37: Data Receive State Machine

9.5 Software Restrictions for Proper CIU Operation

• Only one card at a time can be selected to execute a command or data transfer. For example, when data
are being transferred to or from a card, a new command must not be issued to another card. A new
command, however, can be issued to the same card, allowing it to read the device status or stop the
transfer.

• Only one command at a time can be issued for data transfers.

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• During an open-ended card-write operation, if the card clock is stopped due to FIFO being empty, the
software must fill FIFO with data first, and then start the card clock. Only then can it issue a stop/abort
command to the card.

• During an SDIO/COMBO card transfer, if the card function is suspended and the software wants to resume
the suspended transfer, it must first reset FIFO, and then issue the resume command as if it were a new
data-transfer command.

• When issuing card reset commands (CMD0, CMD15 or CMD52_reset), while a card data transfer is in
progress, the software must set the stop_abort_cmd bit in the Command register, so that the CIU can stop
the data transfer after issuing the card reset command.

• When the data’s end bit error is set in the RINTSTS register, the CIU does not guarantee SDIO interrupts. In
such a case, the software ignores SDIO interrupts and issues a stop/abort command to the card, so that
the card stops sending read-data.

• If the card clock is stopped due to FIFO being full during a card read, the software will read at least two
FIFO locations to restart the card clock.

• Only one CE-ATA device at a time can be selected for a command or data transfer. For example, when
data are transferred from a CE-ATA device, a new command should not be sent to another CE-ATA device.

• If a CE-ATA device’s interrupts are enabled (nIEN=0), a new RW_BLK command should not be sent to the
same device if the execution of a RW_BLK command is already in progress (the RW_BLK command used
in this databook is the RW_MULTIPLE_BLOCK MMC command defined by the CE-ATA specifications).
Only the CCSD can be sent while waiting for the CCS.

• If, however, a CE-ATA device’s interrupts are disabled (nIEN=1), a new command can be issued to the
same device, allowing it to read status information.

• Open-ended transfers are not supported in CE-ATA devices.

• The send_auto_stop signal is not supported (software should not set the send_auto_stop bit) in CE-ATA
transfers.

After configuring the command start bit to 1, the values of the following registers cannot be changed before a
command has been issued:

• CMD - command

• CMDARG - command argument

• BYTCNT - byte count

• BLKSIZ - block size

• CLKDIV - clock divider

• CKLENA - clock enable

• CLKSRC - clock source

• TMOUT - timeout

• CTYPE - card type

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9.6 RAM for Receiving and Sending Data

The submodule RAM is a buffer area for sending and receiving data. It can be divided into two units: the one is for
sending data, and the other is for receiving data. The process of sending and receiving data can also be achieved
by the CPU and DMA for reading and writing. The latter method is described in detail in Section 9.8.

9.6.1 Transmit RAM Module

There are two ways to enable a write operation: DMA and CPU read/write.

If SDIO-sending is enabled, data can be written to the transferred RAM module by APB interface or DMA. Data
will be written from register EMAC_FIFO to the CPU, directly, by an APB interface.

9.6.2 Receive RAM Module

There are two ways to enable a read operation: DMA and CPU read/write.

When a subunit of the data path receives data, the subdata will be written onto the receive-RAM. Then, these
subdata can be read either with the APB or the DMA method at the reading end. Register EMAC_FIFO can be
read by the APB directly.

9.7 Descriptor Chain

Each linked list module consists of two parts: the linked list itself and a data buffer. In other words, each module
points to a unique data buffer and the linked list that follows the module. Figure 38 shows the descriptor
chain.

Figure 38: Descriptor Chain

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9.8 The Structure of a Linked List

Each linked list consists of four words. As is shown below, Figure 39 demonstrates the linked list’s structure, and
Table 34, Table 35, Table 36, Table 37 provide the descriptions of linked lists.

Figure 39: The Structure of a Linked List

The DES0 element contains control and status information.

Table 34: DES0

Bits Name Description

When set, this bit indicates that the descriptor is
owned by the DMAC. When reset, it indicates that the
31 OWN
descriptor is owned by the Host. The DMAC clears
this bit when it completes the data transfer.
These error bits indicate the status of the transition to
or from the card.
The following bits are also present in RINTSTS, which
indicates their digital logic OR gate.
• EBE: End Bit Error
30 CES (Card Error Summary) • RTO: Response Time out
• RCRC: Response CRC
• SBE: Start Bit Error
• DRTO: Data Read Timeout
• DCRC: Data CRC for Receive
• RE: Response Error
29:6 Reserved Reserved
When set, this bit indicates that the descriptor list has
reached its final descriptor. The DMAC then returns
5 ER (End of Ring)
to the base address of the list, creating a Descriptor
Ring.
When set, this bit indicates that the second address in
CH
4 the descriptor is the Next Descriptor address. When
(Second Address Chained)
this bit is set, BS2 (DES1[25:13]) should be all zeros.

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Bits Name Description

When set, this bit indicates that this descriptor con-
tains the first buffer of the data. If the size of the first
3 FD (First Descriptor)
buffer is 0, the Next Descriptor contains the beginning
of the data.
This bit is associated with the last block of a DMA
transfer. When set, the bit indicates that the buffers
pointed by this descriptor are the last buffers of the
2 LD (Last Descriptor) data. After this descriptor is completed, the remain-
ing byte count is 0. In other words, after the descriptor
with the LD bit set is completed, the remaining byte
count should be 0.
When set, this bit will prevent the setting of the TI/RI
DIC (Disable Interrupt
1 bit of the DMAC Status Register (IDSTS) for the data
on Completion)
that ends in the buffer pointed by this descriptor.
0 Reserved Reserved

The DES1 element contains the buffer size.

Table 35: DES1

Bits Name Description

31:26 Reserved Reserved
25:13 Reserved Reserved
Indicates the data buffer byte size, which must be a
multiple of four. In the case where the buffer size is not
12:0 BS1 (Buffer 1 Size)
a multiple of four, the resulting behavior is undefined.
This field should not be zero.

The DES2 element contains the address pointer to the data buffer.
Table 36: DES2

Bits Name Description

These bits indicate the physical address of the data
31:0 Buffer Address Pointer 1
buffer.

The DES3 element contains the address pointer to the next descriptor if the present descriptor is not the last one
in a chained descriptor structure.

Table 37: DES3

Bits Name Description

If the Second Address Chained (DES0[4]) bit is set,
then this address contains the pointer to the physical
31:0 Next Descriptor Address memory where the Next Descriptor is present.

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Bits Name Description

If this is not the last descriptor, then the Next Descrip-
tor address pointer must be DES3[1:0] = 0.

9.9 Initialization
9.9.1 DMAC Initialization
The DMAC initialization should proceed as follows:

• Write to the DMAC Bus Mode Register (BMOD_REG) will set the Host bus’s access parameters.

• Write to the DMAC Interrupt Enable Register (IDINTEN) will mask any unnecessary interrupt causes.

• The software driver creates either the transmit or the receive descriptor list. Then, it writes to the DMAC
Descriptor List Base Address Register (DBADDR), providing the DMAC with the starting address of the list.

• The DMAC engine attempts to acquire descriptors from descriptor lists.

9.9.2 DMAC Transmission Initialization

The DMAC transmission occurs as follows:

1. The Host sets up the elements (DES0-DES3) for transmission, and sets the OWN bit (DES0[31]). The Host
also prepares the data buffer.

2. The Host programs the write-data command in the CMD register in BIU.

3. The Host also programs the required transmit threshold (TX_WMARK field in FIFOTH register).

4. The DMAC engine fetches the descriptor and checks the OWN bit. If the OWN bit is not set, it means that
the host owns the descriptor. In this case, the DMAC enters a suspend-state and asserts the Descriptor
Unable interrupt in the IDSTS register. In such a case, the host needs to release the DMAC by writing any
value to PLDMND_REG.

5. It then waits for the Command Done (CD) bit and no errors from BIU, which indicates that a transfer can be
done.

6. Subsequently, the DMAC engine waits for a DMA interface request (dw_dma_req) from BIU. This request
will be generated, based on the programmed transmit-threshold value. For the last bytes of data which
cannot be accessed using a burst, single transfers are performed on the AHB Master Interface.

7. The DMAC fetches the transmit data from the data buffer in the Host memory and transfers them to FIFO
for transmission to card.

8. When data span across multiple descriptors, the DMAC fetches the next descriptor and extends its
operation using the following descriptor. The last descriptor bit indicates whether the data span multiple
descriptors or not.

9. When data transmission is complete, the status information is updated in the IDSTS register by setting the
Transmit Interrupt, if it has already been enabled. Also, the OWN bit is cleared by the DMAC by performing
a write transaction to DES0.

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9.9.3 DMAC Reception Initialization

The DMAC reception occurs as follows:

1. The Host sets up the element (DES0-DES3) for reception, and sets the OWN bit (DES0[31]).

2. The Host programs the read-data command in the CMD register in BIU.

3. Then, the Host programs the required level of the receive-threshold (RX_WMARK field in FIFOTH register).

4. The DMAC engine fetches the descriptor and checks the OWN bit. If the OWN bit is not set, it means that
the host owns the descriptor. In this case, the DMA enters a suspend-state and asserts the Descriptor
Unable interrupt in the IDSTS register. In such a case, the host needs to release the DMAC by writing any
value to PLDMND_REG.

5. It then waits for the Command Done (CD) bit and no errors from BIU, which indicates that a transfer can be
done.

6. The DMAC engine then waits for a DMA interface request (dw_dma_req) from BIU. This request will be
generated, based on the programmed receive-threshold value. For the last bytes of the data which cannot
be accessed using a burst, single transfers are performed on the AHB.

7. The DMAC fetches the data from FIFO and transfers them to the Host memory.

8. When data span across multiple descriptors, the DMAC will fetch the next descriptor and extend its
operation using the following descriptor. The last descriptor bit indicates whether the data span multiple
descriptors or not.

9. When data reception is complete, the status information is updated in the IDSTS register by setting
Receive-Interrupt, if it has already been enabled. Also, the OWN bit is cleared by the DMAC by performing
a write-transaction to DES0.

9.10 Clock Phase Selection

If the setup time requirements for the input or output data signal are not met, users can specify the clock phase,
as shown in the figure below.

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Figure 40: Clock Phase Selection

Please find detailed information on the clock phase selection register CLK_EDGE_SEL in Section
Registers.

9.11 Interrupt
Interrupts can be generated as a result of various events. The IDSTS register contains all the bits that might
cause an interrupt. The IDINTEN register contains an enable bit for each of the events that can cause an
interrupt.

There are two groups of summary interrupts, ”Normal” ones (bit8 NIS) and ”Abnormal” ones (bit9 AIS), as
outlined in the IDSTS register. Interrupts are cleared by writing 1 to the position of the corresponding bit. When all
the enabled interrupts within a group are cleared, the corresponding summary bit is also cleared. When both
summary bits are cleared, the interrupt signal dmac_intr_o is de-asserted (stops signalling).

Interrupts are not queued up, and if a new interrupt-event occurs before the driver has responded to it, no
additional interrupts are generated. For example, the Receive Interrupt IDSTS[1] indicates that one or more data
were transferred to the Host buffer.

An interrupt is generated only once for concurrent events. The driver must scan the IDSTS register for the
interrupt cause.

9.12 Register Summary

Name Description Address Access

CTRL_REG Control register 0x0000 R/W
CLKDIV_REG Clock divider configuration register 0x0008 R/W
CLKSRC_REG Clock source selection register 0x000C R/W

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Name Description Address Access

CLKENA_REG Clock enable register 0x0010 R/W
TMOUT_REG Data and response timeout configuration register 0x0014 R/W
CTYPE_REG Card bus width configuration register 0x0018 R/W
BLKSIZ_REG Card data block size configuration register 0x001C R/W
BYTCNT_REG Data transfer length configuration register 0x0020 R/W
INTMASK_REG SDIO interrupt mask register 0x0024 R/W
CMDARG_REG Command argument data register 0x0028 R/W
CMD_REG Command and boot configuration register 0x002C R/W
RESP0_REG Response data register 0x0030 RO
RESP1_REG Long response data register 0x0034 RO
RESP2_REG Long response data register 0x0038 RO
RESP3_REG Long response data register 0x003C RO
MINTSTS_REG Masked interrupt status register 0x0040 RO
RINTSTS_REG Raw interrupt status register 0x0044 R/W
STATUS_REG SD/MMC status register 0x0048 RO
FIFOTH_REG FIFO configuration register 0x004C R/W
CDETECT_REG Card detect register 0x0050 RO
WRTPRT_REG Card write protection (WP) status register 0x0054 RO
TCBCNT_REG Transferred byte count register 0x005C RO
TBBCNT_REG Transferred byte count register 0x0060 RO
DEBNCE_REG Debounce filter time configuration register 0x0064 R/W
USRID_REG User ID (scratchpad) register 0x0068 R/W
RST_N_REG Card reset register 0x0078 R/W
BMOD_REG Burst mode transfer configuration register 0x0080 R/W
PLDMND_REG Poll demand configuration register 0x0084 WO
DBADDR_REG Descriptor base address register 0x0088 R/W
IDSTS_REG IDMAC status register 0x008C R/W
IDINTEN_REG IDMAC interrupt enable register 0x0090 R/W
DSCADDR_REG Host descriptor address pointer 0x0094 RO
BUFADDR_REG Host buffer address pointer register 0x0098 RO
CLK_EDGE_SEL Clock phase selection register 0x0800 R/W

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9.13 Registers
SD/MMC controller registers can be accessed by the APB bus of the CPU.

Register 9.1: CTRL_REG (0x0000)

S
TU
TA
SD _S
CC PT
P_ RU

SE
SE RT SD STO ER

ET
se WA E TA

N
O CC _ T

ES
O
AB D_ TO E_IN

(re D_ Q_R _DA

IN rve IT SP

_R
ER
D
N AU IC

DM rve BLE

CO _R SET
RE _ EA

RO T
SE _ V

LL
NT ESE
ND DE

ND _R
)

d)

T_ d)

FI _R )
R
ed

ed

A d
se A

FO E
SE TA_
ve

(re N
rv

rv

E
r
se

se

se

A
CE
(re

(re

(re
31 25 24 23 12 11 10 9 8 7 6 5 4 3 2 1 0

0x00 1 0x00 0 0 0 0 0 0 0 0 0 0 0 0 Reset

CEATA_DEVICE_INTERRUPT_STATUS Software should appropriately write to this bit after the

power-on reset or any other reset to the CE-ATA device. After reset, the CE-ATA device’s interrupt
is usually disabled (nIEN = 1). If the host enables the CE-ATA device’s interrupt, then software
should set this bit. (R/W)

SEND_AUTO_STOP_CCSD Always set send_auto_stop_ccsd and send_ccsd bits together;

send_auto_stop_ccsd should not be set independently of send_ccsd. When set, SD/MMC au-
tomatically sends an internally-generated STOP command (CMD12) to the CE-ATA device. After
sending this internally-generated STOP command, the Auto Command Done (ACD) bit in RINTSTS
is set and an interrupt is generated for the host, in case the ACD interrupt is not masked. Af-
ter sending the Command Completion Signal Disable (CCSD), SD/MMC automatically clears the
send_auto_stop_ccsd bit. (R/W)

SEND_CCSD When set, SD/MMC sends CCSD to the CE-ATA device. Software sets this bit only
if the current command is expecting CCS (that is, RW_BLK), and if interrupts are enabled for the
CE-ATA device. Once the CCSD pattern is sent to the device, SD/MMC automatically clears the
send_ccsd bit. It also sets the Command Done (CD) bit in the RINTSTS register, and generates
an interrupt for the host, in case the Command Done interrupt is not masked. NOTE: Once the
send_ccsd bit is set, it takes two card clock cycles to drive the CCSD on the CMD line. Due to this,
within the boundary conditions the CCSD may be sent to the CE-ATA device, even if the device
has signalled CCS. (R/W)

ABORT_READ_DATA After a suspend-command is issued during a read-operation, software polls the

card to find when the suspend-event occurred. Once the suspend-event has occurred, software
sets the bit which will reset the data state machine that is waiting for the next block of data. This
bit is automatically cleared once the data state machine is reset to idle. (R/W)

SEND_IRQ_RESPONSE Bit automatically clears once response is sent. To wait for MMC card inter-
rupts, host issues CMD40 and waits for interrupt response from MMC card(s). In the meantime, if
host wants SD/MMC to exit waiting for interrupt state, it can set this bit, at which time SD/MMC
command state-machine sends CMD40 response on bus and returns to idle state. (R/W)

Continued on the next page...

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Register 9.1: CTRL_REG (0x0000)

Continued from the previous page...

READ_WAIT For sending read-wait to SDIO cards. (R/W)

INT_ENABLE Global interrupt enable/disable bit. 0: Disable; 1: Enable. (R/W)

DMA_RESET To reset DMA interface, firmware should set bit to 1. This bit is auto-cleared after two
AHB clocks. (R/W)

FIFO_RESET To reset FIFO, firmware should set bit to 1. This bit is auto-cleared after completion of
reset operation. Note: FIFO pointers will be out of reset after 2 cycles of system clocks in addition
to synchronization delay (2 cycles of card clock), after the fifo_reset is cleared. (R/W)

CONTROLLER_RESET To reset controller, firmware should set this bit. This bit is auto-cleared after
two AHB and two cclk_in clock cycles. (R/W)

Register 9.2: CLKDIV_REG (0x0008)

R3

R2

R1

R0
DE

DE

DE

DE
VI

VI

VI

VI
DI

DI

DI

DI
K_

K_

K_

K_
CL

CL

CL

CL
31 24 23 16 15 8 7 0

0x000 0x000 0x000 0x000 Reset

CLK_DIVIDER3 Clock divider-3 value. Clock division factor is 2*n, where n=0 bypasses the divider
(division factor of 1). For example, a value of 1 means divide by 2*1 = 2, a value of 0xFF means
divide by 2*255 = 510, and so on. In MMC-Ver3.3-only mode, these bits are not implemented
because only one clock divider is supported. (R/W)

CLK_DIVIDER2 Clock divider-2 value. Clock division factor is 2*n, where n=0 bypasses the divider
(division factor of 1). For example, a value of 1 means divide by 2*1 = 2, a value of 0xFF means
divide by 2*255 = 510, and so on. In MMC-Ver3.3-only mode, these bits are not implemented
because only one clock divider is supported. (R/W)

CLK_DIVIDER1 Clock divider-1 value. Clock division factor is 2*n, where n=0 bypasses the divider
(division factor of 1). For example, a value of 1 means divide by 2*1 = 2, a value of 0xFF means
divide by 2*255 = 510, and so on. In MMC-Ver3.3-only mode, these bits are not implemented
because only one clock divider is supported. (R/W)

CLK_DIVIDER0 Clock divider-0 value. Clock division factor is 2*n, where n=0 bypasses the divider
(division factor of 1). For example, a value of 1 means divide by 2*1 = 2, a value of 0xFF means
divide by 2*255 = 510, and so on. In MMC-Ver3.3-only mode, these bits are not implemented
because only one clock divider is supported. (R/W)

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Register 9.3: CLKSRC_REG (0x000C)

EG
_R
d)

RC
ve

KS
r
se

CL
(re
31 4 3 0

0x000000 0x0 Reset

CLKSRC_REG Clock divider source for two SD cards is supported. Each card has two bits assigned
to it. For example, bit[1:0] are assigned for card 0, bit[3:2] are assigned for card 1. Card 0 maps
and internally routes clock divider[0:3] outputs to cclk_out[1:0] pins, depending on bit value.
00 : Clock divider 0;
01 : Clock divider 1;
10 : Clock divider 2;
11 : Clock divider 3.
In MMC-Ver3.3-only controller, only one clock divider is supported. The cclk_out is always from
clock divider 0, and this register is not implemented. (R/W)

Register 9.4: CLKENA_REG (0x0010)

L
BE
NA
d)

_E
ve

LK
r
se

CC
(re

31 2 1 0

0x00000 0x00000 Reset

CCLK_ENABEL Clock-enable control for two SD card clocks and one MMC card clock is supported.
0: Clock disabled;
1: Clock enabled.
In MMC-Ver3.3-only mode, since there is only one cclk_out, only cclk_enable[0] is used. (R/W)

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9. SD/MMC Host Controller

Register 9.5: TMOUT_REG (0x0014)

UT
EO
IM
UT

_T
EO

E
NS
M
TI

O
_

SP
TA
DA

RE
31 8 7 0

0x0FFFFFF 0x040 Reset

DATA_TIMEOUT Value for card data read timeout. This value is also used for data starvation by host
timeout. The timeout counter is started only after the card clock is stopped. This value is specified
in number of card output clocks, i.e. cclk_out of the selected card.
NOTE: The software timer should be used if the timeout value is in the order of 100 ms. In this
case, read data timeout interrupt needs to be disabled. (R/W)

RESPONSE_TIMEOUT Response timeout value. Value is specified in terms of number of card output
clocks, i.e., cclk_out. (R/W)

Register 9.6: CTYPE_REG (0x0018)

8

4
TH

TH
ID

ID
)

)
_W

_W
ed

ed
rv

rv
RD

RD
se

se
CA

CA
(re

(re

31 18 17 16 15 2 1 0

0x00000 0x00000 0x00000 0x00000 Reset

CARD_WIDTH8 One bit per card indicates if card is in 8-bit mode.

0: Non 8-bit mode;
1: 8-bit mode.
Bit[17:16] correspond to card[1:0] respectively. (R/W)

CARD_WIDTH4 One bit per card indicates if card is 1-bit or 4-bit mode.
0: 1-bit mode;
1: 4-bit mode.
Bit[1:0] correspond to card[1:0] respectively. Only NUM_CARDS*2 number of bits are imple-
mented. (R/W)

Register 9.7: BLKSIZ_REG (0x001C)

E
IZ
_S
)
ed

CK
rv
se

O
BL
(re

31 16 15 0

0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0x00200 Reset

BLOCK_SIZE Block size. (R/W)

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9. SD/MMC Host Controller

Register 9.8: BYTCNT_REG (0x0020)

31 0

0x000000200 Reset

BYTCNT_REG Number of bytes to be transferred, should be an integral multiple of Block Size for
block transfers. For data transfers of undefined byte lengths, byte count should be set to 0. When
byte count is set to 0, it is the responsibility of host to explicitly send stop/abort command to
terminate data transfer. (R/W)

Register 9.9: INTMASK_REG (0x0024)

K
AS
_M

K
NT
d)

AS
ve

_I

_M
r

IO
se

T
SD
(re

IN
31 18 17 16 15 0

0x00000 0x00000 0x00000 Reset

SDIO_INT_MASK SDIO interrupt mask, one bit for each card. Bit[17:16] correspond to card[15:0] re-
spectively. When masked, SDIO interrupt detection for that card is disabled. 0 masks an interrupt,
and 1 enables an interrupt. In MMC-Ver3.3-only mode, these bits are always 0. (R/W)

INT_MASK These bits used to mask unwanted interrupts. A value of 0 masks interrupt, and a value
of 1 enables the interrupt. (R/W)
Bit 15 (EBE): End-bit error, read/write (no CRC)
Bit 14 (ACD): Auto command done
Bit 13 (SBE/BCI): Start Bit Error/Busy Clear Interrupt
Bit 12 (HLE): Hardware locked write error
Bit 11 (FRUN): FIFO underrun/overrun error
Bit 10 (HTO): Data starvation-by-host timeout/Volt_switch_int
Bit 9 (DRTO): Data read timeout
Bit 8 (RTO): Response timeout
Bit 7 (DCRC): Data CRC error
Bit 6 (RCRC): Response CRC error
Bit 5 (RXDR): Receive FIFO data request
Bit 4 (TXDR): Transmit FIFO data request
Bit 3 (DTO): Data transfer over
Bit 2 (CD): Command done
Bit 1 (RE): Response error
Bit 0 (CD): Card detect

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9. SD/MMC Host Controller

Register 9.10: CMDARG_REG (0x0028)

31 0

0x000000000 Reset

CMDARG_REG Value indicates command argument to be passed to the card. (R/W)

Register 9.11: CMD_REG (0x002C)

Y
NL
_O
RS

TE
TE

EX T RC
T R M P LE
IS

DA D/W R_ STO MP

E_ NG _C
EG
_R E

TR D_ VD _CM N

PE H
CK IC

CT
N R T IO
A AU AT D

NS LE SE
A FE _ O
LO EV

E
RE NS TO A_C
SE T_P OR IZAT

O E_ N
RE PO ES ED
CH A_E ITE OD
TE ATA D

R
_C _D

SP NS PO
DA CE TE

BE

S _R T
AI AB L

RE CK PEC
US rve MD

W P_ ITIA
UP _ EC

X
UM
(re rve E

DE
se OL

AD XP
(re _H )

(re rve )
(re rve )
se d)

CC rve )
RE _E )
se C

O N

E X
E d

se d
se d

se d
S d

_N

IN
(re RT_

(re rve

I
ST _

D_
RD

ND
A

CM
CA

SE
ST

31 30 29 28 27 26 25 24 23 22 21 20 16 15 14 13 12 11 10 9 8 7 6 5 0

0 0 1 0 0 0 0 0 0 0 0 0x00 0 0 0 0 0 0 0 0 0 0 0x00 Reset

START_CMD Start command. Once command is served by the CIU, this bit is automatically cleared.
When this bit is set, host should not attempt to write to any command registers. If a write is
attempted, hardware lock error is set in raw interrupt register. Once command is sent and a
response is received from SD_MMC_CEATA cards, Command Done bit is set in the raw interrupt
Register. (R/W)

USE_HOLE Use Hold Register. (R/W) 0: CMD and DATA sent to card bypassing HOLD Register; 1:
CMD and DATA sent to card through the HOLD Register.

CCS_EXPECTED Expected Command Completion Signal (CCS) configuration. (R/W)

0: Interrupts are not enabled in CE-ATA device (nIEN = 1 in ATA control register), or command
does not expect CCS from device.
1: Interrupts are enabled in CE-ATA device (nIEN = 0), and RW_BLK command expects command
completion signal from CE-ATA device.
If the command expects Command Completion Signal (CCS) from the CE-ATA device, the software
should set this control bit. SD/MMC sets Data Transfer Over (DTO) bit in RINTSTS register and
generates interrupt to host if Data Transfer Over interrupt is not masked.

READ_CEATA_DEVICE Read access flag. (R/W)

0: Host is not performing read access (RW_REG or RW_BLK)towards CE-ATA device
1: Host is performing read access (RW_REG or RW_BLK) towards CE-ATA device.
Software should set this bit to indicate that CE-ATA device is being accessed for read transfer.
This bit is used to disable read data timeout indication while performing CE-ATA read transfers.
Maximum value of I/O transmission delay can be no less than 10 seconds. SD/MMC should not
indicate read data timeout while waiting for data from CE-ATA device. (R/W)

Continued on the next page...

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9. SD/MMC Host Controller

Register 9.11: CMD_REG (0x002C)

Continued from the previous page...

UPDATE_CLOCK_REGISTERS_ONLY (R/W)
0: Normal command sequence.
1: Do not send commands, just update clock register value into card clock domain
Following register values are transferred into card clock domain: CLKDIV, CLRSRC, and CLKENA.
Changes card clocks (change frequency, truncate off or on, and set low-frequency mode). This
is provided in order to change clock frequency or stop clock without having to send command to
cards.
During normal command sequence, when update_clock_registers_only = 0, following control reg-
isters are transferred from BIU to CIU: CMD, CMDARG, TMOUT, CTYPE, BLKSIZ, and BYTCNT.
CIU uses new register values for new command sequence to card(s). When bit is set, there are no
Command Done interrupts because no command is sent to SD_MMC_CEATA cards.

CARD_NUMBER Card number in use. Represents physical slot number of card being accessed. In
MMC-Ver3.3-only mode, up to two cards are supported. In SD-only mode, up to two cards are
supported. (R/W)

SEND_INITIALIZATION (R/W)
0: Do not send initialization sequence (80 clocks of 1) before sending this command.
1: Send initialization sequence before sending this command.
After power on, 80 clocks must be sent to card for initialization before sending any commands to
card. Bit should be set while sending first command to card so that controller will initialize clocks
before sending command to card.

STOP_ABORT_CMD (R/W)
0: Neither stop nor abort command can stop current data transfer. If abort is sent to function-
number currently selected or not in data-transfer mode, then bit should be set to 0.
1: Stop or abort command intended to stop current data transfer in progress. When open-ended
or predefined data transfer is in progress, and host issues stop or abort command to stop data
transfer, bit should be set so that command/data state-machines of CIU can return correctly to idle
state.

WAIT_PRVDATA_COMPLETE (R/W)
0: Send command at once, even if previous data transfer has not completed;
1: Wait for previous data transfer to complete before sending Command.
The wait_prvdata_complete = 0 option is typically used to query status of card during data transfer
or to stop current data transfer. card_number should be same as in previous command.

SEND_AUTO_STOP (R/W)
0: No stop command is sent at the end of data transfer;
1: Send stop command at the end of data transfer.

Continued on the next page...

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9. SD/MMC Host Controller

Register 9.11: CMD_REG (0x002C)

Continued from the previous page ...

TRANSFER_MODE (R/W)
0: Block data transfer command;
1: Stream data transfer command. Don’t care if no data expected.

READ/WRITE (R/W)
0: Read from card;
1: Write to card.
Don’t care if no data is expected from card.

DATA_EXPECTED (R/W)
0: No data transfer expected.
1: Data transfer expected.

CHECK_RESPONSE_CRC (R/W)
0: Do not check;
1: Check response CRC.
Some of command responses do not return valid CRC bits. Software should disable CRC checks
for those commands in order to disable CRC checking by controller.

RESPONSE_LENGTH (R/W)
0: Short response expected from card;
1: Long response expected from card.

RESPONSE_EXPECT (R/W)
0: No response expected from card;
1: Response expected from card.

CMD_INDEX Command index. (R/W)

Register 9.12: RESP0_REG (0x0030)

31 0

0x000000000 Reset

RESP0_REG Bit[31:0] of response. (RO)

Register 9.13: RESP1_REG (0x0034)

31 0

0x000000000 Reset

RESP1_REG Bit[63:32] of long response. (RO)

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9. SD/MMC Host Controller

Register 9.14: RESP2_REG (0x0038)

31 0

0x000000000 Reset

RESP2_REG Bit[95:64] of long response. (RO)

Register 9.15: RESP3_REG (0x003C)

31 0

0x000000000 Reset

RESP3_REG Bit[127:96] of long response. (RO)

Register 9.16: MINTSTS_REG (0x0040)

SK
_M

SK
PT
RU

M
S_
ER

TU
NT
d)

TA
ve

_I

_S
r

IO
se

T
SD
(re

IN
31 18 17 16 15 0

0 0x0 0x00000 Reset

SDIO_INTERRUPT_MSK Interrupt from SDIO card, one bit for each card. Bit[17:16] correspond
to card1 and card0, respectively. SDIO interrupt for card is enabled only if corresponding
sdio_int_mask bit is set in Interrupt mask register (Setting mask bit enables interrupt). (RO)

INT_STATUS_MSK Interrupt enabled only if corresponding bit in interrupt mask register is set. (RO)
Bit 15 (EBE): End-bit error, read/write (no CRC)
Bit 14 (ACD): Auto command done
Bit 13 (SBE/BCI): Start Bit Error/Busy Clear Interrupt
Bit 12 (HLE): Hardware locked write error
Bit 11 (FRUN): FIFO underrun/overrun error
Bit 10 (HTO): Data starvation by host timeout (HTO)
Bit 9 (DTRO): Data read timeout
Bit 8 (RTO): Response timeout
Bit 7 (DCRC): Data CRC error
Bit 6 (RCRC): Response CRC error
Bit 5 (RXDR): Receive FIFO data request
Bit 4 (TXDR): Transmit FIFO data request
Bit 3 (DTO): Data transfer over
Bit 2 (CD): Command done
Bit 1 (RE): Response error
Bit 0 (CD): Card detect

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9. SD/MMC Host Controller

Register 9.17: RINTSTS_REG (0x0044)

AW
_R

W
PT

RA
RU

S_
ER

U
NT
d)

AT
ve

ST
_I
er

IO

T_
s

SD
(re

IN
31 18 17 16 15 0

0x00000 0x0 0x00000 Reset

SDIO_INTERRUPT_RAW Interrupt from SDIO card, one bit for each card. Bit[17:16] correspond to
card1 and card0, respectively. Setting a bit clears the corresponding interrupt bit and writing 0 has
no effect. (R/W)
0: No SDIO interrupt from card;
1: SDIO interrupt from card.
In MMC-Ver3.3-only mode, these bits are always 0. Bits are logged regardless of interrupt-mask
status. (R/W)

INT_STATUS_RAW Setting a bit clears the corresponding interrupt and writing 0 has no effect. Bits
are logged regardless of interrupt mask status. (R/W)
Bit 15 (EBE): End-bit error, read/write (no CRC)
Bit 14 (ACD): Auto command done
Bit 13 (SBE/BCI): Start Bit Error/Busy Clear Interrupt
Bit 12 (HLE): Hardware locked write error
Bit 11 (FRUN): FIFO underrun/overrun error
Bit 10 (HTO): Data starvation by host timeout (HTO)
Bit 9 (DTRO): Data read timeout
Bit 8 (RTO): Response timeout
Bit 7 (DCRC): Data CRC error
Bit 6 (RCRC): Response CRC error
Bit 5 (RXDR): Receive FIFO data request
Bit 4 (TXDR): Transmit FIFO data request
Bit 3 (DTO): Data transfer over
Bit 2 (CD): Command done
Bit 1 (RE): Response error
Bit 0 (CD): Card detect

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9. SD/MMC Host Controller

Register 9.18: STATUS_REG (0x0048)

S
TE
Y

K
US

M K
TA

AR
ER AR
_B

_S
X

AT M
DE

_3 Y C

M
US

W R
TA US _M

FS

X_ ATE
IN

T
T

FI _T PTY
DA A_B ATE
E_

TA

D_
UN

_R W
FI _E L
NS

_S

AN

FO UL
se d)

FO X_
T T
ed

FO M
DA A_S
(re rve

O
_C

FI _F
rv

SP

M
se

FO

FO
T

CO
DA
RE
(re

FI

FI
31 30 29 17 16 11 10 9 8 7 4 3 2 1 0

0 0 0x000 0x00 1 1 1 0x01 0 1 1 0 Reset

FIFO_COUNT FIFO count, number of filled locations in FIFO. (RO)

RESPONSE_INDEX Index of previous response, including any auto-stop sent by core. (RO)

DATA_STATE_MC_BUSY Data transmit or receive state-machine is busy. (RO)

DATA_BUSY Inverted version of raw selected card_data[0]. (RO)

0: Card data not busy;
1: Card data busy.

DATA_3_STATUS Raw selected card_data[3], checks whether card is present. (RO)

0: card not present;
1: card present.

COMMAND_FSM_STATES Command FSM states. (RO)

0: Idle
1: Send init sequence
2: Send cmd start bit
3: Send cmd tx bit
4: Send cmd index + arg
5: Send cmd crc7
6: Send cmd end bit
7: Receive resp start bit
8: Receive resp IRQ response
9: Receive resp tx bit
10: Receive resp cmd idx
11: Receive resp data
12: Receive resp crc7
13: Receive resp end bit
14: Cmd path wait NCC
15: Wait, cmd-to-response turnaround

FIFO_FULL FIFO is full status. (RO)

FIFO_EMPTY FIFO is empty status. (RO)

FIFO_TX_WATERMARK FIFO reached Transmit watermark level, not qualified with data transfer. (RO)

FIFO_RX_WATERMARK FIFO reached Receive watermark level, not qualified with data transfer. (RO)

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9. SD/MMC Host Controller

Register 9.19: FIFOTH_REG (0x004C)

ZE
SI
N_
IO
ACT
ANS
TR
E_
PL

K
TI

K
AR
UL

AR
d)

)
ed

ed
M

M
ve

M
rv

rv
A_

_W

_W
er

se

se
s

DM

RX

TX
(re

(re

(re
31 30 28 27 26 16 15 12 11 0

0 0x0 0 x x x x x x x x x x x 0 0 0 0 0x0000 Reset

DMA_MULTIPLE_TRANSACTION_SIZE Burst size of multiple transaction, should be programmed

same as DMA controller multiple-transaction-size SRC/DEST_MSIZE. 000: 1-byte transfer; 001:
4-byte transfer; 010: 8-byte transfer; 011: 16-byte transfer; 100: 32-byte transfer; 101: 64-byte
transfer; 110: 128-byte transfer; 111: 256-byte transfer. (R/W)

RX_WMARK FIFO threshold watermark level when receiving data to card.When FIFO data count
reaches greater than this number (FIFO_RX_WATERMARK), DMA/FIFO request is raised. During
end of packet, request is generated regardless of threshold programming in order to complete any
remaining data.In non-DMA mode, when receiver FIFO threshold (RXDR) interrupt is enabled, then
interrupt is generated instead of DMA request.During end of packet, interrupt is not generated if
threshold programming is larger than any remaining data. It is responsibility of host to read remain-
ing bytes on seeing Data Transfer Done interrupt.In DMA mode, at end of packet, even if remaining
bytes are less than threshold, DMA request does single transfers to flush out any remaining bytes
before Data Transfer Done interrupt is set. (R/W)

TX_WMARK FIFO threshold watermark level when transmitting data to card. When FIFO data count
is less than or equal to this number (FIFO_TX_WATERMARK), DMA/FIFO request is raised. If In-
terrupt is enabled, then interrupt occurs. During end of packet, request or interrupt is generated,
regardless of threshold programming.In non-DMA mode, when transmit FIFO threshold (TXDR) in-
terrupt is enabled, then interrupt is generated instead of DMA request. During end of packet, on
last interrupt, host is responsible for filling FIFO with only required remaining bytes (not before FIFO
is full or after CIU completes data transfers, because FIFO may not be empty). In DMA mode, at
end of packet, if last transfer is less than burst size, DMA controller does single cycles until required
bytes are transferred. (R/W)

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9. SD/MMC Host Controller

Register 9.20: CDETECT_REG (0x0050)

N
T_
EC
ET
d)

_D
ve

RD
r
se

CA
(re
31 2 1 0

0x0 0x0 Reset

CARD_DETECT_N Value on card_detect_n input ports (1 bit per card), read-only bits.0 represents
presence of card. Only NUM_CARDS number of bits are implemented. (RO)

Register 9.21: WRTPRT_REG (0x0054)

CT
TE
OR
d)

_P
ve

TE
r
se

RI
(re

W
31 2 1 0

0x0 0x0 Reset

WRITE_PROTECT Value on card_write_prt input ports (1 bit per card).1 represents write protection.
Only NUM_CARDS number of bits are implemented. (RO)

Register 9.22: TCBCNT_REG (0x005C)

31 0

0x000000000 Reset

TCBCNT_REG Number of bytes transferred by CIU unit to card. (RO)

Register 9.23: TBBCNT_REG (0x0060)

31 0

0x000000000 Reset

TBBCNT_REG Number of bytes transferred between Host/DMA memory and BIU FIFO. (RO)

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9. SD/MMC Host Controller

Register 9.24: DEBNCE_REG (0x0064)

T
UN
CO
_
CE
)

UN
ed
rv

BO
se

DE
(re

31 24 23 0

0 0 0 0 0 0 0 0 0x0000000 Reset

DEBOUNCE_COUNT Number of host clocks (clk) used by debounce filter logic. The typical de-
bounce time is 5 ~ 25 ms to prevent the card instability when the card is inserted or removed.
(R/W)

Register 9.25: USRID_REG (0x0068)

31 0

0x000000000 Reset

USRID_REG User identification register, value set by user. Default reset value can be picked by user
while configuring core before synthesis. Can also be used as a scratchpad register by user. (R/W)

Register 9.26: RST_N_REG (0x0078)

ET
ES
_R
RD
d)

CA
ver

T_
se

RS
(re

31 2 1 0

0 0x1 Reset

RST_CARD_RESET Hardware reset.1: Active mode; 0: Reset. These bits cause the cards to enter
pre-idle state, which requires them to be re-initialized. CARD_RESET[0] should be set to 1’b0 to
reset card0, CARD_RESET[1] should be set to 1’b0 to reset card1.The number of bits implemented
is restricted to NUM_CARDS. (R/W)

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9. SD/MMC Host Controller

Register 9.27: BMOD_REG (0x0080)

R
BL

SW
DE

O FB
)

)
P
ed

ed
D_

D_

BM D_
D_
rv

rv
O

O
se

se
BM

BM

BM
(re

(re
31 11 10 8 7 6 2 1 0

0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0x0 0 0x00 0 0 Reset

BMOD_PBL Programmable Burst Length. These bits indicate the maximum number of beats to be
performed in one IDMAC transaction. The IDMAC will always attempt to burst as specified in PBL
each time it starts a burst transfer on the host bus. The permissible values are 1, 4, 8, 16, 32, 64,
128 and 256. This value is the mirror of MSIZE of FIFOTH register. In order to change this value,
write the required value to FIFOTH register. This is an encode value as follows:
000: 1-byte transfer; 001: 4-byte transfer; 010: 8-byte transfer; 011: 16-byte transfer; 100: 32-
byte transfer; 101: 64-byte transfer; 110: 128-byte transfer; 111: 256-byte transfer.
PBL is a read-only value and is applicable only for data access, it does not apply to descriptor
access. (R/W)

BMOD_DE IDMAC Enable. When set, the IDMAC is enabled. (R/W)

BMOD_FB Fixed Burst. Controls whether the AHB Master interface performs fixed burst transfers or
not. When set, the AHB will use only SINGLE, INCR4, INCR8 or INCR16 during start of normal
burst transfers. When reset, the AHB will use SINGLE and INCR burst transfer operations. (R/W)

BMOD_SWR Software Reset. When set, the DMA Controller resets all its internal registers. It is
automatically cleared after one clock cycle. (R/W)

Register 9.28: PLDMND_REG (0x0080)

31 0

0x000000000 Reset

PLDMND_REG Poll Demand. If the OWN bit of a descriptor is not set, the FSM goes to the Suspend
state. The host needs to write any value into this register for the IDMAC FSM to resume normal
descriptor fetch operation. This is a write only register, PD bit is write-only. (WO)

Register 9.29: DBADDR_REG (0x0088)

31 0

0x000000000 Reset

DBADDR_REG Start of Descriptor List. Contains the base address of the First Descriptor. The LSB
bits [1:0] are ignored and taken as all-zero by the IDMAC internally. Hence these LSB bits may be
treated as read-only. (R/W)

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9. SD/MMC Host Controller

Register 9.30: IDSTS_REG (0x008C)

DE
CO
E_
SM

(re S_ ES

ID S_ E
(re NIS
S_ S

ID rve U
FB

ST FB
d)

ID ed)

ID S_ )

ST RI
ST AI

TI
ST d
ST C
se D
_F
ve

S_

ID _

ID S_

S_
rv
TS

S
er

se
ST

ST

ST
s

S
(re

ID

ID

ID
31 17 16 13 12 10 9 8 7 6 5 4 3 2 1 0

0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0x00 0x0 0 0 0 0 0 0 0 0 0 0 Reset

IDSTS_FSM DMAC FSM present state: (RO)

0: DMA_IDLE; 1: DMA_SUSPEND; 2: DESC_RD; 3: DESC_CHK; 4: DMA_RD_REQ_WAIT
5: DMA_WR_REQ_WAIT; 6: DMA_RD; 7: DMA_WR; 8: DESC_CLOSE.

IDSTS_FBE_CODE Fatal Bus Error Code. Indicates the type of error that caused a Bus Error. Valid
only when the Fatal Bus Error bit IDSTS[2] is set. This field does not generate an interrupt. (RO)
3b001: Host Abort received during transmission;
3b010: Host Abort received during reception;
Others: Reserved.

IDSTS_AIS Abnormal Interrupt Summary. Logical OR of the following: IDSTS[2] : Fatal Bus Interrupt,
IDSTS[4] : DU bit Interrupt. Only unmasked bits affect this bit. This is a sticky bit and must be
cleared each time a corresponding bit that causes AIS to be set is cleared. Writing 1 clears this
bit. (R/W)

IDSTS_NIS Normal Interrupt Summary. Logical OR of the following: IDSTS[0] : Transmit Interrupt,
IDSTS[1] : Receive Interrupt. Only unmasked bits affect this bit. This is a sticky bit and must be
cleared each time a corresponding bit that causes NIS to be set is cleared. Writing 1 clears this
bit. (R/W)

IDSTS_CES Card Error Summary. Indicates the status of the transaction to/from the card, also
present in RINTSTS. Indicates the logical OR of the following bits: EBE : End Bit Error, RTO :
Response Timeout/Boot Ack Timeout, RCRC : Response CRC, SBE : Start Bit Error, DRTO : Data
Read Timeout/BDS timeout, DCRC : Data CRC for Receive, RE : Response Error.
Writing 1 clears this bit. The abort condition of the IDMAC depends on the setting of this CES bit.
If the CES bit is enabled, then the IDMAC aborts on a response error. (R/W)

IDSTS_DU Descriptor Unavailable Interrupt. This bit is set when the descriptor is unavailable due to
OWN bit = 0 (DES0[31] =0). Writing 1 clears this bit. (R/W)

IDSTS_FBE Fatal Bus Error Interrupt. Indicates that a Bus Error occurred (IDSTS[12:10]) . When this
bit is set, the DMA disables all its bus accesses. Writing 1 clears this bit. (R/W)

IDSTS_RI Receive Interrupt. Indicates the completion of data reception for a descriptor. Writing 1
clears this bit. (R/W)

IDSTS_TI Transmit Interrupt. Indicates that data transmission is finished for a descriptor. Writing 1
clears this bit. (R/W)

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Register 9.31: IDINTEN_REG (0x0090)

se _ S

IN _ E
ID rve DU
(re TEN CE

ID TEN FB
se NI

N_ I
TE AI

TI
TE R
d)

ID ed)

ID TE N )
IN _
(re N_

IN _

IN _
IN d
ID TEN

ID TEN
ve

rv
r
se

IN

IN
(re

ID
31 10 9 8 7 6 5 4 3 2 1 0

0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Reset

IDINTEN_AI Abnormal Interrupt Summary Enable. (R/W)

When set, an abnormal interrupt is enabled. This bit enables the following bits:
IDINTEN[2]: Fatal Bus Error Interrupt;
IDINTEN[4]: DU Interrupt.

IDINTEN_NI Normal Interrupt Summary Enable. (R/W)

When set, a normal interrupt is enabled. When reset, a normal interrupt is disabled. This bit enables
the following bits:
IDINTEN[0]: Transmit Interrupt;
IDINTEN[1]: Receive Interrupt.

IDINTEN_CES Card Error summary Interrupt Enable. When set, it enables the Card Interrupt sum-
mary. (R/W)

IDINTEN_DU Descriptor Unavailable Interrupt. When set along with Abnormal Interrupt Summary
Enable, the DU interrupt is enabled. (R/W)

IDINTEN_FBE Fatal Bus Error Enable. When set with Abnormal Interrupt Summary Enable, the Fatal
Bus Error Interrupt is enabled. When reset, Fatal Bus Error Enable Interrupt is disabled. (R/W)

IDINTEN_RI Receive Interrupt Enable. When set with Normal Interrupt Summary Enable, Receive
Interrupt is enabled. When reset, Receive Interrupt is disabled. (R/W)

IDINTEN_TI Transmit Interrupt Enable. When set with Normal Interrupt Summary Enable, Transmit
Interrupt is enabled. When reset, Transmit Interrupt is disabled. (R/W)

Register 9.32: DSCADDR_REG (0x0094)

31 0

0x000000000 Reset

DSCADDR_REG Host Descriptor Address Pointer, updated by IDMAC during operation and cleared
on reset. This register points to the start address of the current descriptor read by the IDMAC.
(RO)

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9. SD/MMC Host Controller

Register 9.33: BUFADDR_REG (0x0098)

31 0

0x000000000 Reset

BUFADDR_REG Host Buffer Address Pointer, updated by IDMAC during operation and cleared on
reset. This register points to the current Data Buffer Address being accessed by the IDMAC. (RO)

Register 9.34: CLK_EDGE_SEL (0x0800)

L
L

SE
SE

_S

V_
F_

DR
SA
SL
N

H
L
E_

E_

E_

E_

E_

E_
G

DG

DG

G
D

D
_E

_E

_E

_E

_E

_E
d)

IN

IN

IN

IN

IN

IN
ve

LK

LK

LK

LK

LK

LK
r
se

CC

CC

CC

CC

CC

CC
(re

31 21 20 17 16 13 12 9 8 6 5 3 2 0

0x000 0x1 0x0 0x1 0x0 0x0 0x0 Reset

CCLKIN_EDGE_N This value should be equal to CCLKIN_EDGE_L. (R/W)

CCLKIN_EDGE_L The low level of the divider clock. The value should be larger than
CCLKIN_EDGE_H. (R/W)

CCLKIN_EDGE_H The high level of the divider clock. The value should be smaller than
CCLKIN_EDGE_L. (R/W)

CCLKIN_EDGE_SLF_SEL It is used to select the clock phase of the internal signal from phase90,
phase180, or phase270. (R/W)

CCLKIN_EDGE_SAM_SEL It is used to select the clock phase of the input signal from phase90,
phase180, or phase270. (R/W)

CCLKIN_EDGE_DRV_SEL It is used to select the clock phase of the output signal from phase90,
phase180, or phase270. (R/W)

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10. Ethernet MAC

10.1 Overview
Features of Ethernet

By using the external Ethernet PHY (physical layer), ESP32 can send and receive data via Ethernet MAC (Media
Access Controller) according to the IEEE 802.3 standard, as Figure 41 shows. Ethernet is currently the most
commonly used network protocol that controls how data is transmitted over local- and wide-area networks,
abbreviated as LAN and WAN, respectively.

Figure 41: Ethernet MAC Functionality Overview

ESP32 MAC Ethernet complies with the following criteria:

• IEEE 802.3-2002 for Ethernet MAC

• IEEE 1588-2008 standard for specifying the accuracy of networked clock synchronization

• Two industry-standard interfaces conforming with IEEE 802.3-2002: Media-Independent Interface (MII) and
Reduced Media-Independent Interface (RMII).

Features of MAC Layer

• Support for a data transmission rate of 10 Mbit/s or 100 Mbit/s through an external PHY interface

• Communication with an external Fast Ethernet PHY through IEEE 802.3-compliant MII and RMII interfaces

• Support for:

– Carrier Sense Multiple Access / Collision Detection (CSMA/CD) protocol in half-duplex mode

– IEEE 802.3x flow control in full-duplex mode

– operations in full-duplex mode, forwarding the received pause-control frame to the user application

– backpressure flow control in half-duplex mode

– If the flow control input signal disappears during a full-duplex operation, a pause frame with zero
pause time value is automatically transmitted.

• The Preamble and the Start Frame Delimiter (SFD) are inserted in the Transmit path, and deleted in the
Receive path.

• Cyclic Redundancy Check (CRC) and Pad can be controlled on a per-frame basis.

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10. Ethernet MAC

• The Pad is generated automatically, if data is below the minimum frame length.

• Programmable frame length supporting jumbo frames of up to 16 KB

• Programmable Inter-frame Gap (IFG) (40-96 bit times in steps of 8)

• Support for a variety of flexible address filtering modes:

– Up to eight 48-bit perfect address filters to mask each byte

– Up to eight 48-bit SA address comparison checks to mask each byte

– All multicast address frames can be transmitted

– All frames in mixed mode can be transmitted without being filtered for network monitoring

– A status report is attached each time all incoming packets are transmitted and filtered

• Returning a 32-bit status for transmission and reception of packets respectively

• Separate transmission, reception, and control interfaces for the application

• Use of the Management Data Input/Output (MDIO) interface to configure and manage PHY devices

• Support for the offloading of received IPv4 and TCP packets encapsulated by an Ethernet frame in the
reception function

• Support for checking IPv4 header checksums, as well as TCP, UDP, or ICMP (Internet Control Message
Protocol) checksums encapsulated in IPv4/IPv6 packets in the enhanced reception function

• Support for Ethernet frame timestamps. (For details please refer to IEEE 1588-2008.) Each frame has a
64-bit timestamp when transmitted or received.

• Two sets of FIFOs: one 2 KB Tx FIFO with programmable threshold and one 2 KB Rx FIFO with
configurable threshold (64 bytes by default)

• When Rx FIFO stores multiple frames, the Receive Status Vector is inserted into the Rx FIFO after
transmitting an EOF (end of frame), so that the Rx FIFO does not need to store the Receive Status of these
frames.

• In store-and-forward mode, all error frames can be filtered during reception, but not forwarded to the
application.

• Under-sized good frames can be forwarded.

• Support for data statistics by generating pulses for lost or corrupted frames in the Rx FIFO due to an
overflow

• Support for store-and-forward mechanism when transmitting data to the MAC core

• Automatic re-transmission of collided frames during transmission (subject to certain conditions, see section
10.2.1.2)

• Discarding frames in cases of late collisions, excessive collisions, excessive deferrals, and under-run
conditions

• The Tx FIFO is flushed by software control.

• Calculating the IPv4 header checksum, as well as the TCP, UDP, or ICMP checksum, and then inserting
them into frames transmitted in store-and-forward mode.

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Figure 42: Ethernet Block Diagram

Ethernet Block Diagram

Figure 42 shows the block diagram of the Ethernet.

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10. Ethernet MAC

Ethernet MAC consists of the MAC-layer configuration register module and three layers: EMAC_CORE (MAC
Core Layer), EMAC_MTL (MAC Transition Layer), and EMAC_DMA (Direct Memory Access). Each of these three
layers has two directions: Tx and Rx. They are connected to the system through the Advanced
High-Performance Bus (AHB) and the Advanced Peripheral Bus (APB) on the chip. Off the chip, they
communicate with the external PHY through the MII and RMII interfaces to establish an Ethernet
connection.

10.2 EMAC_CORE
The MAC supports many interfaces with the PHY chip. The PHY interface can be selected only once after reset.
The MAC communicates with the application side (DMA side), using the MAC Transmit Interface (MTI), MAC
Receive Interface (MRI) and the MAC Control Interface (MCI).

10.2.1 Transmit Operation

A transmit operation is initiated when the MTL Application pushes in data at the time a response signal is
asserted. When the SOF (start of frame) signal is detected, the MAC accepts the data and begins transmitting to
the RMII or MII. The time required to transmit the frame data to the RMII or MII, after the application initiates
transmission, varies, depending on delay factors like IFG delay, time to transmit Preamble or SFD (Start Frame
Delimiter), and any back-off delays in half-duplex mode. Until then, the MAC does not accept the data received
from MTL by de-asserting the ready signal.

After the EOF (end of frame) is transmitted to the MAC, the MAC completes the normal transmission and yields
the Transmit Status to the MTL. If a normal collision (in half-duplex mode) occurs during transmission, the MAC
makes valid the Transmit Status in the MTL. It then accepts and drops all further data until the next SOF is
received. The MTL block should retransmit the same frame from SOF upon observing a retry request (in the
Status) from the MAC.

The MAC issues an underflow status if the MTL is not able to provide the data continuously during transmission.
During the normal transmission of a frame from MTL, if the MAC receives an SOF without getting an EOF for the
previous frame, it ignores the SOF and considers the new frame as a continuation of the previous one.

10.2.1.1 Transmit Flow Control

In full-duplex mode, when the Transmit Flow Control Enable bit (TFE bit in the Flow Control Register) is set to 1,
the MAC will generate and send a pause frame, as needed. The pause frame is added and transmitted together
with the calculated CRC. The generation of pause frames can be initiated in two ways.

When the application sets the Flow Control Busy bit (FCB bit in the Flow Control Register) to 1, or when the Rx
FIFO is full, a pause frame is transmitted.

• If an application has requested flow control by setting the FCB bit in the Flow Control Register to 1, the MAC
will generate and send a single pause frame. The pause time value in the generated frame is the pause time
value programmed in the Flow Control Register. To extend or end the pause time before the time specified
in the previously transmitted pause frame, the application program must configure the pause time value in
the Flow Control Register to the appropriate value and, then, request another pause frame transmission.

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10. Ethernet MAC

• If the application has requested flow control when the Rx FIFO is full, the MAC will generate and transmit a
pause frame. The value of the pause time of the generated frame is the pause time value programmed in
the Flow Control Register. If the Rx FIFO remains full during the configurable interval, which is determined
by the Pause Low Threshold bit (PLT) in the Flow Control Register before the pause time expires, a second
pause frame will be transmitted. As long as the Rx FIFO remains full, the process repeats itself. If the FIFO
is no longer full before the sample time, the MAC will send a pause frame with zero pause time, indicating
to the remote end that the Rx buffer is ready to receive the new data frame.

10.2.1.2 Retransmission During a Collision

In half-duplex mode, a collision may occur on the MAC line interface when frames are transmitted to the MAC.
The MAC may even give a status to indicate a retry before the end of the frame is received. The retransmission is
then enabled and the frame is popped out from the FIFO. When more than 96 bytes are transmitted to the MAC
core, the FIFO controller frees the space in the FIFO, allowing the DMA to push more data into FIFO. This means
that data cannot be retransmitted after the threshold is exceeded or when the MAC core indicates that a late
collision has occurred.

The MAC transmitter may abort the transmission of a frame because of collision, Tx FIFO underflow, loss of
carrier, jabber timeout, no carrier, excessive deferral, and late collision. When frame transmission is aborted
because of collision, the MAC requests retransmission of the frame.

10.2.2 Receive Operation

A receive operation is initiated when the MAC detects an SFD on the RMII or MII. The MAC strips the Preamble
and SFD before processing the frame. The header fields are checked for the filtering and the FCS (Frame Check
Sequence) field used to verify the CRC for the frame. The received frame is stored in a shallow buffer until the
address filtering is performed. The frame is dropped in the MAC if it fails the address filtering.

The frame received by the MAC will be pushed into the Rx FIFO. Once the FIFO status exceeds the Receive
Threshold, configured by the Receive Threshold Control (RTC) bit in the Operation Mode register, the DMA can
initiate a preconfigured burst transmission to the AHB interface.

In the default pass-through mode, when the FIFO receives a complete packet or 64 bytes configured by the RTC
bit in the Operation Mode Register, the data pops up and its availability is notified to the DMA. After the DMA
initiates the transmission to the AHB interface, the data transmission continues from the FIFO until the complete
packet is transmitted. Upon completing transmitting the EOF, the status word will pop up and be transmitted to
the DMA controller.

In the Rx FIFO Store-and-Forward mode (configured through the RSF or Receive Store and Forward bit in the
Operation Mode Register), only the valid frames are read and forwarded to the application. In the passthrough
mode, error frames are not discarded because the error status is received at the end of the frame. The start of
frame will have been read from the FIFO at that point.

10.2.2.1 Reception Protocol

After the receive module receives the packets, the Preamble and SFD of the received frames are removed. When
the SFD is detected, the MAC starts sending Ethernet frame data to the Rx FIFO, starting at the first byte

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10. Ethernet MAC

(destination address) following the SFD. This timestamp is passed on to the application, unless the MAC filters
out and drops the frame.

If the received frame length/type is less than 0x600 and the automatic CRC/Pad removal option is programmed
for the MAC, the MAC will send frame data to the Rx FIFO (the amount of data does not exceed the number
specified in the length/type field). Then MAC begins discarding the remaining section, including the FCS field. If
the frame length/type is greater than, or equal to, 0x600, the MAC will send all received Ethernet frame data to
the Rx FIFO, regardless of the programmed value of the automatic CRC removal option. By default, the MAC
watchdog timer is enabled, meaning that frames, including DA, SA, LT, data, pad and FCS, which exceed 2048
bytes, are cut off. This function can be disabled by programming the Watchdog Disable (WD) bit in the MAC
Configuration Register. However, even if the watchdog timer is disabled, frames longer than 16 KB will be cut off
and the watchdog timeout status will be given.

10.2.2.2 Receive Frame Controller

If the RA (Receive All) bit in the MAC Frame Filter Register is reset, the MAC will filter frames based on the
destination and source addresses. If the application decides not to receive any bad frames, such as runt frames
and CRC error frames, another level of filtering is needed. When a frame fails the filtering, the frame is discarded
and is not transmitted to the application. When the filter parameters are changed dynamically, if a frame fails the
DA and SA filterings, the remaining part of the frame is discarded and the Receive Status word is updated
immediately and, therefore, the zero frame length bit, CRC error bit, and runt frame error bit are set to 1. This
indicates that the frame has failed the filtering.

10.2.2.3 Receive Flow Control

The MAC will detect the received pause frame and pause transmission of frames for a specified delay within the
received pause frame (in full-duplex mode only). The Pause Frame Detect Function can be enabled or disabled
by the RFCE (Receive Flow Control Enable) bit in the Flow Control Register. When receive flow control is enabled,
it starts monitoring whether the destination address of the received frame matches the multicast address of the
control frame (0x0180 C200 0001). If a match is detected (i.e. the destination address of the received frame
matches the destination address of the reserved control frame), the MAC will determine whether to transmit the
received control frame to the application, according to the PCF (Pass Control Frames) bit in the Frame Filter
Register.

The MAC will also decode the type, the opcode, and the pause timer field of the Receive Control Frame. If the
value of the status byte counter is 64 bits and there are no CRC errors, the MAC transmitter will halt the
transmission of any data frame. The duration of the pause is the decoded pause time value multiplied by the
interval (which is 64 bytes for both 10 Mbit/s and 100 Mb/s modes). At the same time, if another pause frame of
zero pause time is detected, the MAC will reset the pause time to manage the new pause request.

If the type field (0x8808), the opcode (0x00001), and the byte length (64 bytes) of the received control frame are
not 0x8808, 0x00001, and 64 bytes, respectively, or if there is a CRC error, the MAC will not generate a
pause.

If a pause frame has a multicast destination address, the MAC filters the frame, according to the address
matching.

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For pause frames with a unicast destination address, the MAC checks whether the DA matches the content of
the EMACADDR0 Register, and whether the Unicast Pause Frame Detect (UPFD) bit in the Flow Control Register
is set to 1. The Pass Control Frames (PCF) bits in the Frame Filter Register [7:6] control the filtering of frames and
addresses.

10.2.2.4 Reception of Multiple Frames

Since the status is available immediately after the data is received. Frames can be stored there, as long as the
FIFO is not full.

10.2.2.5 Error Handling

If the Rx FIFO is full before receiving the EOF data from the MAC, an overflow will be generated and the entire
frame will be discarded. In fact, status bit RDES0[11] will indicate that this frame is partial due to an overflow, and
that it should be discarded.

If the function that corresponds to the Flush Transmit FIFO (FTF) bit and the Forward Undersized Good Frames
(FUGF) bit in the Operation Mode Register is enabled, the Rx FIFO can filter error frames and runt frames. If the
receive FIFO is configured to operate in store-and-forward mode, all error frames will be filtered and
discarded.

In passthrough mode, if a frame’s status and length are available when reading a SOF from the Rx FIFO, the
entire error frame can be discarded. DMA can clear the error frame being read from the FIFO by enabling the
Receive Frame Clear bit. The data transmission to the application (DMA) will then stop, and the remaining frames
will be read internally and discarded. If FIFO is available, the transmission of the next frame will be initiated.

10.2.2.6 Receive Status Word

After receiving the Ethernet frames, the MAC outputs the receive status to the application. The detailed
description of the receive status is the same as that which is configured by bit [31:0] in RDES0.

10.3 MAC Interrupt Controller

The MAC core can generate interrupts due to various events.

The interrupt register bits only indicate various interrupt events. To clear the interrupts, the corresponding status
register and other registers must be read. An Interrupt Status Register describes the events that prompt the MAC
core to generate interrupts. Each interrupt event can be prevented by setting the corresponding mask bit in the
Interrupt Mask Register to 1. For example, if bit3 of the interrupt register is set high, it indicates that a magic
packet or Wake-on-LAN frame has been received in Power-down mode. The PMT Control and Status register
must be read to clear this interrupt event.

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10. Ethernet MAC

10.4 MAC Address Filtering

Address filtering will check the destination and source addresses of all received frames and report the address
filtering status accordingly. For example, filtered frames can be identified either as multicast or broadcast.The
address check, then, is based on the parameters selected by the application (Frame Filter Registers).

Physical (MAC) addresses are used for address checking during address filtering.

10.4.1 Unicast Destination Address Filtering

The MAC supports up to 8 MAC addresses for perfect filtering of unicast addresses. If a perfect filtering is
selected (by resetting bit[1] in the Frame Filter Register), the MAC compares all 48 bits of the received unicast
address with the programmed MAC address to determine if there is a match. By default, EMACADDR0 is always
enabled, and the other addresses (EMACADDR0 ~ EMACADDR7) are selected by a separate enable bit. When
the individual bytes of the other addresses (EMACADDR0 ~ EMACADDR7) are compared with the DA bytes
received, the latter can be masked by setting the corresponding Mask Byte Control bit in the register to 1. This
facilitates the DA group address filtering.

10.4.2 Multicast Destination Address Filtering

The MAC can be programmed to pass all multicast frames by setting the Pass All Multicast (PAM) bit in the
Frame Filter Register to 1. If the PAM bit is reset, the MAC will filter multicast addresses, according to Bit[2] in the
Frame Filter Register.

In perfect filtering mode, the multicast address is compared with the programmed MAC Destination Address
Registers (EMACADDR0 ~ EMACADDR7). Group address filtering is also supported.

10.4.3 Broadcast Address Filtering

The MAC does not filter any broadcast frames in the default mode. However, if the MAC is programmed to reject
all broadcast frames, which can happen by setting the Disable Broadcast Frames (DBF) bit in the Frame Filter
Register to 1, all broadcast frames will be discarded.

10.4.4 Unicast Source Address Filtering

The MAC may also perform a perfect filtering based on the source address field of the received frame. By default,
the Address Filtering Module (AFM) compares the Source Address (SA) field with the values programmed in the
SA register. By setting Bit[30] in the SA register to 1, the MAC Address Register (EMACADDR0 - EMACADDR7)
can be configured to contain SA, instead of Destination Address (DA), for filtering. Group filtering with SA is also
supported. If the Source Address Filter (SAF) enable bit in the Frame Filter Register is set to 1, the MAC discards
frames that do not pass the SA filtering. Otherwise, the result of SA filtering is given as a status bit in the Receive
Status word (Please refer to Table 47).

When the SAF enable bit is set to 1, the result of the SA filtering and DA filtering is AND’ed to determine whether
or not to forward the frame. Any frame that fails to pass will be discarded. Frames need to pass both filterings in
order to be forwarded to the application.

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10.4.5 Inverse Filtering Operation

For both destination address (DA) and source address (SA) filtering, you can invert the results matched through
the filtering at the final output. The inverse filtering of DA and SA are controlled by the DAIF and SAIF bits,
respectively, in the Frame Filter Register. The DAIF bit applies to both unicast and multicast DA frames. When
DAIF is set to 1, the result of unicast or multicast destination address filtering will be inverted. Similarly, when the
SAIF bit is set to 1, the result of unicast SA filtering is reversed.

The following two tables summarize the destination address and source address filtering, based on the type of
the frames received.

Table 39: Destination Address Filtering

Frame Type PM PF DAIF PAM DB DA Filter Result

1 X X X X Pass
Broadcast 0 X X X 0 Pass
0 X X X 1 Fail
1 X X X X All frames pass.
0 X 0 X X Pass when results of perfect/group filtering match.
Unicast 0 X 1 X X Fail when results of perfect/group filtering match.
0 1 0 X X Pass when results of perfect/group filtering match.
0 1 1 X X Fail when results of perfect/group filtering match.
1 X X X X All frames pass.
X X X 1 X All frames pass.
Pass when results of perfect/group filtering match and
0 X 0 0 X
pause control frame is discarded, if PCF = 0x.
Pass when results of perfect/group filtering match and
Multicast 0 1 0 0 X
pause control frame is discarded, if PCF = 0x.
Fail when results of perfect/group filtering match and
0 X 1 0 X
pause control frame is discarded, if PCF = 0x.
Fail when results of perfect/group filtering match and
0 1 1 0 X
pause control frame is discarded, if PCF = 0x.

The filtering parameters in the MAC Frame Filter Register described in Table 39 are as follows.
Parameter name: Parameter setting:
PM: Pass All Multicast 1: Set
PF: Perfect Filter 0: Cleared
DAIF: Destination Address Inverse Filtering
PAM: Pass All Multicast
DB: Disable Broadcast Frames

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Table 40: Source Address Filtering

Frame Type PM SAIF SAF Source Address Filter Operation

1 X X Pass all frames
Pass when results of perfect/group filtering match. Frames not passed are
0 0 0
not discarded.
Fail when results of perfect/group filtering match. Frames not passed are
0 1 0
Unicast not discarded.
Pass when results of perfect/group filtering match. Frames not passed are
0 0 1
discarded.
Fail when results of perfect/group filtering match. Frames not passed are
0 1 1
discarded.

The filtering parameters in the MAC Frame Filter Register described in Table 40 are as follows.
Parameter name: Parameter setting:
PM: Pass All Multicast 1: Set
SAF: Source Address Filtering 0: Cleared
SAIF: Source Address Inverse Filtering X: Don’t care

10.4.6 Good Transmitted Frames and Received Frames

A frame successfully transmitted is considered a ”good frame”. In other words, a transmitted frame is considered
to be good, if the frame transmission is not aborted due to the following errors:

• Jabber timeout

• No carrier or loss of carrier

• Late collision

• Frame underflow

• Excessive deferral

• Excessive collision

The received frames are considered ”good frames”, if there are not any of the following errors:

• CRC error

• Runt frames (frames shorter than 64 bytes)

• Alignment error (in 10/100 Mbps modes only)

• Length error (non-type frames only)

• Frame size over the maximum size (for non-type frames over the maximum frame size only)�

• MII_RXER input error

The maximum frame size depends on the frame type:

• The maximum size of untagged frames = 1518 bytes

• The maximum size of VLAN frames = 1522 bytes

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10.5 EMAC_MTL (MAC Transaction Layer)

The MAC Transaction Layer provides FIFO memory to buffer and regulates the frames between the application
system memory and the MAC. It also enables the data to be transmitted between the application clock domain
and the MAC clock domains. The MTL layer has two data paths, namely the Transmit path and the Receive path.
The data path for both directions is 32-bit wide and operates with a simple FIFO protocol.

10.6 PHY Interface

The DMA and the Host driver communicate through two data structures:

• Control and Status Registers (CSR)

• Descriptor lists and data buffers

For details please refer to Register Summary and Linked List Descriptors.

10.6.1 MII (Media Independent Interface)

Media Independent Interface (MII) defines the interconnection between MAC sublayers and PHYs at the data
transmission rate of 10 Mbit/s and 100 Mbit/s.

10.6.1.1 Interface Signals Between MII and PHY

Interface signals between MII and PHY are shown in Figure 43.

Figure 43: MII Interface

MII Interface Signal Description:

• MII_TX_CLK: TX clock signal. This signal provides the reference timing for TX data transmission. The
frequencies are divided into two types: 2.5 MHz at a data transmission rate of 10 Mbit/s, and 25 MHz at
100 Mbit/s.

• MII_TXD[3:0]: Transmit data signal in groups of four, syn-driven by the MAC sub-layer, and valid only when
the MII_TX_EN signal is valid. MII_TXD[0] is the lowest significant bit and MII_TXD[3] is the highest
significant bit. When the signal MII_TX_EN is pulled low, sending data does not have any effect on the PHY.

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• MII_TX_EN: Transmit data enable signal. This signal indicates that the MAC is currently sending nibbles (4
bits) for the MII. This signal must be synchronized with the first nibble of the header (MII_TX_CLK) and must
be synchronized when all nibbles to be transmitted are sent to the MII.

• MII_RX_CLK: RX clock signal. This signal provides the reference timing for RX data transmission. The
frequencies are divided into two types: 2.5 MHz at the data transmission rate of 10 Mbit/s, and 25 MHz at
100 Mbit/s.

• MII_RXD[3:0]: Receive data signal in groups of four, syn-driven by the PHY, and valid only when MII_RX_DV
signal is valid. MII_RXD[0] is the lowest significant bit and MII_RXD[3] is the highest significant bit. When
MII_RX_DV is disabled and MII_RX_ER is enabled, the specific MII_RXD[3:0] value represents specific
information from the PHY.

• MII_RX_DV: Receive data valid signal. This signal indicates that the PHY is currently receiving the recovered
and decoded nibble that will be transmitted to the MII. This signal must be synchronized with the first nibble
of the recovered frame (MII_RX_CLK) and remain synchronized till the last nibble of the recovered frame.
This signal must be disabled before the first clock cycle following the last nibble. In order to receive the
frame correctly, the MII_RX_DV signal must cover the frame to be received over the time range, starting no
later than when the SFD field appears.

• MII_CRS: Carrier sense signal. When the transmitting or receiving medium is in the non-idle state, the
signal is enabled by the PHY. When the transmitting or receiving medium is in the idle state, the signal is
disabled by the PHY. The PHY must ensure that the MII_CRS signal remains valid under conflicting
conditions. This signal does not need to be synchronized with the TX and RX clocks. In full-duplex mode,
this signal is insignificant.

• MII_COL: Collision detection signal. After a collision is detected on the medium, the PHY must immediately
enable the collision detection signal, and the collision detection signal must remain active as long as a
condition for collision exists. This signal does not need to be synchronized with the TX and RX clocks. In
full-duplex mode, this signal is meaningless.

• MII_RX_ER: Receive error signal. The signal must remain for one or more cycles (MII_RX_CLK) to indicate
to the MAC sublayer that an error has been detected somewhere in the frame.

• MDIO and MDC: Management Data Input/Output and Management Data Clock. The two signals constitute
a serial bus defined for the Ethernet family of IEEE 802.3 standards, used to transfer control and data
information to the PHY, see section Station Management Agent (SMA) Interface.

10.6.1.2 MII Clock

In MII mode, there are two directions of clock, Tx and Rx clocks in the interface between MII and the PHY.
MII_TX_CLK is used to synchronize the TX data, and MII_RX_CLK is used to synchronize the RX data. The
MII_RX_CLK clock is provided by the PHY. The MII_TX_CLK is provided by the chip’s internal PLL or external
crystal oscillator. For details regarding Figure 44, please refer to the clock-related registers in Register
Summary.

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10. Ethernet MAC

Figure 44: MII Clock

10.6.2 RMII (Reduced Media-Independent Interface)

RMII interface signals are shown in figure 45.

Figure 45: RMII Interface

10.6.2.1 RMII Interface Signal Description

The Reduced Media-Independent Interface (RMII) specification reduces the number of pins between the
microcontroller’s external peripherals and the external PHY at a data transmission rate of 10 Mbit/s or 100 Mbit/s.
According to the IEEE 802.3u standard, MII includes 16 pins that contain data and control signals. The RMII
specification reduces 62.5% of the pins to the number of seven.

RMII has the following features:

• Support for an operating rate of 10 Mbit/s or 100 Mbit/s

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10. Ethernet MAC

• The reference clock frequency must be 50 MHz.

• The same reference clock must be provided externally both to the MAC and the external Ethernet PHY. It
provides independent 2-bit-wide Tx and Rx data paths.

10.6.2.2 RMII Clock

The configuration of the RMII clock is as figure 46 shows.

Figure 46: RMII Clock

10.6.3 Station Management Agent (SMA) Interface

As Figure 44 shows, the MAC uses MDC and MDIO signals to transfer control and data information to the PHY.
The maximum clock frequency is 2.5 MHz. The clock is generated from the application clock by a clock divider.
The PHY transmits register data during a write/read operation through the MDIO. This signal is driven
synchronously to the MDC clock.

Please refer to Register Summary for details about the EMII Address Register and the EMII Data Register.

10.7 Ethernet DMA Features

The DMA has independent Transmit and Receive engines, and a CSR (Control and Status Registers) space. The
Transmit engine transfers data from the system memory to the device port (MTL), while the Receive engine
transmits data from the device port to the system memory. The controller uses descriptors to efficiently move
data from source to destination with minimal Host CPU intervention. The DMA is designed for packet-oriented
data transmission, such as frames in Ethernet. The controller can be programmed to interrupt the Host CPU for
normal situations, such as the completion of frame transmission or reception, or when errors occur.

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10.8 Linked List Descriptors

This section shows the structure of the linked lists and the descriptors. Every linked list consists of eight
words.

10.8.1 Transmit Descriptors

The structure of the transmitter linked lists is shown in Figure 47. Table 41 to Table 46 show the description of the
linked lists.
31 0
Ctrl/status Status

TTSS
OWN

TTSE
TDES0 Ctrl[30:26] Ctrl[24:18] Status[16:7]
[6:3] [2:0]
Ctrl
TDES1 Reserved Transmit Buffer Size[12:0]
[31:29]
TDES2 Buffer Address [31:0]
TDES3 Next Descriptor Address[31:0]
TDES4 Reserved
TDES5 Reserved
TDES6 Transmit Frame Timestamp Low[31:0]
TDES7 Transmit Frame Timestamp High[31:0]

Figure 47: Transmit Descriptor

Table 41: Transmit Descriptor 0 (TDES0)

Bits Name Description

When set, this bit indicates that the descriptor is owned by the DMA.
When this bit is reset, it indicates that the descriptor is owned by the
Host. The DMA clears this bit, either when it completes the frame
transmission or when the buffers allocated to the descriptor are
[31] OWN: Own Bit
empty. The ownership bit of the First Descriptor of the frame should
be set after all subsequent descriptors belonging to the same frame
have been set. This avoids a possible race condition between fetch-
ing a descriptor and the driver setting an ownership bit.
When set, this bit sets the Transmit Interrupt (Register 5[0]) after the
[30] IC: Interrupt on Completion present frame has been transmitted. This bit is valid only when the
last segment bit (TDES0[29]) is set.
When set, this bit indicates that the buffer contains the last segment
[29] LS: Last Segment of the frame. When this bit is set, the TBS1 or TBS2 field in TDES1
should have a non-zero value.
When set, this bit indicates that the buffer contains the first segment
[28] FS: First Segment
of a frame.
When this bit is set, the MAC does not append a cyclic redundancy
[27] DC: Disable CRC check (CRC) to the end of the transmitted frame. This is valid only
when the first segment (TDES0[28]) is set.

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Bits Name Description

When set, the MAC does not automatically add padding to a frame
shorter than 64 bytes. When this bit is reset, the DMA automatically
[26] DP: Disable Pad adds padding and CRC to a frame shorter than 64 bytes, and the
CRC field is added despite the state of the DC (TDES0[27]) bit. This
is valid only when the first segment (TDES0[28]) is set.
When set, this bit enables IEEE1588 hardware timestamping for the
TTSE: Transmit Timestamp
[25] transmit frame referenced by the descriptor. This field is valid only
Enable
when the First Segment control bit (TDES0[28]) is set.
When set, the MAC replaces the last four bytes of the transmitted
packet with recalculated CRC bytes. The host should ensure that
CRCR: CRC Replacement the CRC bytes are present in the frame being transmitted from the
[24]
Control Transmit Buffer. This bit is valid when the First Segment control bit
(TDES0[28]) is set. In addition, CRC replacement is done only when
Bit TDES0[27] is set to 1.
These bits control the checksum calculation and insertion. The fol-
lowing list describes the bit encoding:
• 2’b00: Checksum insertion is disabled.
• 2’b01: Only IP header checksum calculation and insertion are
enabled.
• 2’b10: IP header checksum and payload checksum calcula-
CIC: Checksum Insertion
[23:22] tion and insertion are enabled, but pseudo-header checksum
Control
is not calculated in hardware.
• 2’b11: IP Header checksum and payload checksum calcula-
tion and insertion are enabled, and pseudo-header checksum
is calculated in hardware.
This field is valid when the First Segment control bit (TDES0[28]) is
set.
When set, this bit indicates that the descriptor list reached its final
[21] TER: Transmit End of Ring descriptor. The DMA returns to the base address of the list, creating
a Descriptor Ring.
When set, this bit indicates that the second address in the descrip-
tor is the Next Descriptor address, rather than the second buffer
TCH: Second Address
[20] address. When TDES0[20] is set, TBS2 (TDES1[28:16]) is a “don’t
Chained
care” value. TDES0[21] takes precedence over TDES0[20]. This bit
should be set to 1.

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Bits Name Description

When set, these bits request the MAC to perform VLAN tagging or
untagging before transmitting the frames. If the frame is modified
for VLAN tags, the MAC automatically recalculates and replaces the
CRC bytes. The following list describes the values of these bits:
• 2’b00: Do not add a VLAN tag.
• 2’b01: Remove the VLAN tag from the frames before trans-
VLIC: VLAN Insertion
[19:18] mission. This option should be used only with the VLAN
Control
frames.
• 2’b10: Insert a VLAN tag with the tag value programmed in
VLAN Tag Inclusion or Replacement Register.
• 2’b1: Replace the VLAN tag in frames with the Tag value
programmed in VLAN Tag Inclusion or Replacement Regis-
ter. This option should be used only with the VLAN frames.
This field is used as a status bit to indicate that a timestamp was
captured for the described transmit frame. When this bit is set,
TTSS: Transmit
[17] TDES2 and TDES3 have a timestamp value captured for the trans-
Timestamp Status
mit frame. This field is only valid when the descriptor’s Last Segment
control bit (TDES0[29]) is set.
When set, this bit indicates that the MAC transmitter detected an
error in the IP datagram header. The transmitter checks the header
length in the IPv4 packet against the number of header bytes re-
ceived from the application, and indicates an error status if there
is a mismatch. For IPv6 frames, a header error is reported if the
[16] IHE: IP Header Error
main header length is not 40 bytes. Furthermore, the Ethernet
Length/Type field value for an IPv4 or IPv6 frame must match the IP
header version received with the packet. For IPv4 frames, an error
status is also indicated if the Header Length field has a value less
than 0x5.
Indicates the logical OR of the following bits:
• TDES0[14]: Jabber Timeout
• TDES0[13]: Frame Flush
• TDES0[11]: Loss of Carrier
• TDES0[10]: No Carrier
[15] ES: Error Summary • TDES0[9]: Late Collision
• TDES0[8]: Excessive Collision
• TDES0[2]: Excessive Deferral
• TDES0[1]: Underflow Error
• TDES0[16]: IP Header Error
• TDES0[12]: IP Payload Error
When set, this bit indicates the MAC transmitter has experienced a
[14] JT: Jabber Timeout jabber timeout. This bit is only set when EMACCONFIG_REG’s bit
EMACJABBER is not set.
When set, this bit indicates that the DMA or MTL flushed the frame
[13] FF: Frame Flushed
because of a software Flush command given by the CPU.

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Bits Name Description

When set, this bit indicates that MAC transmitter detected an error
in the TCP, UDP, or ICMP IP datagram payload.
The transmitter checks the payload length received in the IPv4 or
[12] IPE: IP Payload Error
IPv6 header against the actual number of TCP, UDP, or ICMP packet
bytes received from the application, and issues an error status in
case of a mismatch.
When set, this bit indicates that a loss of carrier occurred during
frame transmission (that is, the MII_CRS signal was inactive for one
[11] LOC: Loss of Carrier or more transmit clock periods during frame transmission). This is
valid only for the frames transmitted without collision when the MAC
operates in the half-duplex mode.
When set, this bit indicates that the Carrier Sense signal from the
[10] NC: No Carrier
PHY was not asserted during transmission.
When set, this bit indicates that frame transmission is aborted be-
cause of a collision occurring after the collision window (64 byte-
[9] LC: Late Collision times including Preamble in MII mode, and 512 byte-times including
Preamble and Carrier Extension). This bit is not valid if the Under-
flow Error bit is set.
When set, this bit indicates that the transmission was aborted after
16 successive collisions while attempting to transmit the current
[8] EC: Excessive Collision frame. If bit EMACRETRY of EMACCONFIG_REG is set, this bit
is set after the first collision, and the transmission of the frame is
aborted.
When set, this bit indicates that the transmitted frame is a VLAN-
[7] VF: VLAN Frame
type frame.
These status bits indicate the number of collisions that occurred
before the frame was transmitted. This count is not valid when the
[6:3] Ctrl/status
Excessive Collisions bit (TDES0[8]) is set. The core updates this
status field only in the half-duplex mode.
When set, this bit indicates that the transmission has ended be-
cause of excessive deferral of over 24,288 bit times (if Jumbo Frame
[2] ED: Excessive Deferral
is enabled) if bit EMACDEFERRAL of EMACCONFIG_REG is set
high.
When set, this bit indicates that the MAC aborted the frame be-
cause the data arrived late from the Host memory. Underflow Er-
ror indicates that the DMA encountered an empty transmit buffer
[1] UF: Underflow Error while transmitting the frame. The transmission process enters the
Suspended state and sets both Bit[5] in Transmit Underflow Regis-
ter (Status Register) and Bit[0] in Transmit Interrupt Register (Status
Register).
When set, this bit indicates that the MAC defers before transmission
[0] DB: Deferred Bit because of the presence of a carrier. This bit is valid only in the half-
duplex mode.

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Table 42: Transmit Descriptor 1 (TDES1)

Bits Name Description

These bits request the MAC to add or replace the Source Address
field in the Ethernet frame with the value given in the MAC Address
0 register. If the Source Address field is modified in a frame, the
MAC automatically recalculates and replaces the CRC bytes. The
Bit[31] specifies the MAC Address Register value (1 or 0) that is
used for Source Address insertion or replacement. The following
list describes the values of Bits[30:29]:
• 2’b00: Do not include the source address.
[31:29] SAIC: SA Insertion Control
• 2’b01: Include or insert the source address. For reliable trans-
mission, the application must provide frames without source
addresses.
• 2’b10: Replace the source address. For reliable transmission,
the application must provide frames with source addresses.
• 2’b11: Reserved
These bits are valid when the First Segment control bit (TDES0[28])
is set.
[28:16] Reserved Reserved
[15:13] Reserved Reserved
TBS1: Transmit Buffer 1 These bits indicate the data buffer byte size in bytes. If this field is 0,
[12:0]
Size the DMA ignores this buffer and uses Buffer 2 or the next descriptor.

Table 43: Transmit Descriptor 2 (TDES2)

Bits Name Description

[31:0] Buffer 1 Address Pointer These bits indicate the physical address of Buffer 1.

Table 44: Transmit Descriptor 3 (TDES3)

Bits Name Description

This address contains the pointer to the physical memory where the
[31:0] Next Descriptor Address
Next Descriptor is present.

Table 45: Transmit Descriptor 6 (TDES6)

Bits Name Description

This field is updated by DMA with the least significant 32 bits of the
TTSL: Transmit Frame timestamp captured for the corresponding transmit frame. This field
[31:0]
Timestamp Low has the timestamp only if the Last Segment (LS) bit in the descriptor
is set, and the Timestamp Status (TTSS) bit is set too.

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Table 46: Transmit Descriptor 7 (TDES7)

Bits Name Description

This field is updated by DMA with the most significant 32 bits of the
TTSH: Transmit Frame timestamp captured for the corresponding receive frame. This field
[31:0]
Timestamp High has the timestamp only if the Last Segment (LS) bit in the descriptor
is set, and the Timestamp Status (TTSS) bit is set too.

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10.8.2 Receive Descriptors

The structure of the receiver linked lists is shown in Figure 48. Table 47 to Table 53 provide the description of the
linked lists.
31 0
Ctrl OWN Status[30:0]
RDES0
Ctrl

Res
RDES1 Reserved[30:16] Receive Buffer 1 Size[12:0]
[15:14]
RDES2 Buffer1 Address [31:0]
RDES3 Next Descriptor Address[31:0]
RDES4 Extended Status[31:0]
RDES5 Reserved
RDES6 Receive Frame Timestamp Low[31:0]
RDES7 Receive Frame Timestamp High[31:0]

Figure 48: Receive Descriptor

Table 47: Receive Descriptor 0 (RDES0)

Bits Name Description

When set, this bit indicates that the descriptor is owned by the DMA
of the DWC_gmac. When this bit is reset, it indicates that the de-
[31] OWN: Own Bit scriptor is owned by the Host. The DMA clears this bit either when
it completes the frame reception or when the buffers that are asso-
ciated with this descriptor are full.
AFM: Destination Address When set, this bit indicates a frame that failed in the DA Filter in the
[30]
Filter Fail MAC.
These bits indicate the byte length of the received frame that was
transmitted to host memory. This field is valid when Last Descrip-
tor (RDES0[8]) is set and either the Descriptor Error (RDES0[14]) or
[29:16] FL: Frame Length Overflow Error bits is reset. The frame length also includes the two
bytes appended to the Ethernet frame when IP checksum calcula-
tion (Type 1) is enabled and the received frame is not a MAC control
frame.
Indicates the logical OR of the following bits:
• RDES0[1]: CRC Error
• RDES0[3]: Receive Error
• RDES0[4]: Watchdog Timeout
• RDES0[6]: Late Collision
[15] ES: Error Summary
• RDES0[7]: Giant Frame
• RDES4[4:3]: IP Header or Payload Error
• RDES0[11]: Overflow Error
• RDES0[14]: Descriptor Error
This field is valid only when the Last Descriptor (RDES0[8]) is set.

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Bits Name Description

When set, this bit indicates a frame truncation caused by a frame
that does not fit within the current descriptor buffers, and that the
[14] DE: Descriptor Error
DMA does not own the Next Descriptor. The frame is truncated.
This field is valid only when the Last Descriptor (RDES0[8]) is set.
SAF: Source Address Filter When set, this bit indicates that the SA field of frame failed the SA
[13]
Fail Filter in the MAC.
When set, this bit indicates that the actual length of the frame re-
[12] LE: Length Error ceived and that the Length/Type field does not match. This bit is
valid only when the Frame Type (RDES0[5]) bit is reset.
When set, this bit indicates that the received frame was damaged
[11] OE: Overflow Error
because of buffer overflow in MTL.
When set, this bit indicates that the frame to which this descriptor
is pointing is a VLAN frame tagged by the MAC. The VLAN tagging
[10] VLAN: VLAN Tag
depends on checking the VLAN fields of the received frame based
on the Register (VLAN Tag Register) settings.
When set, this bit indicates that this descriptor contains the first
buffer of the frame. If the size of the first buffer is 0, the second
[9] FS: First Descriptor buffer contains the beginning of the frame. If the size of the second
buffer is also 0, the next Descriptor contains the beginning of the
frame.
When set, this bit indicates that the buffers pointed to by this de-
[8] LS: Last Descriptor
scriptor are the last buffers of the frame.
When the Advanced Timestamp feature is present, and when this
bit set, it indicates that a snapshot of the Timestamp is written in
descriptor words 6 (RDES6) and 7 (RDES7). This is valid only when
the Last Descriptor bit (RDES0[8]) is set.
When IP Checksum Engine (Type 1) is selected, this bit, if set, indi-
cates one of the following:
Timestamp Available, • The 16-bit IPv4 header checksum calculated by the core did
[7] IP Checksum Error (Type1), not match the received checksum bytes.
or Giant Frame • The header checksum checking is bypassed for non-IPv4
frames.
Otherwise, this bit, when set, indicates the Giant Frame Status. Gi-
ant frames are larger than 1,518 bytes (or 1,522 bytes for VLAN or
2,000 bytes when Bit[27] of the MAC Configuration register is set),
normal frames and larger-than-9,018-byte (9,022-byte for VLAN)
frames when Jumbo Frame processing is enabled.
When set, this bit indicates that a late collision has occurred while
[6] LC: Late Collision
receiving the frame in the half-duplex mode.
When set, this bit indicates that the Receive Frame is an Ethernet-
type frame (the LT field is greater than, or equal to, 1,536). When
[5] FT: Frame Type
this bit is reset, it indicates that the received frame is an IEEE 802.3
frame. This bit is not valid for Runt frames which are less than 14
bytes.

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Bits Name Description

When set, this bit indicates that the Receive Watchdog Timer has
RWT: Receive
[4] expired while receiving the current frame and the current frame is
Watchdog Timeout
truncated after the Watchdog Timeout.
When set, this bit indicates that the MII_RXER signal is asserted
[3] RE: Receive Error
while MII_RXDV is asserted during frame reception.
When set, this bit indicates that the received frame has a non-
[2] DE: Dribble Bit Error integer multiple of bytes (odd nibbles). This bit is valid only in the
MII Mode.
When set, this bit indicates that a Cyclic Redundancy Check (CRC)
[1] CE: CRC Error Error occurred on the received frame. This field is valid only when
the Last Descriptor (RDES0[8]) is set.
When either Advanced Timestamp or IP Checksum Offload (Type
2) is present, this bit, when set, indicates that the extended status
is available in descriptor word 4 (RDES4). This is valid only when
the Last Descriptor bit (RDES0[8]) is set. This bit is invalid when Bit
30 is set.
When IP Checksum Offload (Type 2) is present, this bit is set even
Extended Status Available/
[0] when the IP Checksum Offload engine bypasses the processing of
Rx MAC Address
the received frame. The bypassing may be because of a non-IP
frame or an IP frame with a non-TCP/UDP/ICMP payload.
When the Advance Timestamp Feature or the IPC Full Offload is not
selected, this bit indicates an Rx MAC Address status. When set,
this bit indicates that the Rx MAC Address registers value (1 to 15)
matched the frame’s DA field. When reset, this bit indicates that the
Rx MAC Address Register 0 value matched the DA field.

Table 48: Receive Descriptor 1 (RDES1)

Bits Name Description

When set, this bit prevents setting the Status Register’s RI bit
(CSR5[6]) for the received frame that ends in the buffer indicated
[31] Ctrl
by this descriptor. This, in turn, disables the assertion of the inter-
rupt to Host because of the RI for that frame.
[30:29] Reserved Reserved
[28:16] Reserved Reserved
When set, this bit indicates that the descriptor list reached its final
[15] RER: Receive End of Ring descriptor. The DMA returns to the base address of the list, creating
a Descriptor Ring.
When set, this bit indicates that the second address in the descrip-
RCH: Second Address tor is the Next Descriptor address rather than the second buffer ad-
[14]
Chained dress. When this bit is set, RBS2 (RDES1[28:16]) is a “don’t care”
value. RDES1[15] takes precedence over RDES1[14].
[13] Reserved Reserved

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Bits Name Description

Indicates the first data buffer size in bytes. The buffer size must be a
multiple of 4, even if the value of RDES2 (buffer1 address pointer) is
RBS1: Receive Buffer 1 not aligned to bus width. When the buffer size is not a multiple of 4,
[12:0]
Size the resulting behavior is undefined. If this field is 0, the DMA ignores
this buffer and uses Buffer 2 or the next descriptor depending on
the value of RCH (Bit[14]).

Table 49: Receive Descriptor 2 (RDES2)

Bits Name Description

[31:0] Buffer 1 Address Pointer These bits indicate the physical address of Buffer 1.

Table 50: Receive Descriptor 3 (RDES3)

Bits Name Description

This address contains the pointer to the physical memory where the
[31:0] Next Descriptor Address
Next Descriptor is present.

Table 51: Receive Descriptor 4 (RDES4)

Bits Name Description

[31:28] Reserved Reserved
[27:26] Reserved Reserved
[25] Reserved Reserved
[24] Reserved Reserved
[23:21] Reserved Reserved
[20:18] Reserved Reserved
[17] Reserved Reserved
[16] Reserved Reserved
[15] Reserved Reserved
When set, this bit indicates that the timestamp was captured for this
[14] Timestamp Dropped
frame but got dropped in the MTL Rx FIFO because of an overflow.
When set, this bit indicates that the received PTP message is having
[13] PTP Version the IEEE 1588 version 2 format. When reset, it has the version 1
format.
When set, this bit indicates that the PTP message is sent directly
over the Ethernet. When this bit is not set and the message type is
[12] PTP Frame Type non-zero, it indicates that the PTP message is sent over UDP-IPv4
or UDP-IPv6. The information about IPv4 or IPv6 can be obtained
from Bits 6 and 7.

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Bits Name Description

These bits are encoded to give the type of the message received.
• 3’b0000: No PTP message received
• 3’b0001: SYNC (all clock types)
• 3’b0010: Follow_Up (all clock types)
• 3’b0011: Delay_Req (all clock types)
• 3’b0100: Delay_Resp (all clock types)
• 3’b0101: Pdelay_Req (in peer-to-peer transparent clock)
[11:8] Message Type
• 3’b0110: Pdelay_Resp (in peer-to-peer transparent clock)
• 3’b0111: Pdelay_Resp_Follow_Up (in peer-to-peer transpar-
ent clock)
• 3’b1000: Announce
• 3’b1001: Management
• 3’b1010: Signaling
• 3’b1011-3’b1110: Reserved
• 3’b1111: PTP packet with Reserved message type
When set, this bit indicates that the received packet is an IPv6
[7] IPv6 Packet Received packet. This bit is updated only when Bit[10] (IPC) of Register (MAC
Configuration Register) is set.
When set, this bit indicates that the received packet is an IPv4
[6] IPv4 Packet Received packet. This bit is updated only when Bit[10] (IPC) of Register (MAC
Configuration Register) is set.
When set, this bit indicates that the checksum offload engine is
[5] IP Checksum Bypassed
bypassed.
When set, this bit indicates that the 16-bit IP payload checksum
(that is, the TCP, UDP, or ICMP checksum) that the core calculated
does not match the corresponding checksum field in the received
[4] IP Payload Error
segment. It is also set when the TCP, UDP, or ICMP segment length
does not match the payload length value in the IP Header field. This
bit is valid when either Bit 7 or Bit 6 is set.
When set, this bit indicates that either the 16-bit IPv4 header check-
sum calculated by the core does not match the received checksum
[3] IP Header Error
bytes, or the IP datagram version is not consistent with the Ethernet
Type value. This bit is valid when either Bit[7] or Bit[6] is set.
These bits indicate the type of payload encapsulated in the IP data-
gram processed by the Receive Checksum Offload Engine (COE).
The COE also sets these bits to 2’b00 if it does not process the IP
datagram’s payload due to an IP header error or fragmented IP.
• 3’b000: Unknown or did not process IP payload
[2:0] IP Payload Type
• 3’b001: UDP
• 3’b010: TCP
• 3’b011: ICMP
• 3’b1xx: Reserved
This bit is valid when either Bit[7] or Bit[6] is set.

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10. Ethernet MAC

Table 52: Receive Descriptor 6 (RDES6)

Bits Name Description

This field is updated by DMA with the least significant 32 bits of the
RTSH: Receive Frame timestamp captured for the corresponding receive frame. This field
[31:0]
Timestamp Low is updated by DMA only for the last descriptor of the receive frame
which is indicated by the Last Descriptor status bit (RDES0[8]).

Table 53: Receive Descriptor 7 (RDES7)

Bits Name Description

This field is updated by DMA with the most significant 32 bits of the
RTSH: Receive Frame timestamp captured for the corresponding receive frame. This field
[31:0]
Timestamp High is updated by DMA only for the last descriptor of the receive frame
which is indicated by the Last Descriptor status bit (RDES0[8]).

10.9 Register Summary

Note that specific fields or bits of a given register may have different access attributes. Below is the list of all
attributes together with the abbreviations used in register descriptions.

• Read Only (RO)

• Write Only (WO)

• Read and Write (R/W)

• Read, Write, and Self Clear (R/W/SC)

• Read, Self Set, and Write Clear (R/SS/WC)

• Read, Write Set, and Self Clear (R/WS/SC)

• Read, Self Set, and Self Clear or Write Clear (R/SS/SC/WC)

• Read Only and Write Trigger (RO/WT)

• Read, Self Set, and Read Clear (R/SS/RC)

• Read, Write, and Self Update (R/W/SU)

• Latched-low (LL)

• Latched-high (LH)

Name Description Address Access

DMA configuration and control registers
DMABUSMODE_REG Bus mode configuration 0x60029000 R/WS/SC
DMATXPOLLDEMAND_REG Pull demand for data transmit 0x60029004 RO/WT
DMARXPOLLDEMAND_REG Pull demand for data receive 0x60029008 RO/WT
Base address of the first receive descrip-
DMARXBASEADDR_REG 0x6002900C R/W
tor

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10. Ethernet MAC

Name Description Address Access

Base address of the first transmit de-
DMATXBASEADDR_REG 0x60029010 R/W
scriptor
State of interrupts, errors and other
DMASTATUS_REG 0x60029014 R/SS/WC
events
Receive and Transmit operating modes
DMAOPERATION_MODE_REG 0x60029018 R/SS/WC
and command
DMAIN_EN_REG Enable / disable interrupts 0x6002901C R/W
Missed Frame and Buffer Overflow
DMAMISSEDFR_REG 0x60029020 R/W
Counter Register
DMARINTWDTIMER_REG Watchdog timer count on receive 0x60029024 R/W
DMATXCURRDESC_REG Pointer to current transmit descriptor 0x60029048 RO
DMARXCURRDESC_REG Pointer to current receive descriptor 0x6002904C RO
DMATXCURRADDR_BUF_REG Pointer to current transmit buffer 0x60029050 RO
DMARXCURRADDR_BUF_REG Pointer to current receive buffer 0x60029054 RO
MAC configuration and control registers
EMACCONFIG_REG MAC configuration 0x6002A000 R/W
EMACFF_REG Frame filter settings 0x6002A004 R/W
EMACMIIADDR_REG PHY configuration access 0x6002A010 R/WS/SC
EMACMIIDATA_REG PHY data read write 0x6002A014 R/W
R/WS/SC(FCB)
EMACFC_REG frame flow control 0x6002A018
R/W(BPA)
EMACDEBUG_REG Status debugging bits 0x6002A024 RO
PMT_RWUFFR_REG Remote Wake-Up Frame Filter 0x6002A028 RO
PMT_CSR_REG PMT Control and Status 0x6002A02C RO
EMACLPI_CSR_REG LPI Control and Status 0x6002A030 RO
EMACLPITIMERSCONTROL_REG LPI Timers Control 0x6002A034 RO
EMACINTS_REG Interrupt status 0x6002A038 RO
EMACINTMASK_REG Interrupt mask 0x6002A03C R/W
Upper 16 bits of the first 6-byte MAC ad-
EMACADDR0HIGH_REG 0x6002A040 R/W
dress
Lower 32 bits of the first 6-byte MAC ad-
EMACADDR0LOW_REG 0x6002A044 R/W
dress
MAC address filtering and upper 16 bits
EMACADDR1HIGH_REG 0x6002A048 R/W
of the second 6-byte MAC address
Lower 32 bits of the second 6-byte MAC
EMACADDR1LOW_REG 0x6002A04C R/W
address
MAC address filtering and upper 16 bits
EMACADDR2HIGH_REG 0x6002A050 R/W
of the third 6-byte MAC address
Lower 32 bits of the third 6-byte MAC
EMACADDR2LOW_REG 0x6002A054 R/W
address
MAC address filtering and upper 16 bits
EMACADDR3HIGH_REG 0x6002A058 R/W
of the fourth 6-byte MAC address

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10. Ethernet MAC

Name Description Address Access

Lower 32 bits of the fourth 6-byte MAC
EMACADDR3LOW_REG 0x6002A05C R/W
address
MAC address filtering and upper 16 bits
EMACADDR4HIGH_REG 0x6002A060 R/W
of the fifth 6-byte MAC address
Lower 32 bits of the fifth 6-byte MAC ad-
EMACADDR4LOW_REG 0x6002A064 R/W
dress
MAC address filtering and upper 16 bits
EMACADDR5HIGH_REG 0x6002A068 R/W
of the sixth 6-byte MAC address
Lower 32 bits of the sixth 6-byte MAC
EMACADDR5LOW_REG 0x6002A06C R/W
address
MAC address filtering and upper 16 bits
EMACADDR6HIGH_REG 0x6002A070 R/W
of the seventh 6-byte MAC address
Lower 32 bits of the seventh 6-byte
EMACADDR6LOW_REG 0x6002A074 R/W
MAC address
MAC address filtering and upper 16 bits
EMACADDR7HIGH_REG 0x6002A078 R/W
of the eighth 6-byte MAC address
Lower 32 bits of the eighth 6-byte MAC
EMACADDR7LOW_REG 0x6002A07C R/W
address
EMACCSTATUS_REG Link communication status 0x6002A0D8 RO
EMACWDOGTO_REG Watchdog timeout control 0x6002A0DC R/W
Clock configuration registers
EMAC_EX_CLKOUT_CONF_REG RMII clock divider setting 0x60029800 R/W
RMII clock half and whole divider set-
EMAC_EX_OSCCLK_CONF_REG 0x60029804 R/W
tings
Clock enable and external / internal
EMAC_EX_CLK_CTRL_REG 0x60029808 R/W
clock selection
PHY type and SRAM configuration registers
EMAC_EX_PHYINF_CONF_REG Selection of MII / RMII phy 0x6002980C R/W
EMAC_PD_SEL_REG Ethernet RAM power-down enable 0x60029810 R/W

10.10 Registers
Note: The value of all reset registers must be set to the reset value.

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10. Ethernet MAC

Register 10.1: DMABUSMODE_REG (0x0000)

EN
E_ MO LIB T
SE D EA
US X8_ RA RS

EN
_L

CH
IZ
L

ST
P_ E

RA ST
L D U

_L
L
PB

ST _S
PB
PB AD DB

UR

C_

IP
R

_R RB
BU
A_

K
A XE
d)

S
TI

_B

_S
ve

DE

SW A
M

D_
DM MI

A_
SC
r

_D

T_
se

O
I_
XE

DM
DM

PR

PR

DE
RX

AL
(re

FI
31 27 26 25 24 23 22 17 16 15 14 13 8 7 6 2 1 0

0 0 0 0 0 0 0 0 0 0x01 0 0x0 0x01 0 0x00 0 1 Reset

DMAMIXEDBURST When this bit is set high and the FB(FIXES_BURST) bit is low, the AHB master
interface starts all bursts of a length more than 16 with INCR (undefined burst), whereas it reverts
to fixed burst transfers (INCRx and SINGLE) for burst length of 16 and less. (R/W)

DMAADDRALIBEA When this bit is set high and the FB bit is 1, the AHB interface generates all bursts
aligned to the start address LS bits. If the FB bit is 0, the first burst (accessing the start address of
data buffer) is not aligned, but subsequent bursts are aligned to the address. (R/W)

PBLX8_MODE When set high, this bit multiplies the programmed PBL(PROG_BURST_LEN) value
(Bits[22:17] and Bits[13:8]) eight times. Therefore, the DMA transfers the data in 8, 16, 32, 64,
128, and 256 beats depending on the PBL value. (R/W)

USE_SEP_PBL When set high, this bit configures the Rx DMA to use the value configured in
Bits[22:17] as PBL. The PBL value in Bits[13:8] is applicable only to the Tx DMA operations. When
reset to low, the PBL value in Bits[13:8] is applicable for both DMA engines. (R/W)

RX_DMA_PBL This field indicates the maximum number of beats to be transferred in one Rx DMA
transaction. This is the maximum value that is used in a single block Read or Write.The Rx DMA
always attempts to burst as specified in the RPBL(RX_DMA_PBL) bit each time it starts a burst
transfer on the host bus. You can program RPBL with values of 1, 2, 4, 8, 16, and 32. Any other
value results in undefined behavior. This field is valid and applicable only when USP(USE_SEP_PBL)
is set high. (R/W)

FIXED_BURST This bit controls whether the AHB master interface performs fixed burst transfers or
not. When set, the AHB interface uses only SINGLE, INCR4, INCR8, or INCR16 during start of
the normal burst transfers. When reset, the AHB interface uses SINGLE and INCR burst transfer
operations. (R/W)

PRI_RATIO These bits control the priority ratio in the weighted round-robin arbitration between the
Rx DMA and Tx DMA. These bits are valid only when Bit 1 (DA) is reset. The priority ratio Rx:Tx
represented by each bit: (R/W)

• 2’b00 — 1: 1

• 2’b01 — 2: 0

• 2’b10 — 3: 1

• 2’b11 — 4: 1

Continued on the next page...

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10. Ethernet MAC

Register 10.1: DMABUSMODE_REG (0x0000)

Continued from the previous page...

PROG_BURST_LEN These bits indicate the maximum number of beats to be transferred in one DMA
transaction. If the number of beats to be transferred is more than 32, then perform the following
steps: 1. Set the PBLx8 mode; 2. Set the PBL. (R/W)

ALT_DESC_SIZE When set, the size of the alternate descriptor increases to 32 bytes. (R/W)

DESC_SKIP_LEN This bit specifies the number of Word to skip between two unchained descriptors.
The address skipping starts from the end of current descriptor to the start of next descriptor. When
the DSL(DESC_SKIP_LEN) value is equal to zero, the descriptor table is taken as contiguous by
the DMA in Ring mode. (R/W)

DMA_ARB_SCH This bit specifies the arbitration scheme between the transmit and receive paths.
1’b0: weighted round-robin with RX: TX or TX: RX, priority specified in PR (bit[15:14]); 1’b1 Fixed
priority (Rx priority to Tx). (R/W)

SW_RST When this bit is set, the MAC DMA Controller resets the logic and all internal registers of the
MAC. It is cleared automatically after the reset operation is complete in all of the ETH_MAC clock
domains. Before reprogramming any register of the ETH_MAC, you should read a zero (0) value in
this bit. (R/WS/SC)

Register 10.2: DMATXPOLLDEMAND_REG (0x0004)

31 0

0x000000000 Reset

TRANS_POLL_DEMAND When these bits are written with any value, the DMA reads the current
descriptor to which the Register (Current Host Transmit Descriptor Register) is pointing. If that
descriptor is not available (owned by the Host), the transmission returns to the suspend state and
Bit[2] (TU) of Status Register is asserted. If the descriptor is available, the transmission resumes.
(RO/WT)

Register 10.3: DMARXPOLLDEMAND_REG (0x0008)

31 0

0x000000000 Reset

RECV_POLL_DEMAND When these bits are written with any value, the DMA reads the current de-
scriptor to which the Current Host Receive Descriptor Register is pointing. If that descriptor is
not available (owned by the Host), the reception returns to the Suspended state and Bit[7] (RU) of
Status Register is asserted. If the descriptor is available, the Rx DMA returns to the active state.
(RO/WT)

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10. Ethernet MAC

Register 10.4: DMARXBASEADDR_REG (0x000C)

31 0

0x000000000 Reset

START_RECV_LIST This field contains the base address of the first descriptor in the Receive De-
scriptor list. The LSB Bits[1:0] are ignored and internally taken as all-zero by the DMA. Therefore,
these LSB bits are read-only. (R/W)

Register 10.5: DMATXBASEADDR_REG (0x0010)

31 0

0x000000000 Reset

START_TRANS_LIST This field contains the base address of the first descriptor in the Transmit De-
scriptor list. The LSB Bits[1:0] are ignored and are internally taken as all-zero by the DMA. Therefore,
these LSB bits are read-only. (R/W)

Register 10.6: DMASTATUS_REG (0x0014)

T ST IL
E

NT

P
L

IN C_ VA
AN _P _U TO
AT

A IN UN P

O
AI
C PR T T
AT

TR S FL OW
FA Y_ SU MM

_I

TR V_ F_ STO
ST

S_ RO NA
RE V_ DT_ _IN

AV
S_ INT

TR NS UF R_
d) RR
ST

L_ EC M
ed INT

TR NS AB W
RE V_ OC O
C_

AN OV FL

A _B BE
RL T_ U
TA R M

C W S
(re BU V_
C_

C BU _
E

A _J O
S

RE _ AN
TS
T_

TR _ D
O

EA IN T_
T

RO

N
PR
(re _PM

BI

CV TR
AC _IN

RE NS T
N_ IN

CV _U
TS ed)

R_

S_

_P

AB M_

RE LY_
e
EM RI
rv

rv

rv
RO

AN

CV
_T
se

se

se
R

R
NO
ER

RE
TR

EA
(re

31 30 29 28 27 26 25 23 22 20 19 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

0 0 0 0 0 0 0x0 0x0 0x0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Reset

TS_TRI_INT This bit indicates an interrupt event in the Timestamp Generator block of the ETH_MAC.
The software must read the corresponding registers in the ETH_MAC to get the exact cause of the
interrupt and clear its source to reset this bit to 1’b0. (RO)

EMAC_PMT_INT This bit indicates an interrupt event in the PMT module of the ETH_MAC. The soft-
ware must read the PMT Control and Status Register in the MAC to get the exact cause of interrupt
and clear its source to reset this bit to 1’b0. (RO)

Continued on the next page...

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10. Ethernet MAC

Register 10.6: DMASTATUS_REG (0x0014)

Continued from the previous page...

ERROR_BITS This field indicates the type of error that caused a Bus Error, for example, error response
on the AHB interface. This field is valid only when Bit[13] (FBI) is set. This field does not generate
an interrupt. (RO)

• 3’b000: Error during Rx DMA Write Data Transfer.

• 3’b011: Error during Tx DMA Read Data Transfer.

• 3’b100: Error during Rx DMA Descriptor Write Access.

• 3’b101: Error during Tx DMA Descriptor Write Access.

• 3’b110: Error during Rx DMA Descriptor Read Access.

• 3’b111: Error during Tx DMA Descriptor Read Access.

TRANS_PROC_STATE This field indicates the Transmit DMA FSM state. This field does not generate
an interrupt. (RO)

• 3’b000: Stopped. Reset or Stop Transmit Command issued.

• 3’b001: Running. Fetching Transmit Transfer Descriptor.

• 3’b010: Reserved for future use.

• 3’b011: Running. Waiting for TX packets.

• 3’b100: Suspended. Receive Descriptor Unavailable.

• 3’b101: Running. Closing Transmit Descriptor.

• 3’b110: TIME_STAMP write state.

• 3’b111: Running. Transferring the TX packets data from transmit buffer to host memory.

RECV_PROC_STATE This field indicates the Receive DMA FSM state. This field does not generate
an interrupt. (RO)

• 3’b000: Stopped. Reset or Stop Receive Command issued.

• 3’b001: Running. Fetching Receive Transfer Descriptor.

• 3’b010: Reserved for future use.

• 3’b011: Running. Waiting for RX packets.

• 3’b100: Suspended. Receive Descriptor Unavailable.

• 3’b101: Running. Closing Receive Descriptor.

• 3’b110: TIME_STAMP write state.

• 3’b111: Running. Transferring the TX packets data from receive buffer to host memory.

Continued on the next page...

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10. Ethernet MAC

Register 10.6: DMASTATUS_REG (0x0014)

Continued from the previous page...

NORM_INT_SUMM Normal Interrupt Summary bit value is the logical OR of the following bits when
the corresponding interrupt bits are enabled in Interrupt Enable Register:(R/SS/WC)

• Bit[0]: Transmit Interrupt.

• Bit[2]: Transmit Buffer Unavailable.

• Bit[6]: Receive Interrupt.

• Bit[14]: Early Receive Interrupt. Only unmasked bits affect the Normal Interrupt Summary bit.
This is a sticky bit and must be cleared (by writing 1 to this bit) each time a corresponding bit,
which causes NIS to be set, is cleared.

ABN_INT_SUMM Abnormal Interrupt Summary bit value is the logical OR of the following when the
corresponding interrupt bits are enabled in Interrupt Enable Register: (R/SS/WC)

• Bit[1]: Transmit Process Stopped.

• Bit[3]: Transmit Jabber Timeout.

• Bit[4]: Receive FIFO Overflow.

• Bit[5]: Transmit Underflow.

• Bit[7]: Receive Buffer Unavailable. Bit[8]: Receive Process Stopped.

• Bit[9]: Receive Watchdog Timeout.

• Bit[10]: Early Transmit Interrupt.

• Bit[13]: Fatal Bus Error. Only unmasked bits affect the Abnormal Interrupt Summary bit. This
is a sticky bit and must be cleared (by writing 1 to this bit) each time a corresponding bit,
which causes AIS to be set, is cleared.

EARLY_RECV_INT This bit indicates that the DMA filled the first data buffer of the packet. This bit is
cleared when the software writes 1 to this bit or when Bit[6] (RI) of this register is set (whichever
occurs earlier). (R/SS/WC)

FATAL_BUS_ERR_INT This bit indicates that a bus error occurred, as described in Bits [25:23]. When
this bit is set, the corresponding DMA engine disables all of its bus accesses. (R/SS/WC)

EARLY_TRANS_INT This bit indicates that the frame to be transmitted is fully transferred to the MTL
Transmit FIFO. (R/SS/WC)

RECV_WDT_TO When set, this bit indicates that the Receive Watchdog Timer expired while receiving
the current frame and the current frame is truncated after the watchdog timeout. (R/SS/WC)

Continued on the next page...

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10. Ethernet MAC

Register 10.6: DMASTATUS_REG (0x0014)

Continued from the previous page...

RECV_PROC_STOP This bit is asserted when the Receive Process enters the Stopped state.
(R/SS/WC)

RECV_BUF_UNAVAIL This bit indicates that the host owns the Next Descriptor in the Receive List and
the DMA cannot acquire it. The Receive Process is suspended. To resume processing Receive
descriptors, the host should change the ownership of the descriptor and issue a Receive Poll
Demand command. If no Receive Poll Demand is issued, the Receive Process resumes when
the next recognized incoming frame is received. This bit is set only when the previous Receive
Descriptor is owned by the DMA. (R/SS/WC)

RECV_INT This bit indicates that the frame reception is complete. When reception is complete, the
Bit[31] of RDES1 (Disable Interrupt on Completion) is reset in the last Descriptor, and the specific
frame status information is updated in the descriptor. The reception remains in the Running state.
(R/SS/WC)

TRANS_UNDFLOW This bit indicates that the Transmit Buffer had an Underflow during frame trans-
mission. Transmission is suspended and an Underflow Error TDES0[1] is set. (R/SS/WC)

RECV_OVFLOW This bit indicates that the Receive Buffer had an Overflow during frame recep-
tion. If the partial frame is transferred to the application, the overflow status is set in RDES0[11].
(R/SS/WC)

TRANS_JABBER_TO This bit indicates that the Transmit Jabber Timer expired, which happens when
the frame size exceeds 2,048 (10,240 bytes when the Jumbo frame is enabled). When the Jabber
Timeout occurs, the transmission process is aborted and placed in the Stopped state. This causes
the Transmit Jabber Timeout TDES0[14] flag to assert. (R/SS/WC)

TRANS_BUF_UNAVAIL This bit indicates that the host owns the Next Descriptor in the Transmit
List and the DMA cannot acquire it. Transmission is suspended. Bits[22:20] explain the Transmit
Process state transitions. To resume processing Transmit descriptors, the host should change
the ownership of the descriptor by setting TDES0[31] and then issue a Transmit Poll Demand
command. (R/SS/WC)

TRANS_PROC_STOP This bit is set when the transmission is stopped. (R/SS/WC)

TRANS_INT This bit indicates that the frame transmission is complete. When transmission is com-
plete, Bit[31] (OWN) of TDES0 is reset, and the specific frame status information is updated in the
descriptor. (R/SS/WC)

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10. Ethernet MAC

Register 10.7: DMAOPERATION_MODE_REG (0x0018)

D
AN
M
M
CO
N_
M

O
TX rve ) EC RD FRA

ES

SI
IS
AM
se d R A _

M
(re rve H_ RW ERR

X E
FR

NS

) _R AM
V_

(re T_ ON RL
se US FO _

RL

RA

RX GF _ E

ed P R
(re FL E_ PIP

R GF
P_ E M

rv TO _F
CT
O

CT

ed _T

O ND RA
S_ R C

IF

se S D
TX D

H_
P

HR M
H_

R
DI STO P_T

_F

DR U _F
H_ W

PT ES
ES

ST

D_ RR
US _F

AR EC
d)

FL STR )

(re ed)

D_ )
_ O

_ d

ed

d
HR

T_
ve

FW ve
RX DR

FW E

ST _S
rv

rv

rv
er

r
AR

_T
_T
se

se

se

se
S_
s

ST
TX
(re

(re

(re

(re
DI

O
31 27 26 25 24 23 22 21 20 19 17 16 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Reset

DIS_DROP_TCPIP_ERR_FRAM When this bit is set, the MAC does not drop the frames which only
have errors detected by the Receive Checksum engine.When this bit is reset, all error frames are
dropped if the Fwd_Err_Frame bit is reset. (R/W)

RX_STORE_FORWARD When this bit is set, the MTL reads a frame from the Rx FIFO only after the
complete frame has been written to it. (R/W)

DIS_FLUSH_RECV_FRAMES When this bit is set, the Rx DMA does not flush any frames because
of the unavailability of receive descriptors or buffers. (R/W)

TX_STR_FWD When this bit is set, transmission starts when a full frame resides in the MTL Trans-
mit FIFO. When this bit is set, the TX_THRESH_CTRL values specified in TX_THRESH_CTRL are
ignored. (R/W)

FLUSH_TX_FIFO When this bit is set, the transmit FIFO controller logic is reset to its default values
and thus all data in the Tx FIFO is lost or flushed. This bit is cleared internally when the flushing
operation is complete. (R/WS/SC)

TX_THRESH_CTRL These bits control the threshold level of the MTL Transmit FIFO. Transmission
starts when the frame size within the MTL Transmit FIFO is larger than the threshold. In addition,
full frames with a length less than the threshold are also transmitted. These bits are used only
when TX_STR_FWD is reset. 3’b000: 64, 3’b001: 128, 3’b010: 192, 3’b011: 256, 3’b100: 40,
3’b101: 32, 3’b110: 24, 3’b111: 16. (R/W)

START_STOP_TRANSMISSION_COMMAND When this bit is set, transmission is placed in the Run-

ning state, and the DMA checks the Transmit List at the current position for a frame to be transmit-
ted. When this bit is reset, the transmission process is placed in the Stopped state after completing
the transmission of the current frame. (R/W)

FWD_ERR_FRAME When this bit is reset, the Rx FIFO drops frames with error status (CRC error,
collision error, giant frame, watchdog timeout, or overflow). (R/W)

FWD_UNDER_GF When set, the Rx FIFO forwards Undersized frames (that is, frames with no Error
and length less than 64 bytes) including pad-bytes and CRC.

DROP_GFRM When set, the MAC drops the received giant frames in the Rx FIFO, that is, frames that
are larger than the computed giant frame limit. (R/W)

Continued on the next page...

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10. Ethernet MAC

Register 10.7: DMAOPERATION_MODE_REG (0x0018)

Continued from the previous page...

RX_THRESH_CTRL These two bits control the threshold level of the MTL Receive FIFO. Transfer (re-
quest) to DMA starts when the frame size within the MTL Receive FIFO is larger than the threshold.
2’b00: 64; 2’b01: 32; 2’b10: 96; 2’b11: 128. (R/W)

OPT_SECOND_FRAME When this bit is set, it instructs the DMA to process the second frame of the
Transmit data even before the status for the first frame is obtained. (R/W)

START_STOP_RX When this bit is set, the Receive process is placed in the Running state. The DMA
attempts to acquire the descriptor from the Receive list and processes the incoming frames.When
this bit is cleared, the Rx DMA operation is stopped after the transfer of the current frame. (R/W)

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10. Ethernet MAC

Register 10.8: DMAIN_EN_REG (0x001C)

_R E

A R E

AI TS E
EE

DM IN JTE
DM IN ISE

DM IN WT
DM IN ISE

(re _FB E

DM IN BU
DM N IE

DM IN BU
DM IN SE

N_ E
DM IN IE
DM IN IE
N I

D M IN IE

E
AI R

AI ET

TI
A O
A N

A U
A R

A R
)

DM ed)
A A
_E

A T
_T
ed

_
_

_
_

_
_
_
_
_

_
DM IN

DM IN
rv

rv
A

A
se

se
DM
(re
31 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Reset

DMAIN_NISE When this bit is set, normal interrupt summary is enabled. When this bit is reset, normal
interrupt summary is disabled. This bit enables the following interrupts in Status Register: (R/W)

• Bit[0]: Transmit Interrupt.

• Bit[2]: Transmit Buffer Unavailable.

• Bit[6]: Receive Interrupt.

• Bit[14]: Early Receive Interrupt.

DMAIN_AISE When this bit is set, abnormal interrupt summary is enabled. When this bit is reset,
the abnormal interrupt summary is disabled. This bit enables the following interrupts in Status
Register:(R/W)

• Bit[1]: Transmit Process Stopped.

• Bit[3]: Transmit Jabber Timeout.

• Bit[4]: Receive Overflow.

• Bit[5]: Transmit Underflow.

• Bit[7]: Receive Buffer Unavailable.

• Bit[8]: Receive Process Stopped.

• Bit[9]: Receive Watchdog Timeout.

• Bit[10]: Early Transmit Interrupt.

• Bit[13]: Fatal Bus Error.

DMAIN_ERIE When this bit is set with Normal Interrupt Summary Enable (Bit[16]), the Early Receive
Interrupt is enabled. When this bit is reset, the Early Receive Interrupt is disabled. (R/W)

Continued on the next page...

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10. Ethernet MAC

Register 10.8: DMAIN_EN_REG (0x001C)

Continued from the previous page...

DMAIN_FBEE When this bit is set with Abnormal Interrupt Summary Enable (Bit[15]), the Fatal Bus
Error Interrupt is enabled. When this bit is reset, the Fatal Bus Error Enable Interrupt is disabled.
(R/W)

DMAIN_ETIE When this bit is set with an Abnormal Interrupt Summary Enable (Bit[15]), the Early
Transmit Interrupt is enabled. When this bit is reset, the Early Transmit Interrupt is disabled. (R/W)

DMAIN_RWTE When this bit is set with Abnormal Interrupt Summary Enable (Bit[15]), the Receive
Watchdog Timeout Interrupt is enabled. When this bit is reset, the Receive Watchdog Timeout
Interrupt is disabled. (R/W)

DMAIN_RSE When this bit is set with Abnormal Interrupt Summary Enable (Bit[15]), the Receive
Stopped Interrupt is enabled. When this bit is reset, the Receive Stopped Interrupt is disabled.
(R/W)

DMAIN_RBUE When this bit is set with Abnormal Interrupt Summary Enable (Bit[15]), the Receive
Buffer Unavailable Interrupt is enabled. When this bit is reset, the Receive Buffer Unavailable Inter-
rupt is disabled. (R/W)

DMAIN_RIE When this bit is set with Normal Interrupt Summary Enable (Bit[16]), the Receive Interrupt
is enabled. When this bit is reset, the Receive Interrupt is disabled. (R/W)

DMAIN_UIE When this bit is set with Abnormal Interrupt Summary Enable (Bit[15]), the Transmit Un-
derflow Interrupt is enabled. When this bit is reset, the Underflow Interrupt is disabled. (R/W)

DMAIN_OIE When this bit is set with Abnormal Interrupt Summary Enable (Bit[15]), the Receive Over-
flow Interrupt is enabled. When this bit is reset, the Overflow Interrupt is disabled. (R/W)

DMAIN_TJTE When this bit is set with Abnormal Interrupt Summary Enable (Bit[15]), the Transmit
Jabber Timeout Interrupt is enabled. When this bit is reset, the Transmit Jabber Timeout Interrupt
is disabled. (R/W)

DMAIN_TBUE When this bit is set with Normal Interrupt Summary Enable (Bit 16), the Transmit Buffer
Unavailable Interrupt is enabled. When this bit is reset, the Transmit Buffer Unavailable Interrupt is
disabled. (R/W)

DMAIN_TSE When this bit is set with Abnormal Interrupt Summary Enable (Bit[15]), the Transmission
Stopped Interrupt is enabled. When this bit is reset, the Transmission Stopped Interrupt is disabled.
(R/W)

DMAIN_TIE When this bit is set with Normal Interrupt Summary Enable (Bit[16]), the Transmit Interrupt
is enabled. When this bit is reset, the Transmit Interrupt is disabled. (R/W)

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10. Ethernet MAC

Register 10.9: DMAMISSEDFR_REG (0x0020)

FC
C
FO

M
C
_B

_B
_F

C
)

_F
ed

ow

ow

ow

ed
rv

rfl

rfl

rfl
se

iss
ve

ve

ve
(re

M
O

O
30 29 28 27 17 16 10 0

0 0 0x0 0x0 0x0 0x0 Reset

Overflow_BFOC This bit is set every time the Overflow Frame Counter (Bits[27:17]) overflows, that
is, the Rx FIFO overflows with the overflow frame counter at maximum value. In such a scenario,
the overflow frame counter is reset to all-zeros and this bit indicates that the rollover happened.
(R/SS/RC)

Overflow_FC This field indicates the number of frames missed by the application. This counter is
incremented each time the MTL FIFO overflows. The counter is cleared when this register is read.
(R/SS/RC)

Overflow_BMFC This bit is set every time Missed Frame Counter (Bits[15:0]) overflows, that is, the
DMA discards an incoming frame because of the Host Receive Buffer being unavailable with the
missed frame counter at maximum value. In such a scenario, the Missed frame counter is reset to
all-zeros and this bit indicates that the rollover happened. (R/SS/RC)

Missed_FC This field indicates the number of frames missed by the controller because of the Host
Receive Buffer being unavailable. This counter is incremented each time the DMA discards an
incoming frame. The counter is cleared when this register is read. (R/SS/RC)

Register 10.10: DMARINTWDTIMER_REG (0x0024)

d )
ve

TC
r
se

W
(re

RI

31 8 7 0

0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0x000 Reset

RIWTC This bit indicates the number of system clock cycles multiplied by 256 for which the watchdog
timer is set. The watchdog timer gets triggered with the programmed value after the Rx DMA
completes the transfer of a frame for which the RI (RECV_INT) status bit is not set because of the
setting in the corresponding descriptor RDES1[31]. When the watchdog timer runs out, the RI bit
is set and the timer is stopped. The watchdog timer is reset when the RI bit is set high because of
automatic setting of RI as per RDES1[31] of any received frame. (R/W)

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10. Ethernet MAC

Register 10.11: DMATXCURRDESC_REG (0x0048)

31 0

0x000000000 Reset

TRANS_DSCR_ADDR_PTR The address of the current receive descriptor list. Cleared on Reset.
Pointer updated by the DMA during operation. (RO)

Register 10.12: DMARXCURRDESC_REG (0x004C)

31 0

0x000000000 Reset

RECV_DSCR_ADDR_PTR The address of the current receive descriptor list. Cleared on Reset.
Pointer updated by the DMA during operation. (RO)

Register 10.13: DMATXCURRADDR_BUF_REG (0x0050)

31 0

0x000000000 Reset

TRANS_BUFF_ADDR_PTR The address of the current receive descriptor list. Cleared on Reset.
Pointer updated by the DMA during operation. (RO)

Register 10.14: DMARXCURRADDR_BUF_REG (0x0054)

31 0

0x000000000 Reset

RECV_BUFF_ADDR_PTR The address of the current receive descriptor list. Cleared on Reset.
Pointer updated by the DMA during operation. (RO)

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10. Ethernet MAC

Register 10.15: EMACCONFIG_REG (0x1000)

CK
AP

AD

HE
AC X RA IT
EG
E

EM CD OF IP
AM

EM CT FER IM
S

LC
G

CR

EM CR PLE CK

EM rve RY FL

EM BAC ST

L
EM rve BE O

FR

RA

F
EM CL OW D
se AB HD

se ET OF
AC II LE

A U BA

RC
AC d) R

A X X
AC OO N
E
BO

RF

EM CR SPE
EM CM AB

(re CR IPC
(re CJ TC

EM D P

K
DC
TE
M
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AC d)
A IS
A A
ed

ed

E
X

PL RX
A
JU

A E
KP

IN
EM W

EM D

P
EM F
rv

rv
C

AC

AC

AC

AC
S2
se

se

TF
IR

A
A
EM

EM

EM

EM
SA

AS
(re

(re
31 30 28 27 26 24 23 22 21 20 19 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

0 0x0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0x0 0 0 0 0x0 Reset

SAIRC This field controls the source address insertion or replacement for all transmitted frames.
Bit[30] specifies which MAC Address register (0 or 1) is used for source address insertion or re-
placement based on the values of Bits [29:28]: (R/W)

• 2’b0x: The input signals mti_sa_ctrl_i and ati_sa_ctrl_i control the SA field generation.

• 2’b10: If Bit[30] is set to 0, the MAC inserts the content of the MAC Address 0 registers in
the SA field of all transmitted frames. If Bit[30] is set to 1 the MAC inserts the content of the
MAC Address 1 registers in the SA field of all transmitted frames.

• 2’b11: If Bit[30] is set to 0, the MAC replaces the content of the MAC Address 0 registers in
the SA field of all transmitted frames. If Bit[30] is set to 1, the MAC replaces the content of
the MAC Address 1 registers in the SA field of all transmitted frames.

ASS2KP When set, the MAC considers all frames, with up to 2,000 bytes length, as normal packets.
When Bit[20] (JE) is not set, the MAC considers all received frames of size more than 2K bytes
as Giant frames. When this bit is reset and Bit[20] (JE) is not set, the MAC considers all received
frames of size more than 1,518 bytes (1,522 bytes for tagged) as Giant frames. When Bit[20] is
set, setting this bit has no effect on Giant Frame status. (R/W)

EMACWATCHDOG When this bit is set, the MAC disables the watchdog timer on the receiver. The
MAC can receive frames of up to 16,383 bytes. When this bit is reset, the MAC does not allow a
receive frame which more than 2,048 bytes (10,240 if JE is set high) or the value programmed in
Register (Watchdog Timeout Register). The MAC cuts off any bytes received after the watchdog
limit number of bytes. (R/W)

EMACJABBER When this bit is set, the MAC disables the jabber timer on the transmitter. The MAC
can transfer frames of up to 16,383 bytes. When this bit is reset, the MAC cuts off the trans-
mitter if the application sends out more than 2,048 bytes of data (10,240 if JE is set high) during
transmission. (R/W)

EMACJUMBOFRAME When this bit is set, the MAC allows Jumbo frames of 9,018 bytes (9,022
bytes for VLAN tagged frames) without reporting a giant frame error in the receive frame status.
(R/W)

Continued on the next page...

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10. Ethernet MAC

Register 10.15: EMACCONFIG_REG (0x1000)

Continued from the previous page...

EMACINTERFRAMEGAP These bits control the minimum IFG between frames during transmission.
(R/W)

• 3’b000: 96 bit times.

• 3’b001: 88 bit times.

• 3’b010: 80 bit times.

• 3’b111: 40 bit times. In the half-duplex mode, the minimum IFG can be configured only for
64 bit times (IFG = 100). Lower values are not considered.

EMACDISABLECRS When set high, this bit makes the MAC transmitter ignore the MII CRS signal
during frame transmission in the half-duplex mode. This request results in no errors generated
because of Loss of Carrier or No Carrier during such transmission. When this bit is low, the MAC
transmitter generates such errors because of Carrier Sense and can even abort the transmissions.
(R/W)

EMACMII This bit selects the Ethernet line speed. It should be set to 1 for 10 or 100 Mbps operations.
In 10 or 100 Mbps operations, this bit, along with FES(EMACFESPEED) bit, it selects the exact
linespeed. In the 10/100 Mbps-only operations, the bit is always 1. (R/W)

EMACFESPEED This bit selects the speed in the MII, RMII interface. 0: 10 Mbps; 1: 100 Mbps.
(R/W)

EMACRXOWN When this bit is set, the MAC disables the reception of frames when the TX_EN is
asserted in the half-duplex mode. When this bit is reset, the MAC receives all packets that are
given by the PHY while transmitting. This bit is not applicable if the MAC is operating in the full-
duplex mode. (R/W)

EMACLOOPBACK When this bit is set, the MAC operates in the loopback mode MII. The MII Receive
clock input (CLK_RX) is required for the loopback to work properly, because the transmit clock is
not looped-back internally. (R/W)

EMACDUPLEX When this bit is set, the MAC operates in the full-duplex mode where it can transmit
and receive simultaneously. This bit is read only with default value of 1’b1 in the full-duplex-mode.
(R/W)

EMACRXIPCOFFLOAD When this bit is set, the MAC calculates the 16-bit one’s complement of the
one’s complement sum of all received Ethernet frame payloads. It also checks whether the IPv4
Header checksum (assumed to be bytes 25/26 or 29/30 (VLAN-tagged) of the received Ethernet
frame) is correct for the received frame and gives the status in the receive status word. The MAC
also appends the 16-bit checksum calculated for the IP header datagram payload (bytes after the
IPv4 header) and appends it to the Ethernet frame transferred to the application (when Type 2 COE
is deselected). When this bit is reset, this function is disabled. (R/W)

Continued on the next page...

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10. Ethernet MAC

Register 10.15: EMACCONFIG_REG (0x1000)

Continued from the previous page...

EMACRETRY When this bit is set, the MAC attempts only one transmission. When a collision occurs
on the MII interface, the MAC ignores the current frame transmission and reports a Frame Abort
with excessive collision error in the transmit frame status. When this bit is reset, the MAC attempts
retries based on the settings of the BL field (Bits [6:5]). This bit is applicable only in the half-duplex
mode. (R/W)

EMACPADCRCSTRIP When this bit is set, the MAC strips the Pad or FCS field on the incoming
frames only if the value of the length field is less than 1,536 bytes. All received frames with length
field greater than or equal to 1,536 bytes are passed to the application without stripping the Pad
or FCS field. When this bit is reset, the MAC passes all incoming frames, without modifying them,
to the Host. (R/W)

EMACBACKOFFLIMIT The Back-Off limit determines the random integer number (r) of slot time de-
lays (512 bit times for 10/100 Mbps) for which the MAC waits before rescheduling a transmission
attempt during retries after a collision. This bit is applicable only in the half-duplex mode.

• 00: k= min (n, 10).

• 01: k = min (n, 8).

• 10: k = min (n, 4).

• 11: k = min (n, 1), n = retransmission attempt. The random integer r takes the value in the
range 0 ~ 2000.

EMACDEFERRALCHECK Deferral Check. (R/W)

EMACTX When this bit is set, the transmit state machine of the MAC is enabled for transmission on
the MII. When this bit is reset, the MAC transmit state machine is disabled after the completion of
the transmission of the current frame, and does not transmit any further frames. (R/W)

EMACRX When this bit is set, the receiver state machine of the MAC is enabled for receiving frames
from the MII. When this bit is reset, the MAC receive state machine is disabled after the completion
of the reception of the current frame, and does not receive any further frames from the MII. (R/W)

PLTF These bits control the number of preamble bytes that are added to the beginning of every Trans-
mit frame. The preamble reduction occurs only when the MAC is operating in the full-duplex mode.
2’b00: 7 bytes of preamble. 2’b01: 5 bytes of preamble. 2’b10: 3 bytes of preamble. (R/W)

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10. Ethernet MAC

Register 10.16: EMACFF_REG (0x1004)

L
AL
E_

PM ed)
ed
V

DE
rv

rv
EI

SA E
se

se

O
C

IF
IF

M
F
F
F
RE

DB
PC

DA
SA
(re

(re
PA
31 30 10 9 8 7 6 5 4 3 2 1 0

0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0x0 0 0 0 0 0 0 Reset

RECEIVE_ALL When this bit is set, the MAC Receiver module passes all received frames, irrespective
of whether they pass the address filter or not, to the Application. The result of the SA or DA filtering
is updated (pass or fail) in the corresponding bits in the Receive Status Word. When this bit is reset,
the Receiver module passes only those frames to the Application that pass the SA or DA address
filter. (R/W)

SAFE When this bit is set, the MAC compares the SA field of the received frames with the values
programmed in the enabled SA registers. If the comparison fails, the MAC drops the frame. When
this bit is reset, the MAC forwards the received frame to the application with updated SAF bit of
the Rx Status depending on the SA address comparison. (R/W)

SAIF When this bit is set, the Address Check block operates in inverse filtering mode for the SA
address comparison. The frames whose SA matches the SA registers are marked as failing the
SA Address filter. When this bit is reset, frames whose SA does not match the SA registers are
marked as failing the SA Address filter. (R/W)

PCF These bits control the forwarding of all control frames (including unicast and multicast Pause
frames). (R/W)

• 2’b00: MAC filters all control frames from reaching the application.

• 2’b01: MAC forwards all control frames except Pause frames to application even if they fail
the Address filter.

• 2’b10: MAC forwards all control frames to application even if they fail the Address Filter.

• 2’b11: MAC forwards control frames that pass the Address Filter.

The following conditions should be true for the Pause frames processing:

• Condition 1: The MAC is in the full-duplex mode and flow control is enabled by setting Bit 2
(RFE) of Register (Flow Control Register) to 1.

• Condition 2: The destination address (DA) of the received frame matches the special multicast
address or the MAC Address 0 when Bit 3 (UP) of the Register(Flow Control Register) is set.

• Condition 3: The Type field of the received frame is 0x8808 and the OPCODE field is 0x0001.

DBF When this bit is set, the AFM(Address Filtering Module) module blocks all incoming broadcast
frames. In addition, it overrides all other filter settings. When this bit is reset, the AFM module
passes all received broadcast frames. (R/W)

PAM When set, this bit indicates that all received frames with a multicast destination address (first bit
in the destination address field is ’1’) are passed. (R/W)

Continued on the next page...

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10. Ethernet MAC

Register 10.16: EMACFF_REG (0x1004)

Continued from the previous page...

DAIF When this bit is set, the Address Check block operates in inverse filtering mode for the DA
address comparison for both unicast and multicast frames. When reset, normal filtering of frames
is performed. (R/W)

PMODE When this bit is set, the Address Filter module passes all incoming frames irrespective of the
destination or source address. The SA or DA Filter Fails status bits of the Receive Status Word are
always cleared when PR(PRTR AT IO)isset.(R/W )

Register 10.17: EMACMIIADDR_REG (0x1010)