Futuristic Transistor Technology below 5nm node

By Pavan H Vora, Akash Verma, Dhaval Parikh

The ‘Semiconductor era’ started in 1960 with the invention of integrated circuit. All the active-passive
components and their interconnection are integrated on single silicon wafer, offering numerous advantages
in terms of portability, functionality, power and performance. VLSI industry is following Moore’s law since
many decades, “number of transistor on a chip becomes double approximately every two year”. To get the
benefits of scaled down transistor, VLSI industry is continuously improving transistor structure & material,
manufacturing techniques and tools for designing IC. Various technique which have been adopted for
transistor so far are high-K dielectric, metal gate, strained silicon, double pattering, controlling channel
from more than one side, silicon on insulator and many more techniques. Many of the techniques are
discussed in [1].
Nowadays internet of things, autonomous vehicle, machine learning, artificial intelligence, and internet
traffic is growing exponentially which act as a driving force for scaling down transistor below existing 7nm
node for higher performance.
I) Issues with Sub-Micron Technology:
Every time we scale down transistor size, we say new technology node is generated like 28nm, 16nm.
Scaling down transistor enables faster switching, higher density, low power consumption, lower the cost
per transistor, and numerous other gains. CMOS transistor base IC technology is performing well up to
28nm node. The short channel effects becomes uncontrollable if we shrink down CMOS transistor below
28 nm. Below this node, a horizontal electric field generated by drain-source supply tries to govern the
channel. As a result gate is unable to control leakage paths which are far from gate.
II) 16nm/7nm Transistor Technology: FinFet and FD-SOI:
VLSI industry have adopted FinFET and SOI transistor for present 16nm-7nm node, as both structure are
able to prevent leakage issue at these nodes. The main objective of both the structures is to maximize gate-
to-channel capacitance and minimize drain-to-channel capacitance [1]. In both transistor structure channel
thickness scaling is introduced as new scaling parameter. As channel thickness is reduces, there is no paths
which are far from the gate area. Thus gate have good control over channel which eliminates short channel
effects.
In Silicon-on-Insulator transistor, buried oxide layer is used which isolates body from substrate shown in
Figure 1(a). Owing to BOX layer, drain-source parasitic junction capacitances are reduced which results
into faster switching. The main challenge with SOI transistor is that, it is difficult to manufacture thin
silicon layer on wafer.

Figure 1: a) FD-SOI Structure b) FinFET Structure and Channel

FinFET which is also called tri-gate controls channel from three sides as shown in Figure 1(b). There is
thin vertical Si-body which looks like back fin of fish wrapped by gate structure. A width of the channel is
almost two times Fin height. Thus to get higher driving strength, multi-Fin structure is used. One of the
gain with FinFET is higher driving current. Main challenge with FinFET is Complex manufacturing
process.
III) Challenges with Technology Node below 5nm: What Next?
Reducing body thickness results into lower mobility as surface roughness scattering is increasing. Since
FinFET is 3-D structure, it is less efficient in terms of thermal dissipation. Also if we scale down FinFET
transistor size further say below 7nm, leakage issue becomes dominant again. Consequently many other
problems comes into consideration like self-heating, threshold flattening. These concerns leads to research
on other possible transistor structure and replacing existing material with new effective materials.
According to ITRS roadmap, next technology nodes are 5nm, 3nm, 2.5nm and 1.5nm. There are many
different research and study are going on in VLSI industry and academia for potential solutions. Here we
discuss some promising solution for future technology node like carbon nanotube FET, GAA transistor
structure, compound semiconductor.

Figure 2: Transistor Technology Roadmap

IV) CNTFET - Carbon Nano Tube FET:
CNT (Carbon Nanotubes) showcase a new class of semiconductor materials that consists of single sheet of
carbon atoms rolled up to form tubular structure. CNTFET is a field-effect transistor (FET) that uses
semiconducting CNT as channel material between the two metal electrodes which behave as source and
drain contacts. Here we will discuss carbon nanotube material and how it is beneficial to FET at lower
technology node.
A) What Is Carbon Nanotube?
CNT is a tubular shaped material, made of carbon, having diameter measurable on the nanometer scale.
They have long and hollow structure and are formed from sheets of carbon that are one atom thick. It is
called as “Graphene”. Carbon nanotubes have varied structures, differing in length, thickness, helicity, and
number of layers. Majorly, they are classified as Single Walled Carbon Nanotube (SWCNT) and Multi-
Walled Carbon Nanotube (MWCNT). As shown in Figure 3(a), one can see that SWCNTs are made up of
single layer of graphene, whereas MWCNTs are made up of multiple layers of grapheme.

Figure 3: a) Single Walled and Multi Walled CNTs b) Chirality Vector Representation
B) Properties of Carbon Nanotube:
The carbon nanotube delivers excellent properties in areas of thermal and physical stability discussed below.
1. Both Metallic and Semiconductor Behavior
The CNT can exhibit metallic and semiconductor behavior. This change in behavior depends on the
direction in which the graphene sheet is rolled. It is termed as chirality vector. This vector is denoted by a
pair of integer (n, m) as shown in Figure 3(b). The CNT behaves as metallic if ‘n’ equals to ‘m’ or the
difference of ‘n’ and ‘m’ is the integral multiple of three or else it behaves as semiconducting [2].
2. Incredible Mobility
SWCNTs have a great potential for application in electronics because of their capacity to behave as either
metal or as a semiconductor, symmetric conduction and their capacity to carry large currents. Electrons and
holes have a high current density along the length of a CNT due to the low scattering rates along the CNT
axis. CNTs can carry current around 10 A/nm2, while standard metal wires have a current carrying capacity
that is only around 10 nA/nm2 [3].
3. Excellent Heat Dissipation
Thermal management is an important parameter for electronic devices performance. Carbon nanotubes
(CNTs) are well-known nanomaterials for excellent heat dissipation. Moreover, they have less effect of the
rise in temperature on the I-V characteristics as compared to silicon [4].
C) CNT in Transistor Applications: CNFET
The bandgap of carbon nanotubes can be changed by its chirality and diameter and thus carbon nanotube
can be made to behave as a semiconductor. Semiconducting CNTs can be a favorable candidate for
nanoscale transistor devices for channel material as it offers numerous advantages over traditional silicon-
MOSFETs. Carbon nanotubes conduct heat similarly to the diamond or sapphire. Also, they switch more
reliably and use much less power than silicon based device [5].
In addition, the CNFETS have four times higher trans-conductance than its counterpart. CNT can be
integrated with High-K material which is offering good gate control over channel. The carrier velocity of
CNFET is twice as compared to MOSFET, due to increased mobility. A carrier mobility of N-type and P-
type CNFET is similar offering advantages in terms of same transistor size. While in CMOS, PMOS
transistor size is approximately 2.5 times more than NMOS transistor as mobility values are different.
The Fabrication process of CNTFET is a very challenging task as it requires precision and accuracy in the
methodologies. Here we discuss the Top-gated CNTFET fabrication methodology.
The first step in this technique starts from the placement of carbon nanotubes onto silicon oxide substrate.
Then individual tube is isolated. Source and drain contacts are defined and patterned using advanced
lithography. The contact resistance is then reduced by refining connection between the contacts and CNT.
The deposition of a thin top-gate dielectric is performed on the nanotube via evaporation technique. Lastly
to complete the process, the gate contact is deposited on gate dielectric [6].

Figure 4: Concept of Carbon-Nanotube FET

D) Challenges of CNTFET:
There are lots of challenges in the roadmap of commercial CNFET technology. Majority of them have been
resolved to a certain level, but a few of them are yet to be overcome. Here we will discuss some of the
major challenges of CNTFET.
1. Contact Resistance
“For any advanced transistor technology, the increase in contact resistance due to lessen in size of transistor
becomes a major performance problem”. The performance of transistor degrade as resistance of contacts
increases significantly due to scaling down transistor. Until now, decreasing the size of the contacts on a
device caused a huge drop in execution — a challenge facing both silicon and carbon Nanotube transistor
technologies [7].
2. Synthesis of Nanotube
In-tube synthesis and to change the chirality of CNT such that it behaves as semiconductor is the biggest
challenge. The synthesized tubes have a mixture of both metals and semiconductors. But since only the
semiconducting ones are useful for qualifying to be a transistor, engineering methodologies need to be
invented to get significantly better result at separating metal tubes from semiconducting tubes.
3. To develop a non-lithographic process to place billions of these nanotubes onto the specific location of
the chip poses a challenging task.
Currently, many engineering teams are carrying out research about CNTFET devices and their logic
applications, both in the Industries and in the Universities. In the year 2015, researchers from one of the
leading semiconductor company succeeded in combining metal contacts with nanotubes using “close-
bonded contact scheme”. They achieved this by putting metal contact at the ends of the tube and making
them to react with the carbon to form a different compounds. This technique helped them to shrink contacts
below 10 nanometers without compromising performance [8].
V) Gate –All-Around FET: GAAFET
One of the futuristic potential transistor structure is Gate-all-around FET. The Gate-all-around FETs is
extended version of FinFET. In GAAFET, the gate material surrounds the channel region from the four
direction. In simple structure, a silicon nanowire as channel is wrapped by gate structure. A vertically
stacked multiple horizontal nanowires structure is proven excellent for boosting current per given area. This
concept of multiple vertically stacked gate-all-around silicon nanowire is shown in Figure 5.

Figure 5: Vertically Stacked Nanowires GAAFET

Apart from silicon material, some other materials like InGaAs, germanium nanowires can also be utilized
for better mobility.
There are many hurdles for GAAFET in terms of complex gate manufacturing, nanowires and contacts.
One of the challenging process is fabricating nanowires from silicon layer as it requires new approach for
etching process.
There are many research labs and institute working for Gate-all-around FET for lower nodes. Recently
Leuven based R&D firm claimed that they achieved excellent electrostatic control over channel with
GAAFET at sub 10nm diameter nanowire. Last year, one of the leading semiconductor company unveils
5nm chip which contains 30 billion transistor on 50mm2 chip using stacked nanowire GAAFET technology.
It claimed that you will achieve 40% improvement in performance compared to 10nm node or 70%
improvement in power consumption at same performance.
VI) Compound Semiconductors:
Another promising way to scale down transistor node is selection of novel material that exhibit higher
carrier mobility. A compound semiconductor with ingredients from columns III and V are having higher
mobility compared to silicon. Some compound semiconductor examples are Indium Gallium Arsenide
(InGaAs), Gallium Arsenide (GaAs), and Indium Arsenide (InAs). According to various studies,
integration of compound semiconductor with FinFET and GAAFET showing excellent performance at
lower nodes.
The main concerns with compound semiconductor is large lattice mismatch between silicon and III-V
semiconductor, resulting into defects of transistor channel. One of the firm developed FinFET containing
V-shaped trenches into the silicon substrate. These trenches filled with indium gallium arsenide and forming
fin of the transistor. The bottom of trench is filled with indium phosphide to reduce the leakage current.
With this trench structure it has been observed that defects terminate at the trench walls, enabling lower
defects in the channel.
VII) Conclusion:
From 22nm node to 7nm node, FinFET have been proven successfully and it may be scale down to one
more node. Beyond that there are various challenges like, self-heating, mobility degradation, threshold
flattening. We have discussed how carbon nanotube’s excellent properties of motilities, heat dissipation,
high current carrying capability offering promising solutions for replacing existing silicon technology. As
stack of horizontal nanowire opened a “fourth gate”, Gate-all-around transistor structure is also good
candidate for replacing vertical Fin structure of FinFET for achieving good electrostatic property. It’s not
clear what come next in technology roadmap. But in futuristic transistor technology that there must be
changes of existing material, structure, EUV lithography process, packaging to sustain the noose of the
Moore’s law.
VIII) References:
[1] Pavan Vora, Ronak Lad, “A Review Paper on CMOS, SOI and FinFET Technology”, www.design-
reuse.com/articles/
[2] P.A Gowri Sankar, K. Udhaya Kumar, “Investigating The Effect of Chirality On Coaxial Carbon
Nanotube Field Effect Transistor”, 2012 International Conference on Computing, Electronics and Electrical
Technologies (ICCEET)
[3] Rashmita Sahoo, S.K Sahoo, “Design of an efficient CNTFET using optimum number of CNT in
channel region for logic gate implementation”, 2015 International Conference on VLSI Systems,
Architecture, Technology and Applications (VLSI-SATA)
[4] Yijian Ouyang and Jing Guo, “Heat dissipation in carbon nanotube transistors”, Appl. Phys. Lett. 89,
183122 (2006)
[5] Philip G. Collins & Phaedon Avouris, “Nanotubes for Electronics”, Scientific American 283, 62 - 69
(2000)
[6] Wind, S. J.; Appenzeller, J.; Martel, R.; Derycke, V.; Avouris, Ph. (2002). "Vertical scaling of carbon
nanotube field-effect transistors using top gate electrodes”, Applied Physics Letters. 80 (20): 3817.
Bibcode:2002ApPhL..80.3817W.
[7] Aaron D. Franklin, Wilfried Haensch, “Defining and overcoming the contact resistance challenge in
scaled carbon nanotube transistors”, 72nd Device Research Conference
[8] IBM, “IBM Research Breakthrough Paves Way for Post-Silicon Future with Carbon Nanotube
Electronics”, https://www-03.ibm.com/press/us/en/pressrelease/47767.wss