Low Power, 165 MHz HDMI Receiver

Data Sheet ADV7610

FEATURES FUNCTIONAL BLOCK DIAGRAM
High-Definition Multimedia Interface (HDMI®)
All mandatory and additional 3D video formats supported HS/VS HS

OUTPUT MUX
HDCP VS/FIELD
Extended colorimetry, including sYCC601, Adobe RGB, KEYS
COMPONENT
FIELD/DE
DE
Adobe YCC 601, and xvYCC extended gamut color 36 PROCESSOR LLC LLC
DATA 24-BIT
CEC 1.4-compatible YCbCr/RGB

HDMI receiver HDMI1 TMDS DEEP

COLOR 4 I2S
LRCLK
165 MHz maximum transition-minimized differential DDC HDMI Rx

OUTPUT MUX
S/PDIF
I2S
signaling (TMDS) clock frequency MCLK
MCLK
24-bit output pixel bus SCLK
SCLK
LRCLK
High-bandwidth Digital Content Protection (HDCP) 1.4
support with internal high definition copy protocol

10775-001
(HDCP) keys ADV7610

HDCP repeater support: up to 127 KSVs supported Figure 1.

Integrated consumer electronics control (CEC) controller
Programmable HDMI equalizer
5 V detect and Hot Plug™ assert for HDMI port
Audio support
S/PDIF (IEC 60958-compatible) digital audio
HDMI audio extraction support
Advanced audio mute feature
I2S, 4 streams for 8 channels
General
Interrupt controller with two interrupt outputs
Standard identification (STDI) circuit
Highly flexible 24-bit pixel output interface
Internal extended display identification data (EDID) RAM
Any-to-any 3 × 3 color space conversion (CSC) matrix
2-layer printed circuit board (PCB) design supported
76-ball, 6 mm × 6 mm, chip-scale package BGA

APPLICATIONS
Portable applications
Pico projectors
Digital video cameras

Rev. 0 Document Feedback

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Trademarks and registered trademarks are the property of their respective owners. Technical Support www.analog.com
ADV7610 Data Sheet

TABLE OF CONTENTS
Features .............................................................................................. 1 Power Supply Sequencing ............................................................. 10
Applications ....................................................................................... 1 Power-Up Sequence ................................................................... 10
Functional Block Diagram .............................................................. 1 Power-Down Sequence .............................................................. 10
Revision History ............................................................................... 2 Functional Overview...................................................................... 11
General Description ......................................................................... 3 HDMI Receiver........................................................................... 11
Detailed Functional Block Diagram .......................................... 3 Component Processor (CP) ...................................................... 11
Specifications..................................................................................... 4 Other Features ............................................................................ 11
Electrical Characteristics ............................................................. 4 Pixel Input/Output Formatting .................................................... 12
Data and I C Timing Characteristics ......................................... 5
2
Pixel Data Output Modes Features .......................................... 12
Absolute Maximum Ratings ............................................................ 7 Outline Dimensions ....................................................................... 14
Package Thermal Performance ................................................... 7 Ordering Guide .......................................................................... 14
ESD Caution .................................................................................. 7
Pin Configuration and Function Descriptions ............................. 8

REVISION HISTORY
12/12—Revision 0: Initial Version

Rev. 0 | Page 2 of 16
Data Sheet ADV7610

GENERAL DESCRIPTION
The ADV7610 is offered in professional (no HDCP) and industrial The HDMI port has dedicated 5 V detect and Hot Plug assert pins.
versions. The operating temperature range is −40°C to +85°C. The HDMI receiver also includes an integrated equalizer that
The ADV7610 is a high quality, single input HDMI-capable ensures the robust operation of the interface with long cables.
receiver. It incorporates an HDMI-capable receiver that supports The ADV7610 contains one main component processor (CP)
all mandatory 3D TV defined in HDMI specification. The that processes the video signals from the HDMI receiver. It
ADV7610 supports formats up to UXGA 60 Hz at eight bits. provides features such as contrast, brightness, saturation
It integrates a CEC controller that supports the capability adjustments, STDI detection block, free run, and synchronization
discovery and control (CDC) feature. alignment controls.

The ADV7610 has a 4-channel stereo audio output port for the Fabricated in an advanced CMOS process, the ADV7610 is provided
audio data extracted from the HDMI stream. The HDMI receiver in a 6 mm × 6 mm, 76-ball CSP_BGA, RoHS-compliant package
has an advanced mute controller that prevents audible extraneous and is specified over the −40°C to +85°C temperature range.
noise in the audio output.
The following audio formats are accessible:
• Four streams from the I2S serializer (eight channels)
• A stream from the S/PDIF serializer (two uncompressed
channels or N compressed channels, for example, AC3)
• A DST stream

DETAILED FUNCTIONAL BLOCK DIAGRAM

XTALP
XTALN DPLL
12

OUTPUT FORMATTER
P0 TO P7
12
SCL P8 TO P15
SDA 12
CONTROL P16 TO P23
INTERFACE LLC
CEC I2C BACKEND
CEC CONTROLLER COLORSPACE
CONVERSION HS
CONTROL VS/FIELD/ALSB
AND DATA
5V DETECT DE
RXA_5V AND HPD
HPA_A/INT2* CONTROLLER
INTERRUPT INT1
CONTROLLER INT2*
HDMI (INT1, INT2)
EDID PROCESSOR
DDCA_SDA REPEATER COMPONENT
DDCA_SCL
AUDIO OUTPUT FORMATTER

CONTROLLER PROCESSOR
A
DATA B
HDCP PREPROCESOR 4
EEPROM C I2S0 TO I2S3
AND COLOR-
RXA_C± PLL SPACE
CONVERSION
PACKET/ LRCLK
RXA_0± INFOFRAME SCLK/INT2*
EQUALIZER SAMPLER HDCP
RXA_1± ENGINE MEMORY MUTE
RXA_2± PACKET MCLK/INT2*
PROCESSOR AUDIO
PROCESSOR

ADV7610
10775-002

*INT2 CAN BE OUTPUT ON ONE OF THE FOLLOWING PINS ONLY: SCLK/INT2, MCLK/INT2, OR HPA_A/INT2.

Figure 2. Detailed Functional Block Diagram

Rev. 0 | Page 3 of 16
ADV7610 Data Sheet

SPECIFICATIONS
DVDD = 1.71 V to 1.89 V, DVDDIO = 3.14 V to 3.46 V, PVDD = 1.71 V to 1.89 V, TVDD = 3.14 V to 3.46 V, CVDD = 1.71 V to 1.89 V,
TMIN to TMAX = −40°C to +85°C, unless otherwise noted.
ELECTRICAL CHARACTERISTICS
Table 1.
Parameter Symbol Test Conditions/Comments Min Typ Max Unit
DIGITAL INPUTS 1
Input High Voltage VIH XTALN and XTALP 1.2 V
VIH Other digital inputs 2 V
Input Low Voltage VIL XTALN and XTALP 0.4 V
VIL Other digital inputs 0.8 V
Input Current IIN RESET pin ±45 ±60 µA
Other digital inputs ±10 µA
Input Capacitance CIN 10 pF
DIGITAL INPUTS (5 V TOLERANT)1, 2
Input High Voltage VIH 2.6 V
Input Low Voltage VIL 0.8 V
Input Current IIN −82 +82 µA
DIGITAL OUTPUTS1
Output High Voltage VOH 2.4 V
Output Low Voltage VOL 0.4 V
High Impedance Leakage Current ILEAK VS/FIELD/ALSB pin ±35 ±60 µA
HPA_A/INT2 pin ±82 µA
Other 10 µA
Output Capacitance COUT 20 pF
POWER REQUIREMENTS 3
Digital Core Power Supply DVDD 1.71 1.8 1.89 V
Digital I/O Power Supply DVDDIO 3.14 3.3 3.46 V
PLL Power Supply PVDD 1.71 1.8 1.89 V
Terminator Power Supply TVDD 3.14 3.3 3.46 V
Comparator Power Supply CVDD 1.71 1.8 1.89 V
Digital Core Supply Current IDVDD UXGA 60 Hz at eight bits 95.7 188.1 mA
Digital I/O Supply Current IDVDDIO UXGA 60 Hz at eight bits 12.9 178.5 mA
PLL Supply Current IPVDD UXGA 60 Hz at eight bits 30.7 36.9 mA
Terminator Supply Current ITVDD UXGA 60 Hz at eight bits 50.9 57.6 mA
Comparator Supply Current ICVDD UXGA 60 Hz at eight bits 95.8 114.4 mA
POWER-DOWN CURRENTS 4
Digital Core Supply Current IDVDD_PD Power-Down Mode 1 0.2 0.5 mA
Digital I/O Supply Current IDVDDIO_PD Power-Down Mode 1 1.3 1.7 mA
PLL Supply Current IPVDD_PD Power-Down Mode 1 1.5 1.8 mA
Terminator Supply Current ITVDD_PD Power-Down Mode 1 0.1 0.3 mA
Comparator Supply Current ICVDD_PD Power-Down Mode 1 1.3 1.7 mA
Power-Up Time tPWRUP 25 ms
1
Data guaranteed by characterization.
2
The following pins are 5 V tolerant: DDCA_SCL, DDCA_SDA, and RXA_5V.
3
Maximum current consumption values are recorded with maximum rated voltage supply levels, Moire X video pattern, and at maximum rated temperature.
4
Power-Down Mode 0 (I/O map, Register 0x0C = 0x62), ring oscillator powered down (HDMI map, Register 0x48 = 0x01), and DDC pads off (HDMI map, Register 0x73 = 0x01).

Rev. 0 | Page 4 of 16
Data Sheet ADV7610
DATA AND I2C TIMING CHARACTERISTICS
Table 2.
Parameter Symbol Test Conditions/Comments Min Typ Max Unit
CLOCK AND CRYSTAL
Crystal Frequency, XTALP 28.63636 MHz
Crystal Frequency Stability ±50 ppm
LLC Frequency Range 1 13.5 165 MHz
I2C PORTS
SCL Frequency 400 kHz
SCL Minimum Pulse Width High 2 t1 600 ns
SCL Minimum Pulse Width Low2 t2 1.3 µs
Start Condition Hold Time2 t3 600 ns
Start Condition Setup Time2 t4 600 ns
SDA Setup Time2 t5 100 ns
SCL and SDA Rise Time2 t6 300 ns
SCL and SDA Fall Time2 t7 300 ns
Stop Condition Setup Time2 t8 0.6 µs
RESET FEATURE
RESET Pulse Width 5 ms
CLOCK OUTPUTS
LLC Mark:Space Ratio2 t9:t10 45:55 55:45 % duty cycle
DATA AND CONTROL OUTPUTS 3
Data Output Transition Time2, 4 t11 End of valid data to negative clock edge 1.0 2.2 ns
t12 Negative clock edge to start of valid data 0.0 0.3 ns
I2S PORT, MASTER MODE
SCLK Mark:Space Ratio2 t15:t16 45:55 55:45 % duty cycle
LRCLK Data Transition Time2 t17 End of valid data to negative SCLK edge 10 ns
LRCLK Data Transition Time2 t18 Negative SCLK edge to start of valid data 10 ns
I2S Data Transition Time2 t19 End of valid data to negative SCLK edge 5 ns
I2S Data Transition Time2 t20 Negative SCLK edge to start of valid data 5 ns
1
Maximum LLC frequency is limited by the clock frequency of UXGA 60 Hz at eight bits.
2
Data guaranteed by characterization.
3
With the DLL block on the output clock bypassed.
4
DLL bypassed on the clock path.

Rev. 0 | Page 5 of 16
ADV7610 Data Sheet
Timing Diagrams
t3 t5 t3

SDA

t6 t1
SCL

10775-003
t2 t7 t4 t8
2
Figure 3. I C Timing

t9 t10

LLC

t11
t12

10775-004
P0 TO P23, HS,
VS/FIELD/ALSB, DE

Figure 4. Pixel Port and Control SDR Output Timing

t15
SCLK
t16
t17
LRCLK

t18

I2S t19
LEFT-JUSTIFIED
MODE MSB MSB – 1

t20
t19
I2S
I2S MODE MSB MSB – 1

t20
I2S t19
RIGHT-JUSTIFIED
MODE MSB LSB
10775-005

t20

Figure 5. I2S Timing

Rev. 0 | Page 6 of 16
Data Sheet ADV7610

ABSOLUTE MAXIMUM RATINGS

Table 3. PACKAGE THERMAL PERFORMANCE
Parameter Rating To reduce power consumption when using the ADV7610, turn
DVDD to GND 2.2 V off the unused sections of the part.
PVDD to GND 2.2 V Due to the PCB metal variation and, therefore, variation in PCB
DVDDIO to GND 4.0 V heat conductivity, the value of θJA may differ for various PCBs.
CVDD to GND 2.2 V
The most efficient measurement solution is obtained using the
TVDD to GND 4.0 V
package surface temperature to estimate the die temperature
Digital Inputs Voltage to GND GND − 0.3 V to DVDDIO + 0.3 V
because this eliminates the variance associated with the θJA value.
5 V Tolerant Digital Inputs to 5.3 V
GND1 Do not exceed the maximum junction temperature (TJ MAX) of
Digital Outputs Voltage to GND GND − 0.3 V to DVDDIO + 0.3 V 125°C. The following equation calculates the junction temperature
XTALP, XTALN GND − 0.3 V to PVDD + 0.3 V using the measured package surface temperature, and it applies
SCL/SDA Data Pins to DVDDIO DVDDIO − 0.3 V to only when a heat sink is not used on the device under test (DUT):
DVDDIO + 3.6 V
TJ = TS + (ΨJT × WTOTAL)
Maximum Junction Temperature 125°C
(TJ MAX) where:
Storage Temperature Range −60°C to +150°C TS is the package surface temperature (°C).
Infrared Reflow Soldering (20 sec) 260°C ΨJT = 0.4°C/W for the 76-ball CSP_BGA.
1
The following inputs are 3.3 V inputs but are 5 V tolerant: DDCA_SCL, DDCA_SDA, WTOTAL = ((PVDD × IPVDD) + (0.05 × TVDD × ITVDD) +
and RXA_5V. (CVDD × ICVDD) + (DVDD × IDVDD) + (DVDDIO × IDVDDIO))
Stresses above those listed under Absolute Maximum Ratings where 0.05 is 5% of the TVDD power that is dissipated on the
may cause permanent damage to the device. This is a stress device itself.
rating only; functional operation of the device at these or any
other conditions above those indicated in the operational
section of this specification is not implied. Exposure to absolute ESD CAUTION
maximum rating conditions for extended periods may affect
device reliability.

Rev. 0 | Page 7 of 16
ADV7610 Data Sheet

PIN CONFIGURATION AND FUNCTION DESCRIPTIONS

1 2 3 4 5 6 7 8 9 10

HPA_A/ MCLK/ SCLK/

A INT2 RXA_5V DDCA_SCL PVDD XTALN XTALP INT1 INT2 DVDD
INT2

B TVDD TVDD DDCA_SDA CEC CS RESET SDA SCL LRCLK DVDD

C RXA_C+ RXA_C– I2S3 I2S1

D RXA_0+ RXA_0– GND GND GND DVDD I2S2 I2S0

VS/
E RXA_1+ RXA_1– GND DVDD FIELD/ DE
ALSB

F RXA_2+ RXA_2– GND DVDDIO HS P0

G CVDD CVDD GND GND GND DVDDIO P1 P2

H P23 P22 P3 P4

J P21 P18 P16 P15 P13 P11 P9 P7 P5 DVDDIO

K P20 P19 P17 LLC P14 P12 P10 P8 P6 DVDDIO

10775-006
Figure 6. Pin Configuration

Table 4. Pin Function Descriptions

Ball No. Mnemonic Type Description
D4, D5, D6, E4, F4, GND Ground Ground.
G4, G5, G6
A1 HPA_A/INT2 Miscellaneous digital A dual function pin that can be configured to output a Hot Plug assert signal
(for HDMI Port A) or an Interrupt 2 signal.
G1, G2 CVDD Power HDMI Analog Block Supply Voltage (1.8 V).
B1, B2 TVDD Power Terminator Supply Voltage (3.3 V).
F7, G7, J10, K10 DVDDIO Power Digital I/O Supply Voltage (3.3 V).
A10, B10, D7, E7 DVDD Power Digital Core Supply Voltage (1.8 V).
A4 PVDD Power PLL Supply Voltage (1.8 V).
C2 RXA_C− HDMI input Digital Input Clock Complement of Port A in the HDMI Interface.
C1 RXA_C+ HDMI input Digital Input Clock True of Port A in the HDMI Interface.
D2 RXA_0− HDMI input Digital Input Channel 0 Complement of Port A in the HDMI Interface.
D1 RXA_0+ HDMI input Digital Input Channel 0 True of Port A in the HDMI Interface.
E2 RXA_1− HDMI input Digital Input Channel 1 Complement of Port A in the HDMI Interface.
E1 RXA_1+ HDMI input Digital Input Channel 1 True of Port A in the HDMI Interface.
F2 RXA_2− HDMI input Digital Input Channel 2 Complement of Port A in the HDMI Interface.
F1 RXA_2+ HDMI input Digital Input Channel 2 True of Port A in the HDMI Interface.
Rev. 0 | Page 8 of 16
Data Sheet ADV7610
Ball No. Mnemonic Type Description
H1 P23 Digital video output Video Pixel Output Port.
H2 P22 Digital video output Video Pixel Output Port.
J1 P21 Digital video output Video Pixel Output Port.
K1 P20 Digital video output Video Pixel Output Port.
K2 P19 Digital video output Video Pixel Output Port.
J2 P18 Digital video output Video Pixel Output Port.
K3 P17 Digital video output Video Pixel Output Port.
J3 P16 Digital video output Video Pixel Output Port.
K4 LLC Digital video output Line Locked Output Clock for the Pixel Data the Range is 13.5 MHz to 162.5 MHz.
J4 P15 Digital video output Video Pixel Output Port.
K5 P14 Digital video output Video Pixel Output Port.
J5 P13 Digital video output Video Pixel Output Port.
K6 P12 Digital video output Video Pixel Output Port.
J6 P11 Digital video output Video Pixel Output Port.
K7 P10 Digital video output Video Pixel Output Port.
J7 P9 Digital video output Video Pixel Output Port.
K8 P8 Digital video output Video Pixel Output Port.
J8 P7 Digital video output Video Pixel Output Port.
K9 P6 Digital video output Video Pixel Output Port.
J9 P5 Digital video output Video Pixel Output Port.
H10 P4 Digital video output Video Pixel Output Port.
H9 P3 Digital video output Video Pixel Output Port.
G10 P2 Digital video output Video Pixel Output Port.
G9 P1 Digital video output Video Pixel Output Port.
F10 P0 Digital video output Video Pixel Output Port.
E10 DE Miscellaneous digital Data Enable. DE is a signal that indicates active pixel data.
F9 HS Digital video output Horizontal Synchronization Output Signal.
E9 VS/FIELD/ALSB Digital input/output Vertical Synchronization Output Signal.
Field Synchronization Output Signal in All Interlaced Video Modes.
VS or FIELD can be configured for this pin.
The ALSB allows selection of the I2C address.
D10, C10, D9, C9 I2S0 to I2S3 Miscellaneous digital Audio Output Pins. These pins can be configured to output S/PDIF digital
audio (S/PDIF) or I2S.
A9 SCLK/INT2 Miscellaneous digital A dual function pin that can be configured to output an audio serial clock or
an Interrupt 2 signal.
B9 LRCLK Miscellaneous digital Audio Left/Right Clock.
A8 MCLK/INT2 Miscellaneous digital A dual function pin that can be configured to output an audio master clock or
an Interrupt 2 signal.
B8 SCL Miscellaneous digital I2C Port Serial Clock Input. SCL is the clock line for the control port.
B7 SDA Miscellaneous digital I2C Port Serial Data Input/Output Pin. SDA is the data line for the control port.
A7 INT1 Miscellaneous digital Interrupt 1. This pin can be active low or active high. When status bits change, this
pin is triggered. The events that trigger an interrupt are under user configuration.
B6 RESET Miscellaneous digital System Reset Input. Active low. A minimum low reset pulse width of 5 ms is
required to reset the ADV7610 circuitry.
A6 XTALP Miscellaneous analog Input Pin for 28.63636 MHz Crystal or an External 1.8 V, 28.63636 MHz Clock
Oscillator Source to Clock the ADV7610.
A5 XTALN Miscellaneous analog Crystal Input. Input pin for 28.63636 MHz crystal.
B4 CEC Digital input/output Consumer Electronic Control Channel.
B5 CS Miscellaneous digital Chip Select (Bar). Pulling this line high causes the I2C state machine to ignore
the I2C transmission.
A3 DDCA_SCL HDMI input HDCP Slave Serial Clock Port A. DDCA_SCL is a 3.3 V input that is 5 V tolerant.
B3 DDCA_SDA HDMI input HDCP Slave Serial Data Port A. DDCA_SDA is a 3.3 V input that is 5 V tolerant.
A2 RXA_5V HDMI input 5 V Detect Pin for Port A in the HDMI Interface.

Rev. 0 | Page 9 of 16
ADV7610 Data Sheet

POWER SUPPLY SEQUENCING

POWER-UP SEQUENCE 3.3V 3.3V SUPPLIES

The recommended power-up sequence of the ADV7610 is to

power up the 3.3 V supplies first, followed by the 1.8 V supplies.

POWER SUPPLY (V)

Hold reset low while the supplies are powered up.
Alternatively, the ADV7610 can be powered up by asserting all 1.8V 1.8V SUPPLIES

supplies simultaneously. In this case, care must be taken while the

supplies are being established to ensure that a lower rated supply
does not rise above a higher rated supply level.
POWER-DOWN SEQUENCE
The ADV7610 supplies can be deasserted simultaneously as long as
a higher rated supply does not fall below a lower rated supply.

10775-007
3.3V SUPPLIES 1.8V SUPPLIES
POWER-UP POWER-UP

Figure 7. Recommended Power-Up Sequence

Rev. 0 | Page 10 of 16
Data Sheet ADV7610

FUNCTIONAL OVERVIEW
HDMI RECEIVER COMPONENT PROCESSOR (CP)
The receiver supports all mandatory and many optional 3D The ADV7610 has an any-to-any 3 × 3 CSC matrix. The CSC
formats. It supports HDTV formats up to UXGA at eight bits. block is placed in the output section of the component processor.
The CSC enables YPrPb-to-RGB and RGB-to-YCrCb conversions.
The HDMI-compatible receiver on the ADV7610 incorporates
Many other standards of colorspace can be implemented using
programmable equalization of the HDMI data signals. This
the colorspace converter.
equalization compensates for the high frequency losses inherent
in HDMI and DVI cabling, especially at longer lengths and higher CP features include:
frequencies. It is capable of equalizing for cable lengths of up to • 525i, 625i, 525p, 625p, 720p, 1080i, 1080p, and other formats
30 meters to achieve robust receiver performance. • Manual adjustments including gain (contrast) and offset
With the inclusion of HDCP, displays can receive encrypted (brightness), hue, and saturation
video content. The HDMI interface of the ADV7610 allows for • Free run output mode that provides stable timing when no
authentication of a video receiver, decryption of encoded data at video input is present
the receiver, and renewability of that authentication during • 162.5 MHz processing rate
transmission, as specified by the HDCP 1.4 protocol. • Contrast, brightness, hue, and saturation controls
The ADV7610 has a synchronization regeneration block to • Standard identification enabled by STDI block
regenerate the DE based on the measurement of the video • RGB that can be color space converted to YCrCb and
format being displayed and to filter the horizontal and vertical decimated to a 4:2:2 format for videocentric back-end IC
synchronization signals to prevent glitches. The HDMI receiver interfacing
also supports TERC4 error detection for detection of corrupted • DE output signal supplied for direct connection to an
HDMI packets following a cable disconnect. HDMI/DVI transmitter
The HDMI receiver contains an audio mute controller that can OTHER FEATURES
detect a variety of conditions that may result in audible extraneous
The ADV7610 has HS, VS, FIELD, and DE output signals with
noise in the audio output. On detection of these conditions, the
programmable position, polarity, and width.
audio signal can be ramped to prevent audio clicks or pops.
Audio output can be formatted to LPCM and IEC 61937. The ADV7610 has programmable interrupt request output pins,
including INT1 and INT2 (INT2 is accessible only via one of
The HDMI receiver features include:
following pins: MCLK/INT2, SCLK/INT2, or HPA_A/INT2).
• 162.5 MHz (UXGA at eight bits) maximum TMDS clock It also features a low power-down mode. The I2C address of the
frequency main map is 0x98 after reset. This can be changed after reset to
• 3D format support defined in the HDMI specification 0x9A if pull-up is attached to the VS/FIELD/ALSB pin and the
• Integrated equalizer for cable lengths of up to 30 meters I2C command SAMPLE_ALSB is issued.
• HDCP 1.4 The ADV7610 is provided in a 6 mm × 6 mm, RoHS-compliant
• Internal HDCP keys BGA package and is specified over the −40°C to +85°C
• PCM audio packet support temperature range.
• TDM I2S audio packet support For more detailed product information about the ADV7610,
• Repeater support contact the local Analog Devices, Inc., sales office.
• Internal EDID RAM
• Hot Plug assert output pin for an HDMI port
• CEC controller

Rev. 0 | Page 11 of 16
ADV7610 Data Sheet

PIXEL INPUT/OUTPUT FORMATTING

The output section of the ADV7610 is highly flexible. The pixel PIXEL DATA OUTPUT MODES FEATURES
output bus can support up to 24-bit 4:4:4 YCrCb. The pixel data The output pixel port features include:
supports both single data rate mode and double data rate mode. In
SDR mode, a 16-/24-bit 4:2:2 or 24-bit 4:4:4 output is possible. • 8-/12-bit ITU-R BT.656 4:2:2 YCrCb with embedded time
In DDR mode, the pixel output port can be configured in an 8-/12- codes and/or HS, VS, and FIELD output signals
bit 4:2:2 YCrCb or 24-bit 4:4:4 RGB. • 16-/24-bit YCrCb with embedded time codes and/or HS
and VS/FIELD pin timing
Bus rotation is supported. Table 5 and Table 6 outline the various
• 24-bit YCrCb/RGB with embedded time codes and/or HS
output formats that are supported. All output modes are controlled
and VS/FIELD pin timing
via I2C.
• DDR 8-/12-bit 4:2:2 YCrCb
• DDR 24-bit 4:4:4 RGB

Table 5. SDR 4:2:2 and 4:4:4 Output Modes

SDR 4:2:2 SDR 4:4:4
OP_FORMAT_SEL[7:0] 0x0 0x0A 0x80 0x8A 0x40
8-Bit SDR 12-Bit SDR 16-Bit SDR 24-Bit SDR
ITU-R BT.656 ITU-R BT.656 ITU-R BT.656 4:2:2 ITU-R BT.656 4:2:2 24-Bit SDR 4:4:4
Pixel Output Mode 0 Mode 2 Mode 0 Mode 2 Mode 0
P23 High-Z Y3, Cb3, Cr3 High-Z Y3 R7
P22 High-Z Y2, Cb2, Cr2 High-Z Y2 R6
P21 High-Z Y1, Cb1, Cr1 High-Z Y1 R5
P20 High-Z Y0, Cb0, Cr0 High-Z Y0 R4
P19 High-Z High-Z High-Z Cb3, Cr3 R3
P18 High-Z High-Z High-Z Cb2, Cr2 R2
P17 High-Z High-Z High-Z Cb1, Cr1 R1
P16 High-Z High-Z High-Z Cb0, Cr0 R0
P15 Y7, Cb7, Cr7 Y11, Cb11, Cr11 Y7 Y11 G7
P14 Y6, Cb6, Cr6 Y10, Cb10, Cr10 Y6 Y10 G6
P13 Y5, Cb5, Cr5 Y9, Cb9, Cr9 Y5 Y9 G5
P12 Y4, Cb4, Cr4 Y8, Cb8, Cr8 Y4 Y8 G4
P11 Y3, Cb3, Cr3 Y7, Cb7, Cr7 Y3 Y7 G3
P10 Y2, Cb2, Cr2 Y6, Cb6, Cr6 Y2 Y6 G2
P9 Y1, Cb1, Cr1 Y5, Cb5, Cr5 Y1 Y5 G1
P8 Y0, Cb0, Cr0 Y4, Cb4, Cr4 Y0 Y4 G0
P7 High-Z High-Z Cb7, Cr7 Cb11, Cr11 B7
P6 High-Z High-Z Cb6, Cr6 Cb10, Cr10 B6
P5 High-Z High-Z Cb5, Cr5 Cb9, Cr9 B5
P4 High-Z High-Z Cb4, Cr4 Cb8, Cr8 B4
P3 High-Z High-Z Cb3, Cr3 Cb7, Cr7 B3
P2 High-Z High-Z Cb2, Cr2 Cb6, Cr6 B2
P1 High-Z High-Z Cb1, Cr1 Cb5, Cr5 B1
P0 High-Z High-Z Cb0, Cr0 Cb4, Cr4 B0

Rev. 0 | Page 12 of 16
Data Sheet ADV7610
Table 6. DDR 4:2:2 and 4:4:4 Output Modes
DDR 4:2:2 Mode (Clock/2) DDR 4:2:2 Mode (Clock/2) DDR 4:4:4 Mode (Clock/2) 1, 2
OP_FORMAT_SEL[7:0] 0x20 0x2A 0x60
8-Bit DDR ITU-656 12-Bit DDR ITU-656 24-Bit DDR RGB
(Clock/2 Output) 4:2:2 Mode 0 (Clock/2 Output) 4:2:2 Mode 2 (Clock/2 Output)
Pixel Output Clock Rise Clock Fall Clock Rise Clock Fall Clock Rise Clock Fall
P23 High-Z High-Z Cb3, Cr3 Y3 R7-0 R7-1
P22 High-Z High-Z Cb2, Cr2 Y2 R6-0 R6-1
P21 High-Z High-Z Cb1, Cr1 Y1 R5-0 R5-1
P20 High-Z High-Z Cb0, Cr0 Y0 R4-0 R4-1
P19 High-Z High-Z High-Z High-Z R3-0 R3-1
P18 High-Z High-Z High-Z High-Z R2-0 R2-1
P17 High-Z High-Z High-Z High-Z R1-0 R1-1
P16 High-Z High-Z High-Z High-Z R0-0 R0-1
P15 Cb7, Cr7 Y7 Cb11, Cr11 Y11 G7-0 G7-1
P14 Cb6, Cr6 Y6 Cb12, Cr12 Y12 G6-0 G6-1
P13 Cb5, Cr5 Y5 Cb9, Cr9 Y9 G5-0 G5-1
P12 Cb4, Cr4 Y4 Cb8, Cr8 Y8 G4-0 G4-1
P11 Cb3, Cr3 Y3 Cb7, Cr7 Y7 G3-0 G3-1
P10 Cb2, Cr2 Y2 Cb6, Cr6 Y6 G2-0 G2-1
P9 Cb1, Cr1 Y1 Cb5, Cr5 Y5 G1-0 G1-1
P8 Cb0, Cr0 Y0 Cb4, Cr4 Y4 G0-0 G0-1
P7 High-Z High-Z High-Z High-Z B7-0 B7-1
P6 High-Z High-Z High-Z High-Z B6-0 B6-1
P5 High-Z High-Z High-Z High-Z B5-0 B5-1
P4 High-Z High-Z High-Z High-Z B4-0 B4-1
P3 High-Z High-Z High-Z High-Z B3-0 B3-1
P2 High-Z High-Z High-Z High-Z B2-0 B2-1
P1 High-Z High-Z High-Z High-Z B1-0 B1-1
P0 High-Z High-Z High-Z High-Z B0-0 B0-1
1
-0 = even samples.
2
-1 = odd samples.

Rev. 0 | Page 13 of 16
ADV7610 Data Sheet

OUTLINE DIMENSIONS
6.10 A1 CORNER
INDEX AREA
6.00 SQ
5.90 10 9 8 7 6 5 4 3 2 1

A
B
BALL A1 C
PAD CORNER 4.50
D
BSC SQ
E
TOP VIEW 0.50 F
BSC G
H
J
K

0.75 BOTTOM VIEW

DETAIL A REF
*1.40 MAX
DETAIL A
0.65 MIN
0.15 MIN

COPLANARITY
0.35 SEATING 0.08 MAX
0.30 PLANE
0.25
BALL DIAMETER

010807-A
*COMPLIANT TO JEDEC STANDARDS MO-225
WITH THE EXCEPTION TO PACKAGE HEIGHT.

Figure 8. 76-Ball Chip Scale Package Ball Grid Array [CSP_BGA]

(BC-76-1)
Dimensions shown in millimeters

ORDERING GUIDE
Temperature Package
Model 1 Range Package Description Option
ADV7610BBCZ −40°C to +85°C 76-Ball Chip Scale Package Ball Grid Array [CSP_BGA] BC-76-1
ADV7610BBCZ-RL −40°C to +85°C 76-Ball Chip Scale Package Ball Grid Array [CSP_BGA], 13” Tape and Reel BC-76-1
ADV7610BBCZ-P −40°C to +85°C 76-Ball Chip Scale Package Ball Grid Array [CSP_BGA], NonHDCP Version BC-76-1
ADV7610BBCZ-P-RL −40°C to +85°C 76-Ball Chip Scale Package Ball Grid Array [CSP_BGA], 13” Tape and Reel, NonHDCP Version BC-76-1
1
Z = RoHS Compliant Part.

Rev. 0 | Page 14 of 16
Data Sheet ADV7610

NOTES

Rev. 0 | Page 15 of 16
ADV7610 Data Sheet

NOTES

The terms HDMI and HDMI High-Definition Multimedia Interface, and the HDMI logo are trademarks or registered trademarks of HDMI Licensing LLC in the United
States and other countries.

©2012 Analog Devices, Inc. All rights reserved. Trademarks and

registered trademarks are the property of their respective owners.
D10775-0-12/12(0)

Rev. 0 | Page 16 of 16